CN110943124A - IGBT chip and manufacturing method thereof - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The present disclosure relates to an IGBT chip and a method of manufacturing the same. The IGBT chip comprises a collector layer, a cut-off layer of a first conduction type, a drift region of the first conduction type, an active region and emitter metal which are sequentially stacked, wherein the active region comprises a grid oxide layer, an emitter of the first conduction type, a contact region of a second conduction type, an insulating isolation layer, two grid grooves, M deep groove grids arranged between the two grid grooves at intervals and M +1 well regions of the second conduction type, M is an integer, and M is greater than or equal to 1, each deep trench gate is separated from the drift region by a gate oxide layer and from the adjacent well region by a gate oxide layer, each gate trench is separated from the adjacent well region by a gate oxide layer, and the M +1 well regions are respectively separated from two adjacent grid electrode grooves by the emitter and the insulating isolation layer.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to an IGBT chip and a manufacturing method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power Semiconductor device composed of a Bipolar Junction Transistor (BJT) and an Insulated Gate Field Effect Transistor (MOS), and has the advantages of both high input impedance of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and low on-state voltage drop of a power Transistor (Giant Transistor, GTR).
The IGBT includes a trench gate IGBT and a planar gate IGBT. Compared with a planar gate IGBT, the trench gate IGBT has smaller conduction voltage drop and stronger latch-up resistance, and is the mainstream in the current IGBT application. In the related art, the depth of the trench gate is proportional to the conduction voltage drop of the device, but the deeper the trench gate, the larger the miller capacitance of the device, and the greater the influence on the switching characteristics of the device. If deep trenches are used to reduce miller capacitance, the channel resistance is higher, which also increases the turn-on voltage drop. Therefore, the conduction voltage drop and the switching loss can only be considered in a compromise according to practical application. It is difficult to reduce the conduction voltage drop and to reduce the switching loss.
Disclosure of Invention
The purpose of the present disclosure is to provide a simple and practical IGBT chip and a manufacturing method thereof.
In order to achieve the above object, the present disclosure provides an IGBT chip including a collector layer, a turn-off layer of a first conductivity type, a drift region of the first conductivity type, an active region, an emitter metal, which are sequentially stacked,
the active region comprises a grid electrode oxidation layer, an emitting electrode of the first conduction type, a contact region of the second conduction type, an insulating isolation layer, two grid electrode grooves, M deep groove grids arranged between the two grid electrode grooves at intervals and M +1 well regions of the second conduction type, M is an integer and is more than or equal to 1,
each deep trench gate is separated from the drift region by the gate oxide layer and is separated from an adjacent well region by the gate oxide layer, each gate trench is separated from an adjacent well region by the gate oxide layer and is separated from the emitter metal by the insulating isolation layer, each deep trench gate is in contact with the emitter metal, each well region is separated from the emitter metal by the contact region, and two well regions adjacent to the two gate trenches in the M +1 well regions are separated from the insulating isolation layer by the emitters.
Optionally, the cut-off layer is lightly doped with a doping concentration of 1 × 1014㎝-3～5×1015㎝-3。
Optionally, the drift region is lightly doped with a doping concentration of 1 × 1013㎝-3～2×1014㎝-3。
Optionally, the contact region is heavily doped with a doping concentration of 1 × 1020㎝-3～1×1022㎝-3。
Optionally, the emitter is heavily doped with a doping concentration of 1 × 1020㎝-3～1×1022㎝-3。
The present disclosure also provides a method of manufacturing an IGBT chip, the method including:
providing a substrate of a first conduction type as a drift region, and growing a field oxide layer on the drift region; etching to remove the field oxide layer, injecting donor impurities, and depositing a first dielectric layer;
opening a deep trench gate region and a gate region on the first dielectric layer by photoetching, and etching (M +2) shallow trenches in the deep trench gate region and the gate region by using the first dielectric layer as a mask;
depositing a second dielectric layer, etching the second dielectric layer, and etching the M shallow trenches into M deep trenches by using the first dielectric layer and the second dielectric layer as masks, so that the M deep trenches are arranged between two shallow trenches;
etching to remove the second dielectric layer and the first dielectric layer, growing a gate oxide layer, depositing doped polysilicon, and filling the M deep trenches and the two shallow trenches;
etching the doped polysilicon and the grid oxide layer to expose M deep trench gates, two grid grooves and a drift region;
injecting impurities of a second conduction type into the exposed drift region and pushing the impurities to form M +1 well regions, so that M deep trench gates and M +1 well regions of the second conduction type are arranged alternately between the two gate grooves, injecting impurities of the first conduction type into each well region and activating to form an emitter of the first conduction type;
depositing an insulating isolation layer, etching the insulating isolation layer and the emitter until M +1 well regions and M deep trench gates are exposed, and injecting impurities of the second conductivity type into each well region to form a contact region of the second conductivity type and activate the contact region;
depositing emitter metal;
and implanting impurities of the first conduction type at one side of the drift region, activating and forming a cut-off layer of the first conduction type, implanting impurities of the second conduction type, and activating and forming a collector layer.
By the technical scheme, the shallow trench gate is used as the gate electrode trench, so that the device has smaller Miller capacitance and better switching characteristic; a switching system with small channel resistance and small Miller capacitance is formed by the grid electrode formed by the shallow trench and the well region, and has low conduction voltage drop and switching loss; the two sides of the first conductive type region below the shallow trench gate are both provided with the deep trench gates, and under the action of the deep trench gates, the resistivity of the region is very small, so that a space charge blocking layer is formed, the carrier storage capacity of a high-resistance voltage-resistant region is improved when the device is conducted, and the conduction loss is reduced; the deep trench gate is connected with the emitter on the surface and is isolated from the drift region (high-resistance voltage-resistant region) of the first conduction type through the gate oxide layer, and the deep trench gate can be used as a charge blocking layer to reduce conduction loss.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 is a schematic structural diagram of an IGBT chip provided in an exemplary embodiment;
fig. 2a to 2j are schematic diagrams of a manufacturing process of an IGBT chip according to an exemplary embodiment.
Description of the reference numerals
101 drift region 102 field oxide 103 first dielectric layer
104 second dielectric layer 105 gate oxide layer 107 deep trench gate
108 gate trench 109 well region 110 emitter
111 insulating spacer 112 contact region 113 emitter metal
114 cutoff layer 115 collector layer
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic structural diagram of an IGBT chip according to an exemplary embodiment. As shown in fig. 1, the IGBT chip may include a collector layer 115, a first conductive-type cut-off layer 114, a first conductive-type drift region 101, an active region, and an emitter metal 113, which are sequentially stacked.
The active region may include a gate oxide layer 105, an emitter 110 of a first conductivity type, a contact region 112 of a second conductivity type, an insulating isolation layer 111, two gate trenches 108, and M deep trench gates 107 and M +1 well regions 109 of the second conductivity type alternately arranged between the two gate trenches 108, where M is an integer and M is greater than or equal to 1.
Wherein each deep trench gate 107 is separated from drift region 101 by gate oxide 105 and from adjacent well region 109 by gate oxide 105. Each gate trench 108 is separated from an adjacent well region 109 by a gate oxide layer 105 and from an emitter metal 113 by an insulating spacer layer 111. Each deep trench gate 107 is in contact with an emitter metal 113. Each well region 109 is separated from emitter metal 113 by a contact region 112. Two of the M +1 well regions 109 adjacent to the two gate trenches 108, respectively, are separated from the insulating isolation layer 111 by an emitter 110.
The IGBT chip in this disclosure is trench type IGBT, and this IGBT chip has the slot of two kinds of different degree of depth: shallow trenches and deep trenches. The shallow trench (gate trench 108) is located in a blank surrounded by the gate oxide layer 105 and the insulating isolation layer 111 and serves as a gate of the device to provide a switching function for the device; the top of the deep trench (deep trench gate 107) is connected with the emitter metal 113 on the surface of the device, wherein the deep trench is separated from the well region 109 by the gate oxide layer 105 and is alternately distributed between the two gate trenches 108, which plays a role in reducing the conduction voltage drop of the device.
Specifically, the gate oxide layer 105 is located between the deep trench gate 107 and the well region 109, between the deep trench gate 107 and the high resistance voltage-withstanding layer (drift region 101), between the gate trench 108 and the well region 109, and between the gate trench 108 and the drift region 101, and plays a role in isolating the protection gate and the deep trench gate 107.
The gate trench 108 is located at a surrounding position of the gate oxide layer 105 and the insulating isolation layer 111, and forms a metal-oxide-semiconductor (MOS) structure with the gate oxide layer 105 and the well region 109, and the MOS structure plays a switching role in a device and is a main characteristic of the device in operation.
The contact region 112 is located between the emitter metal 113 and the well region 109, which can reduce the contact resistance between the well region 109 and the metal 113, and improve the latch-up resistance of the device.
The drift region (high resistance to voltage layer) 101 is located between the active region and the electric field stop layer 114, and provides a larger longitudinal voltage resistance for the device.
The first conductive-type electric field cut-off layer 114 is located between the first conductive-type drift region 101 and the collector 115, and is used for cutting off an electric field inside the device, preventing the electric field from penetrating through to the collector, and optimizing the softness of the device and improving the injection efficiency of minority carriers.
The first conductive type field stop layer 114 is lightly doped with a doping concentration of 1 × 1014㎝-3～5×1015㎝-3。
The drift region 101 of the first conductivity type is lightly doped with a doping concentration of 1 × 1014㎝-3～5×1015㎝-3. The light doping concentration may be a linear distribution or a gaussian-like distribution.
The contact region 112 of the second conductivity type is heavily doped with a doping concentration of 1 × 1020㎝-3～1×1022㎝-3。
The emitter 110 of the first conductive type is heavily doped with a doping concentration of 1 × 1020㎝-3～1×1022㎝-3。
The emitter 110 and the contact region 112 form ohmic contact with the emitter metal 113, which can improve the contact resistance of the device and reduce the contact resistance.
The first conductive type is an N type and the second conductive type is a P type, or the first conductive type is a P type and the second conductive type is an N type.
By the technical scheme, the shallow trench gate is used as the gate electrode trench, so that the device has smaller Miller capacitance and better switching characteristic; a switching system with small channel resistance and small Miller capacitance is formed by the grid electrode formed by the shallow trench and the well region, and has low conduction voltage drop and switching loss; the two sides of the first conductive type region below the shallow trench gate are both provided with the deep trench gates, and under the action of the deep trench gates, the resistivity of the region is very small, so that a space charge blocking layer is formed, the carrier storage capacity of a high-resistance voltage-resistant region is improved when the device is conducted, and the conduction loss is reduced; the deep trench gate is connected with the emitter on the surface and is isolated from the drift region (high-resistance voltage-resistant region) of the first conduction type through the gate oxide layer, and the deep trench gate can be used as a charge blocking layer to reduce conduction loss.
The present disclosure also provides a manufacturing method of the above-mentioned IGBT chip. Fig. 2a to 2j are schematic diagrams of a manufacturing process of an IGBT chip according to an exemplary embodiment.
The method may comprise the steps of:
(1) a substrate of a first conductivity type is provided as a drift region (voltage-proof layer) 101, and a Field Oxide (FOX) 102 is grown on the drift region 101, as shown in fig. 2 a.
(2) The field oxide layer 102 is removed by etching (e.g., wet etching), donor impurities are implanted, and a first dielectric layer 103 (e.g., silicon dioxide or silicon nitride) is deposited, as shown in fig. 2 b.
(3) The deep trench gate region and the gate region are opened on the first dielectric layer 103 by photolithography and etching, and (M +2) shallow trenches are etched in the deep trench gate region and the gate region using the first dielectric layer 103 as a mask, as shown in fig. 2c, where M is 3 in this embodiment.
(4) Depositing a second dielectric layer 104 (e.g., silicon nitride or silicon dioxide), etching (e.g., photolithography) the second dielectric layer 104, and etching the M shallow trenches into M deep trenches using the first dielectric layer 103 and the second dielectric layer 104 as masks, such that the M deep trenches are between the two shallow trenches, as shown in fig. 2 d.
(5) The second dielectric layer 104 and the first dielectric layer 103 are removed by etching (e.g., wet etching), the gate oxide layer 105 is grown, and doped polysilicon (D-poly)106 is deposited, filling the M deep trenches and the two shallow trenches, as shown in fig. 2 e.
(6) The doped polysilicon and gate oxide layer 105 are etched to expose the M deep trench gates 107, the two gate trenches 108, and the drift region 101, as shown in fig. 2 f.
(7) Impurities of the second conductivity type are self-aligned implanted into the exposed drift region 101 and high-temperature junction pushing is performed to form M +1 well regions 109, so that M deep trench gates 107 and M +1 well regions 109 of the second conductivity type are alternately arranged between two gate trenches 108, impurities of the first conductivity type are self-aligned implanted into each well region 109, and emitters 110 of the first conductivity type are activated and formed, as shown in fig. 2 g.
(8) Depositing an insulating isolation layer 111, etching (e.g., photolithography) the insulating isolation layer 111 and the emitter 110 until the M +1 well regions 109 and the M deep trench gates 107 are exposed, self-aligned etching silicon contact holes through the insulating isolation layer 111, and implanting impurities of the second conductivity type on each well region 109 to form contact regions 112 of the second conductivity type and activate, as shown in fig. 2 h.
(9) Emitter metal 113 is deposited as shown in fig. 2 i.
(10) The back surface is thinned, and an impurity of the first conductivity type is implanted on the drift region 101 side and activated to form a cut-off layer 114 of the first conductivity type, and an impurity of the second conductivity type is implanted and activated to form a collector layer 115, as shown in fig. 2 j.
Optionally, the cut-off layer is lightly doped with a doping concentration of 1 × 1014㎝-3～5×1015㎝-3。
Optionally, the drift region is lightly doped with a doping concentration of 1 × 1013㎝-3～2×1014㎝-3。
Optionally, the contact region is heavily doped with a doping concentration of 1 × 1020㎝-3～1×1022㎝-3。
Optionally, the emitter is heavily doped with a doping concentration of 1 × 1020㎝-3～1×1022㎝-3。
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (10)
1. An IGBT chip, characterized in that the IGBT chip comprises a collector layer (115), a cut-off layer (114) of a first conductivity type, a drift region (101) of the first conductivity type, an active region, an emitter metal (113) which are laminated in this order,
the active region comprises a grid oxide layer (105), an emitter (110) of the first conduction type, a contact region (112) of the second conduction type, an insulating isolation layer (111), two grid grooves (108), M deep trench gates (107) and M +1 well regions (109) of the second conduction type, wherein the M is an integer and is not less than 1,
wherein each deep trench gate (107) is separated from the drift region (101) by the gate oxide layer (105) and from an adjacent well region (109) by the gate oxide layer (105), each gate trench (108) is separated from an adjacent well region (109) by the gate oxide layer (105) and from the emitter metal (113) by the insulating isolation layer (111), each deep trench gate (107) is in contact with the emitter metal (113), each well region (109) is separated from the emitter metal (113) by the contact region (112), two well regions (109) of the M +1 well regions (109) that are respectively adjacent to the two gate trenches (108) are separated from the insulating isolation layer (111) by the emitter (110).
2. The IGBT chip of claim 1, wherein the cut-off layer (114) is lightly doped with a doping concentration of 1 x 1014㎝-3～5×1015㎝-3。
3. The IGBT chip of claim 1, wherein the drift region (101) is lightly doped with a doping concentration of 1 x 1013㎝-3～2×1014㎝-3。
4. The IGBT chip of claim 1, wherein the contact regions (112) are heavily doped with a doping concentration of 1 x 1020㎝-3～1×1022㎝-3。
5. The IGBT chip of claim 1, wherein the emitter (110) is heavily doped with a doping concentration of 1 x 1020㎝-3～1×1022㎝-3。
6. A method of manufacturing an IGBT chip, characterized in that the method comprises:
providing a substrate of a first conductivity type as a drift region (101), and growing a field oxide layer (102) on the drift region (101);
etching away the field oxide layer (102), implanting donor impurities, and depositing a first dielectric layer (103);
opening a deep trench gate region and a gate region on the first dielectric layer (103) by photoetching, and etching (M +2) shallow trenches in the deep trench gate region and the gate region by using the first dielectric layer (103) as a mask;
depositing a second dielectric layer (104), etching the second dielectric layer (104), and etching the M shallow trenches into M deep trenches by using the first dielectric layer (103) and the second dielectric layer (104) as masks, so that the M deep trenches are arranged between the two shallow trenches;
etching to remove the second dielectric layer (104) and the first dielectric layer (103), growing a gate oxide layer (105), depositing doped polysilicon, and filling the M deep trenches and the two shallow trenches;
etching the doped polysilicon and the gate oxide layer (105) to expose M deep trench gates (107), two gate trenches (108) and a drift region (101);
implanting impurities of a second conductivity type into the exposed drift region (101) and pushing the impurities to form M +1 well regions (109), so that M deep trench gates (107) and M +1 well regions (109) of the second conductivity type are arranged alternately between the two gate trenches (108), implanting impurities of the first conductivity type into each well region (109) and activating to form emitters (110) of the first conductivity type;
depositing an insulating isolation layer (111), etching the insulating isolation layer (111) and the emitter (110) until M +1 well regions (109) and M deep trench gates (107) are exposed, and injecting impurities of the second conductivity type into each well region (109) to form a contact region (112) of the second conductivity type and activate the contact region;
-depositing an emitter metal (113);
and implanting an impurity of the first conductivity type at the side of the drift region (101) and activating to form a cut-off layer (114) of the first conductivity type, and implanting an impurity of the second conductivity type and activating to form a collector layer (115).
7. The method of claim 6, wherein the stop layer (114) is lightly doped with a doping concentration of 1 x 1014㎝-3～5×1015㎝-3。
8. The method according to claim 6, characterized in that the drift region (101) is lightly doped with a doping concentration of 1 x 1013㎝-3～2×1014㎝-3。
9. The method of claim 6, wherein the contact region (112) is heavily doped with a doping concentration of 1 x 1020㎝-3～1×1022㎝-3。
10. The method of claim 6, wherein the emitter (110) is heavily doped with a doping concentration of 1 x 1020㎝-3～1×1022㎝-3。
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113066775A (en) * | 2021-02-10 | 2021-07-02 | 华为技术有限公司 | Insulated gate bipolar field effect transistor, insulated gate bipolar field effect transistor group and power converter |
| CN114068534A (en) * | 2021-11-15 | 2022-02-18 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN115985942A (en) * | 2023-03-21 | 2023-04-18 | 晶艺半导体有限公司 | Trench gate IGBT device and manufacturing method |
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| CN1418377A (en) * | 2001-01-19 | 2003-05-14 | 三菱电机株式会社 | Kusunoki Shigeru |
| US20020179976A1 (en) * | 2001-05-29 | 2002-12-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| CN104916672A (en) * | 2014-03-14 | 2015-09-16 | 株式会社东芝 | Semiconductor device and method for manufacturing same |
| CN105431949A (en) * | 2014-07-11 | 2016-03-23 | 新电元工业株式会社 | Semiconductor device and method for producing semiconductor device |
| WO2017117902A1 (en) * | 2016-01-05 | 2017-07-13 | 株洲中车时代电气股份有限公司 | Trench gate igbt |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113066775A (en) * | 2021-02-10 | 2021-07-02 | 华为技术有限公司 | Insulated gate bipolar field effect transistor, insulated gate bipolar field effect transistor group and power converter |
| CN114068534A (en) * | 2021-11-15 | 2022-02-18 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN115985942A (en) * | 2023-03-21 | 2023-04-18 | 晶艺半导体有限公司 | Trench gate IGBT device and manufacturing method |
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