CN110931511A - Display panel and preparation method thereof - Google Patents
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- CN110931511A CN110931511A CN201911172341.6A CN201911172341A CN110931511A CN 110931511 A CN110931511 A CN 110931511A CN 201911172341 A CN201911172341 A CN 201911172341A CN 110931511 A CN110931511 A CN 110931511A
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 79
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 60
- 239000000463 material Substances 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 16
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 16
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 11
- 229910021389 graphene Inorganic materials 0.000 claims description 11
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 17
- 229910052751 metal Inorganic materials 0.000 abstract description 13
- 239000002184 metal Substances 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 342
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 238000002834 transmittance Methods 0.000 description 16
- 238000002161 passivation Methods 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 229910010272 inorganic material Inorganic materials 0.000 description 9
- 239000011147 inorganic material Substances 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 239000011159 matrix material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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Abstract
The invention provides a display panel and a preparation method thereof, wherein the display panel is provided with at least one routing layer, and the routing layer comprises a first transparent conducting layer and a two-dimensional conducting layer; the two-dimensional conducting layer is arranged on one side of the first transparent conducting layer in a laminated mode. The technical effect of the present invention is to provide a display panel and a method for manufacturing the same, in which the metal wires of the gate, the source, the drain, and the capacitor electrode include a transparent conductive layer and a two-dimensional conductive layer, so as to implement a transparent display panel, effectively reduce the resistance value of the metal wires, reduce the power consumption, reduce the voltage drop (IR drop) of the display panel, and improve the lighting effect of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
An Active matrix organic light-emitting device (referred to as an AMOLED for short) has the advantages of Active light emission, wide color gamut, fast response, wide viewing angle, high contrast, planarization, and the like, and is a development trend of next generation display and illumination technologies.
In the prior art, a display panel includes a gate layer, a source drain layer, and a pixel electrode. The gate layer and the source drain layer of the array substrate are made of opaque metal materials, so that the display panel cannot achieve a full-transparent effect.
In order to achieve the effect of full transparency of the display panel, those skilled in the art generally prepare all the metal traces in the display panel by using ITO (indium tin oxide, indium zinc oxide) material.
As shown in fig. 1, the display panel includes a substrate 1, a capacitor first electrode 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate electrode 6, a capacitor second electrode 7, a dielectric layer 8, a source/drain electrode 9, a passivation layer 10, a light emitting layer 11, a planarization layer 12, a pixel electrode 13, and a pixel defining layer 14. The first capacitor electrode 2, the gate electrode 6, the second capacitor electrode 7 and the source/drain electrode 9 are all made of ITO (indium tin oxide, indium zinc oxide) materials, so that the display panel achieves a full-transparent effect. Since the gate 306 and the source and drain 309 are made of ITO (indium tin oxide, indium zinc oxide) material, the gate is disposed in the scan line (scan line) direction and the source and drain are disposed in the data line (data line) direction, the scan line and the data line are also made of ITO (indium tin oxide, indium zinc oxide) material. Because the scanning lines and the data lines are made of ITO materials, the resistance (Rs) of the display panel is large, and the voltage drop (IR drop) is large, so that the lighting effect of the display panel is influenced, and the power consumption of the display panel is large.
Disclosure of Invention
The invention provides a display panel and a preparation method thereof, and aims to solve the technical problems that in the prior art, scanning lines and data lines of the display panel are made of ITO materials, so that the resistance (Rs) is large, the voltage drop is large, the lighting effect of the display panel is influenced, and the power consumption is large.
In order to achieve the above object, the present invention provides a display panel, which has at least one routing layer, wherein the routing layer includes a first transparent conductive layer and a two-dimensional conductive layer; the two-dimensional conducting layer is arranged on one side of the first transparent conducting layer in a laminated mode.
Furthermore, the routing layer further comprises a second transparent conducting layer arranged on one surface, far away from the first transparent conducting layer, of the two-dimensional conducting layer.
Further, the material used for the first transparent conductive layer is at least one of indium tin oxide and indium zinc oxide; the material used by the second transparent conducting layer is at least one of indium tin oxide and indium zinc oxide.
Furthermore, the two-dimensional conducting layers are made of graphene and/or molybdenum disulfide; the thickness of the two-dimensional conducting layer is 10-50A.
Further, the wiring layer comprises a source drain electrode, a grid electrode, a driving electrode and a capacitance electrode.
Furthermore, the display panel further comprises a substrate, a capacitor first electrode, a buffer layer, an active layer, a gate insulating layer, a gate, a capacitor second electrode, a dielectric layer and a source drain electrode; the first electrode of the capacitor is arranged on the substrate base plate; the buffer layer is arranged on the substrate and covers the first electrode of the capacitor; the active layer is arranged on the buffer layer; the gate insulating layer is arranged on the active layer and the buffer layer corresponding to the first capacitor electrode; the grid electrode is arranged on the grid electrode insulating layer corresponding to the active layer; the second capacitor electrode is arranged on the gate insulation layer corresponding to the first capacitor electrode; the dielectric layer is arranged on the substrate and covers the grid electrode, the grid electrode insulating layer, the active layer and the capacitor second electrode; the dielectric layer is provided with a through hole and extends to the surface of the active layer from one surface of the dielectric layer, which is far away from the substrate base plate; and the source and drain electrodes are arranged on one surface of the dielectric layer, which is far away from the substrate base plate, extend through the through holes and are connected to the active layer.
In order to achieve the above object, the present invention further provides a method for manufacturing a display panel, which includes steps of preparing at least one routing layer, including forming a first transparent conductive layer; and forming a two-dimensional conductive layer on the first transparent conductive layer.
Further, in the step of preparing at least one routing layer, a second transparent conductive layer is formed on the two-dimensional conductive layer.
Further, depositing graphene and/or molybdenum disulfide on the first transparent conducting layer by adopting a chemical vapor deposition mode to form a two-dimensional conducting layer.
Further, the preparation method of the display panel further comprises the following steps: providing a substrate base plate; forming a first electrode of a capacitor on the substrate base plate; forming a buffer layer on the substrate and covering the first electrode of the capacitor; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer and on the buffer layer corresponding to the first capacitor electrode; in the step of preparing at least one wiring layer, forming a wiring layer as a grid electrode and a capacitor second electrode, wherein the grid electrode is positioned on the grid electrode insulating layer corresponding to the active layer, and the capacitor second electrode is positioned on the grid electrode insulating layer corresponding to the first capacitor electrode; forming a dielectric layer on the substrate and covering the gate electrode, the gate insulating layer, the active layer and the capacitor second electrode; forming a through hole extending from one surface of the dielectric layer far away from the substrate to the surface of the active layer; and in the step of preparing at least one wiring layer, forming another wiring layer as a source drain electrode, wherein the source drain electrode is positioned on one surface of the dielectric layer, which is far away from the substrate base plate, and extends through the through hole and is connected to the active layer.
The technical effect of the present invention is to provide a display panel and a method for manufacturing the same, wherein the metal wires of the gate, the source, the drain, and the capacitor electrode include a transparent conductive layer and a two-dimensional conductive layer, so as to realize a transparent display panel, and effectively reduce the resistance value of the metal wires, thereby reducing the voltage drop (IR drop) of the display panel, and improving the lighting effect of the display panel.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a display panel according to the prior art;
FIG. 2 is a schematic structural diagram of a wiring layer according to embodiment 1;
fig. 3 is a schematic structural diagram of the display panel according to embodiment 1;
FIG. 4 is a schematic structural diagram of a wiring layer according to embodiment 2;
fig. 5 is a schematic structural diagram of the display panel according to embodiment 2.
The components of the drawings are identified as follows:
1 a substrate base plate; 2 a capacitive first electrode; 3 a buffer layer; 4 an active layer;
5 a gate insulating layer; 6, a grid electrode; 7 a capacitive second electrode; 8 a dielectric layer; 9 source and drain electrodes;
10 a passivation layer; 11 a light emitting layer; 12 a planar layer; 13 pixel electrodes; 14 pixel definition layers;
80 through holes; 120 through holes;
100 routing layers; 111 a first transparent conductive layer; 112 a two-dimensional conductive layer; 113 a second transparent conductive layer;
201 a first TFT switch; 202 a second TFT switch; 203 capacitance; 1000 display panel.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings for illustrating the invention and enabling those skilled in the art to fully describe the technical contents of the present invention so that the technical contents of the present invention can be more clearly and easily understood. The present invention may, however, be embodied in many different forms of embodiments and the scope of the present invention should not be construed as limited to the embodiments set forth herein.
Example 1
As shown in fig. 2, the present embodiment provides a display panel 1000, where the display panel 1000 has at least one routing layer 100. The routing layer 100 includes a first transparent conductive layer 111 and a two-dimensional conductive layer 112. The two-dimensional conductive layer 112 is stacked on the lower surface of the first transparent conductive layer 111. The material of the first transparent conductive layer 111 is at least one of indium tin oxide and indium zinc oxide, and has good light transmittance. The two-dimensional conductive layer 112 is made of transparent graphene and/or transparent molybdenum disulfide, is 10-50A thick, and has good light transmittance and good conductivity. In this embodiment, the routing layer 100 includes a source/drain, a gate, a driving electrode, and a capacitor electrode.
As shown in fig. 3, the display panel 1000 includes a substrate 1, a capacitor first electrode 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate electrode 6, a capacitor second electrode 7, a dielectric layer 8, a source/drain electrode 9, a passivation layer 10, a light emitting layer 11, a planarization layer 12, a pixel electrode 13, and a pixel defining layer 14.
The base substrate 1 may be a glass substrate or a PI substrate.
The first electrode 2 of the capacitor is arranged on the upper surface of the substrate 1 and is a lower electrode of the capacitor. The material used for the capacitive first electrode 2 includes, but is not limited to, transparent ITO or IZO.
The buffer layer 3 is disposed on the upper surface of the substrate 1 and covers the first electrode 2. The structure of the buffer layer 3 may be composed of a single layer or a multi-layer film. The buffer layer 3 is made of inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx), and can achieve the effect of isolating water and oxygen.
The active layer 4 is provided on the upper surface of the buffer layer. The material of the active layer 4 is an oxide semiconductor (oxide semiconductor) including but not limited to IGZO or ITZO.
The gate insulating layer 5 is disposed on the active layer 4 and on the buffer layer 4 corresponding to the first electrode 2 of the capacitor. The structure of the gate insulating layer 5 may be composed of a single layer or a plurality of layers. The gate insulating layer 5 is made of an inorganic material such as silicon oxide (SiO2) or silicon nitride (SiNx), and has a good insulating effect.
The gate electrode 6 is disposed on the upper surface of the gate insulating layer 5 corresponding to the active layer 4. Specifically, the gate electrode 6 includes a first transparent conductive layer 111 and a two-dimensional conductive layer 112. The two-dimensional conductive layer 112 is disposed on the upper surface of the gate insulating layer 5 corresponding to the active layer 4, and the first transparent conductive layer 111 is stacked on the upper surface of the two-dimensional conductive layer 112. The first transparent conductive layer 111 and the two-dimensional conductive layer 112 have good light transmittance and electrical conductivity, so that the gate 6 is a transparent electrode having excellent light transmittance and electrical conductivity.
The second capacitor electrode 7 is disposed on the upper surface of the gate insulating layer 5 corresponding to the first capacitor electrode 2 and is an upper electrode of the capacitor. The capacitance second electrode 7 includes a first transparent conductive layer 111 and a two-dimensional conductive layer 112. The two-dimensional conductive layer 112 is disposed on the upper surface of the gate insulating layer 5 corresponding to the first electrode 2 of the capacitor, and the first transparent conductive layer 111 is stacked on the upper surface of the two-dimensional conductive layer 112. The first transparent conductive layer 111 and the two-dimensional conductive layer 112 have good light transmittance and electrical conductivity, so that the second electrode 7 of the capacitor is a transparent electrode with excellent light transmittance and electrical conductivity.
The dielectric layer 8 is disposed on the upper surface of the substrate 1 and covers the gate electrode 6, the gate insulating layer 5, the active layer 4, and the capacitor second electrode 7. The dielectric layer 8 structure may be composed of a single layer or a plurality of layers. The buffer layer 3 is made of inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx). The dielectric layer 8 is provided with a via 80 extending from a side of the dielectric layer 8 remote from the substrate base plate 1 to an upper surface of the active layer 4.
The source and drain electrodes 9 are provided on the side of the dielectric layer 8 remote from the substrate base plate 1 and extend through the via 80 and connect to the active layer 4. Specifically, the source-drain electrode 9 includes a first transparent conductive layer 111 and a two-dimensional conductive layer 112. The two-dimensional conductive layer 112 is disposed on a surface of the dielectric layer 8 away from the substrate 1, and extends through the via 80 and connects to the active layer 4, and the first transparent conductive layer 111 is stacked on an upper surface of the two-dimensional conductive layer 112. The first transparent conductive layer 111 and the two-dimensional conductive layer 112 have good light transmittance and electrical conductivity, so that the source/drain 9 can be a transparent electrode, and has excellent light transmittance and electrical conductivity.
The display panel 1000 further includes a passivation layer 10, a light emitting layer 11, a planarization layer 12, a pixel electrode 14, and a pixel defining layer 15. Wherein, the passivation layer 10 is disposed on the upper surface of the source/drain electrode 9. The light emitting layer 11 is disposed on the upper surface of the passivation layer 10, and the light emitting layer 11 includes a red color set (R), a green color set (G), and a blue color set (B). The planarization layer 12 is disposed on the passivation layer 10 and the light emitting layer 11, and covers the light emitting layer 11. A via 120 penetrates the passivation layer 10 and the planarization layer 12, and corresponds to a source and a drain. The pixel electrode 14 is disposed on the upper surface of the planarization layer 12 and is connected to a source/drain electrode through a via 120. The pixel defining layer 15 covers a portion of the pixel electrode 14. The display panel 1000 provided in this embodiment further includes other components, which are not described herein again.
As shown in fig. 3, the display panel 1000 includes a first TFT switch 100, a second TFT switch 202, and a capacitor 203. Wherein the first TFT switch 100 is a switch only as the display panel 1000; the second TFT switch 202 is a driving switch for driving the display panel 1000 to implement a display function; the capacitor 203 is a storage capacitor for temporarily storing power for the display panel 1000.
In this embodiment, a display panel 1000 is provided, where the metal wires of the gate, the source, the drain, and the capacitor electrode include a transparent conductive layer and a two-dimensional conductive layer. The conductive layer and the two-dimensional conductive layer have good transmittance, so that the fully transparent display panel 1000 is realized, the resistance value of the metal wire is effectively reduced, the voltage drop (IR drop) of the display panel is reduced, the power consumption is reduced, and the lighting effect of the display panel is improved.
The embodiment also provides a preparation method of the display panel, which comprises the step of preparing at least one wiring layer.
In the step of preparing the routing layer, a first transparent conductive layer and a two-dimensional conductive layer are formed on the upper surface of the first transparent conductive layer. In the step of forming the first transparent conductive layer, indium tin oxide and/or indium zinc oxide is deposited to form the first transparent conductive layer. In the step of forming the two-dimensional conducting layer, graphene and/or molybdenum disulfide are deposited on the upper surface of the first transparent conducting layer in a chemical vapor deposition mode to form the two-dimensional conducting layer, and the thickness of the two-dimensional conducting layer is 10-50A (angstroms). In this embodiment, the routing layer includes a source/drain, a gate, a driving electrode, and a capacitor electrode.
The present embodiment provides a method for producing a display panel, including the following step S11) -S19).
S11) providing a substrate, and cleaning and baking the substrate. The substrate base plate is a glass base plate or a Polyimide (PI) base plate.
S12) forming a capacitive first electrode on the substrate base plate. Specifically, a transparent ITO or IZO material is deposited on the upper surface of the substrate base plate to form the capacitive first electrode. The first capacitor is a lower electrode of the capacitor.
S13) forming a buffer layer on the substrate and covering the first electrode of the capacitor. And depositing inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx) on the substrate base plate to form the buffer layer. The structure of the buffer layer can be composed of a single layer or a plurality of layers of films, so that the buffer layer has a good water and oxygen isolating effect.
S14) forming an active layer on the buffer layer. And depositing an oxide semiconductor (oxide semiconductor) material on the buffer layer to form the active layer. The active layer includes, but is not limited to, IGZO or ITZO.
S15) forming a gate insulating layer on the active layer and on the buffer layer corresponding to the first capacitor electrode. And depositing inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx) on the upper surface of the active layer and the upper surface of the buffer layer corresponding to the first capacitor electrode to form the gate insulating layer.
S16), in the step of preparing at least one wiring layer, forming a wiring layer as a gate electrode and a capacitor second electrode, wherein the gate electrode is located on the gate insulating layer corresponding to the active layer, and the capacitor second electrode is located on the gate insulating layer corresponding to the first capacitor electrode.
Specifically, transparent graphene and/or transparent molybdenum disulfide are deposited on the upper surface of the gate insulating layer corresponding to the active layer, and transparent graphene and/or transparent molybdenum disulfide are deposited on the upper surface of the gate insulating layer corresponding to the first capacitor electrode, so that a two-dimensional conducting layer is formed, and the thickness of the two-dimensional conducting layer is 10-50A. And depositing indium tin oxide and indium zinc oxide materials on the upper surface of the two-dimensional conductive layer to form a first transparent conductive layer. In this embodiment, the gate and the second capacitor electrode both include the first transparent conductive layer and the two-dimensional conductive layer, so that the gate and the second capacitor electrode have good transmittance and conductivity.
S17) forming a dielectric layer on the substrate and covering the gate electrode, the gate insulating layer, the active layer and the capacitor second electrode. And depositing inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx) on the upper surface of the substrate base plate to form the dielectric layer.
S18) forming a through hole, wherein the through hole extends from the surface of the dielectric layer far away from the substrate to the surface of the active layer.
S19), in the step of preparing at least one wiring layer, forming another wiring layer as a source drain electrode, wherein the source drain electrode is positioned on one surface of the dielectric layer far away from the substrate base plate and extends to be connected to the active layer through the through hole.
Specifically, a chemical vapor deposition method is adopted to deposit transparent graphene and/or transparent molybdenum disulfide materials in the through holes and on the upper surface of part of the dielectric layer, and a two-dimensional conducting layer with the thickness of 10-50A (angstroms) is formed. The two-dimensional conducting layer is attached to the bottom wall and the side wall of the through hole to form a groove. And depositing indium tin oxide and indium zinc oxide materials in the grooves, filling the grooves to form a first transparent conducting layer, wherein the first transparent conducting layer is attached to the upper surface of the two-dimensional conducting layer. In this embodiment, the source and drain electrodes include the first transparent conductive layer and the two-dimensional conductive layer, so that the source and drain electrodes have good transmittance and conductivity.
After the step of forming the source and drain electrodes, the method further includes steps of preparing a passivation layer, a light emitting layer, a planarization layer, a pixel electrode, and a pixel defining layer, which are not described herein in detail.
The present embodiment provides a display panel and a manufacturing method thereof, where metal wires of a gate, a source, a drain, and a capacitor electrode include a transparent conductive layer and a two-dimensional conductive layer, so as to implement a transparent display panel, and effectively reduce a resistance value of the metal wires, thereby reducing a voltage drop (IR drop) of the display panel, reducing power consumption, and improving an effect of lighting the display panel.
Example 2
The embodiment provides a display panel and a manufacturing method thereof, including most technical solutions of embodiment 1, and the difference is that the routing layer further includes a second conductive layer, so that the display panel has better transmittance and conductivity, and the performance of the display panel is improved while the display panel is fully transparent.
The present embodiment provides a display panel 1000 including at least one wiring layer 100. The wiring layer 100 includes source and drain electrodes, a gate electrode, a driving electrode, and a capacitance electrode.
As shown in fig. 4, the routing layer 100 includes a first transparent conductive layer 111, a two-dimensional conductive layer 112, and a second transparent conductive layer 113. The two-dimensional conductive layer 112 and the second transparent conductive layer 113 are sequentially stacked on the upper surface of the first transparent conductive layer 111.
As shown in fig. 5, the display panel 1000 includes a substrate 1, a capacitor first electrode 2, a buffer layer 3, an active layer 4, a gate insulating layer 5, a gate electrode 6, a capacitor second electrode 7, a dielectric layer 8, a source/drain electrode 9, a passivation layer 10, a light emitting layer 11, a planarization layer 12, a pixel electrode 13, and a pixel defining layer 14. The gate 6, the capacitor second electrode 7, and the source/drain 9 each include a first transparent conductive layer 111, a two-dimensional conductive layer 112, and a second transparent conductive layer 113. The two-dimensional conductive layer 112 and the second transparent conductive layer 113 are sequentially stacked on the upper surface of the first transparent conductive layer 111. In addition, the material used for the capacitive first electrode 2 includes, but is not limited to, transparent ITO or IZO.
Therefore, the present embodiment provides a display panel, where the metal wires of the gate, the source, the drain, and the capacitor electrode include double-layered conductive layers and two-dimensional conductive layers, and the two-dimensional conductive layers are disposed between the double-layered conductive layers. The conductive layer and the two-dimensional conductive layer have good transmittance, so that a fully transparent display panel can be realized, the resistance value of the metal wire is effectively reduced, the voltage drop (IR drop) of the display panel is reduced, and the lighting effect of the display panel is improved.
The present embodiment also provides a manufacturing method of a display panel, including the following step S21) -S29).
S21) providing a substrate, and cleaning and baking the substrate. The substrate base plate is a glass base plate or a Polyimide (PI) base plate.
S22) forming a capacitive first electrode on the substrate base plate. Specifically, a transparent ITO or IZO material is deposited on the upper surface of the substrate base plate to form the capacitive first electrode. The first capacitor is a lower electrode of the capacitor.
S23) forming a buffer layer on the substrate and covering the first electrode of the capacitor. And depositing inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx) on the substrate base plate to form the buffer layer. The structure of the buffer layer can be composed of a single layer or a plurality of layers of films, so that the buffer layer has a good water and oxygen isolating effect.
S24) forming an active layer on the buffer layer. And depositing an oxide semiconductor (oxide semiconductor) material on the buffer layer to form the active layer. The active layer includes, but is not limited to, IGZO or ITZO.
S25) forming a gate insulating layer on the active layer and on the buffer layer corresponding to the first capacitor electrode. And depositing inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx) on the upper surface of the active layer and the upper surface of the buffer layer corresponding to the first capacitor electrode to form the gate insulating layer.
S26), in the step of preparing at least one wiring layer, forming a wiring layer as a gate electrode and a capacitor second electrode, wherein the gate electrode is located on the gate insulating layer corresponding to the active layer, and the capacitor second electrode is located on the gate insulating layer corresponding to the first capacitor electrode.
Specifically, indium tin oxide and indium zinc oxide materials are deposited on the upper surface of the grid insulating layer corresponding to the active layer, and a first transparent conducting layer is formed. And depositing transparent graphene and/or transparent molybdenum disulfide on the upper surface of the first transparent conducting layer by adopting a chemical vapor deposition mode to form a two-dimensional conducting layer. And depositing indium tin oxide and indium zinc oxide materials on the upper surface of the two-dimensional conductive layer to form a second transparent conductive layer. In this embodiment, the gate and the second capacitor electrode each include a first transparent conductive layer, a two-dimensional conductive layer, and a second transparent conductive layer, so that the gate and the second capacitor electrode have good transmittance and conductivity.
S27) forming a dielectric layer on the substrate and covering the gate electrode, the gate insulating layer, the active layer and the capacitor second electrode. And depositing inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiNx) on the upper surface of the substrate base plate to form the dielectric layer.
S28) forming a through hole, wherein the through hole extends from the surface of the dielectric layer far away from the substrate to the surface of the active layer.
S29), in the step of preparing at least one wiring layer, forming another wiring layer as a source drain electrode, wherein the source drain electrode is positioned on one surface of the dielectric layer far away from the substrate base plate and extends to be connected to the active layer through the through hole.
Specifically, indium tin oxide and indium zinc oxide materials are deposited in the through holes and on the upper surface of part of the dielectric layer, and a first transparent conductive layer is formed. The first transparent conducting layer is attached to the bottom wall and the side wall of the through hole to form a first groove. And depositing transparent graphene and/or transparent molybdenum disulfide in the first groove to form a two-dimensional conducting layer, wherein the two-dimensional conducting layer is attached to the bottom wall and the side wall of the second groove to form a second groove. And depositing indium tin oxide and indium zinc oxide materials in the second groove, and filling the second groove to form a second transparent conducting layer. In this embodiment, the source and drain electrodes include the first transparent conductive layer, the two-dimensional conductive layer, and the second transparent conductive layer, so that the source and drain electrodes have good transmittance and conductivity.
After the step of forming the source and drain electrodes, the method further includes steps of preparing a passivation layer, a light emitting layer, a planarization layer, a pixel electrode, and a pixel defining layer, which are not described herein in detail.
The embodiment provides a display panel and a preparation method thereof, wherein metal leads of a grid electrode, a source electrode, a drain electrode and a capacitance electrode comprise double-layer conductive layers and two-dimensional conductive layers, and the two-dimensional conductive layers are arranged between the double-layer conductive layers. The conductive layer and the two-dimensional conductive layer have good transmittance, so that a fully transparent display panel can be realized, the resistance value of the metal wire is effectively reduced, the voltage drop (IR drop) of the display panel is reduced, the power consumption is reduced, and the lighting effect of the display panel is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A display panel is characterized in that the display panel is provided with at least one routing layer, and the routing layer comprises a first transparent conductive layer; and
and the two-dimensional conductive layer is stacked on one side of the first transparent conductive layer.
2. The display panel of claim 1, wherein the routing layer further comprises a second transparent conductive layer disposed on a side of the two-dimensional conductive layer away from the first transparent conductive layer.
3. The display panel according to claim 2,
the material used by the first transparent conducting layer is at least one of indium tin oxide and indium zinc oxide;
the material used by the second transparent conducting layer is at least one of indium tin oxide and indium zinc oxide.
4. The display panel according to claim 1,
the two-dimensional conducting layers are made of graphene and/or molybdenum disulfide;
the thickness of the two-dimensional conducting layer is 10-50A.
5. The display panel according to claim 1, wherein the wiring layer comprises a source drain electrode, a gate electrode, a driving electrode, and a capacitance electrode.
6. The display panel according to claim 1, further comprising:
a substrate base plate;
the capacitor first electrode is arranged on the substrate base plate;
the buffer layer is arranged on the substrate and covers the first electrode of the capacitor;
an active layer disposed on the buffer layer;
the gate insulation layer is arranged on the active layer and the buffer layer corresponding to the first capacitor electrode;
the grid electrode is arranged on the grid electrode insulating layer corresponding to the active layer;
the second capacitor electrode is arranged on the gate insulation layer corresponding to the first capacitor electrode;
a dielectric layer disposed on the substrate and covering the gate electrode, the gate insulating layer, the active layer and the capacitor second electrode; the dielectric layer is provided with a through hole which extends to the surface of the active layer from one surface of the dielectric layer, which is far away from the substrate base plate; and
and the source and drain electrodes are arranged on one surface of the dielectric layer, which is far away from the substrate base plate, extend through the through holes and are connected to the active layer.
7. A method for preparing a display panel comprises preparing at least one wiring layer including
Forming a first transparent conductive layer;
and forming a two-dimensional conductive layer on the first transparent conductive layer.
8. The method for manufacturing a display panel according to claim 7, further comprising forming a second transparent conductive layer on the two-dimensional conductive layer in the step of manufacturing at least one routing layer.
9. The method for manufacturing a display panel according to claim 7,
and depositing graphene and/or molybdenum disulfide on the first transparent conducting layer by adopting a chemical vapor deposition mode to form a two-dimensional conducting layer.
10. The method for manufacturing a display panel according to claim 7, further comprising the steps of:
providing a substrate base plate;
forming a first electrode of a capacitor on the substrate base plate;
forming a buffer layer on the substrate and covering the first electrode of the capacitor;
forming an active layer on the buffer layer;
forming a gate insulating layer on the active layer and on the buffer layer corresponding to the first capacitor electrode;
in the step of preparing at least one wiring layer, forming a wiring layer as a grid electrode and a capacitor second electrode, wherein the grid electrode is positioned on the grid electrode insulating layer corresponding to the active layer, and the capacitor second electrode is positioned on the grid electrode insulating layer corresponding to the first capacitor electrode;
forming a dielectric layer on the substrate and covering the gate electrode, the gate insulating layer, the active layer and the capacitor second electrode;
forming a through hole extending from one surface of the dielectric layer far away from the substrate to the surface of the active layer;
and in the step of preparing at least one wiring layer, forming another wiring layer as a source drain electrode, wherein the source drain electrode is positioned on one surface of the dielectric layer, which is far away from the substrate base plate, and extends through the through hole and is connected to the active layer.
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| CN111312077A (en) * | 2020-03-03 | 2020-06-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN111725281A (en) * | 2020-06-12 | 2020-09-29 | 维沃移动通信有限公司 | Display module and electronic equipment |
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