CN110912095A

CN110912095A - Overvoltage and impact current resistant starting circuit

Info

Publication number: CN110912095A
Application number: CN201911112304.6A
Authority: CN
Inventors: 冯非; 董凯; 霍跃庆; 韩敏; 严会会; 刘国美
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2019-11-14
Filing date: 2019-11-14
Publication date: 2020-03-24

Abstract

The invention relates to an overvoltage and impact current resistant starting circuit, which is suitable for a power circuit needing to realize surge voltage and impact current suppression functions, and comprises the following components: the circuit comprises an input end Vi, a clamping voltage circuit, a first field effect transistor Q1 and a buffer circuit. The slope of the clamp voltage Vc is controlled by a buffer circuit. In the whole circuit, the first field effect transistor Q1 is a power device, and other components have low power consumption, so that the efficiency is high. The circuit implementation mode in the prior art uses two sets of circuits to achieve the functions of impact current suppression and overvoltage suppression, and has the advantages of multiple used components, high cost and low reliability.

Description

Overvoltage and impact current resistant starting circuit

Technical Field

The invention relates to the technical field of circuits, in particular to an overvoltage and impact current resistant starting circuit.

Background

The input end of the internal power supply of the electronic equipment needs a capacitor with a large capacitance value for filtering and power failure maintenance, and the impact of starting current, namely impact current, is brought to a power supply system at the moment of power-on starting of the equipment. The impact current not only has a serious influence on a power supply system, but also causes damage to electronic devices and circuit boards inside the electronic equipment.

In the conventional circuit design, in order to suppress the rush current on the line at the moment of powering on the device, a soft start circuit is added at the input end of the power circuit, as shown in fig. 1, fig. 2, and fig. 3. In fig. 1, an inductor L is used at the power input end, and the method is simple and is suitable for a low-power circuit due to the limitations of the size, weight and the like of the inductor; in fig. 2, a thermistor NTC is used at the power input end, and the normal operation loss of the circuit is large; in fig. 3, a combination of a relay and a resistor is used, the resistor consumes a large amount of power when the relay is not turned on, and the relay is also a long-life component and cannot be used in a high-safety situation.

In some application fields, overvoltage surge beyond the normal working range of a power supply can be generated on a bus bar of a power supply system, and in order to meet various requirements of overvoltage and impact current resistance of a power supply of electronic equipment, an overvoltage and impact current resistant starting circuit with a simple structure and reliable functions is required to be designed at the front end of the power supply of the electronic equipment, so that the impact current and the overvoltage can be inhibited.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the defects of the prior art, the overvoltage and impact current resistant starting circuit is provided, integrates impact current suppression and overvoltage suppression, solves the problems of high power consumption, low efficiency, large size and the like of the starting circuit in the traditional protection mode, and protects the power supply system of the electronic equipment and the circuit of the electronic equipment to the greatest extent.

The technical solution of the invention is as follows:

the starting circuit for resisting overvoltage and impact current comprises a field effect transistor Q1, a clamping voltage circuit and a buffer circuit, wherein one end of an input end Vi is connected with the drain electrode of the field effect transistor Q1, and the grid electrode of the field effect transistor Q1 is connected with the output of the buffer circuit; the output of the clamping voltage circuit is connected to the buffer circuit input.

Further, the starting circuit for resisting overvoltage and impact current controls the grid of the field-effect transistor Q1 by the clamping voltage Vc output by the clamping voltage circuit, so as to clamp the output voltage of the field-effect transistor Q1 and further realize the function of suppressing surge voltage; the slope established by the clamping voltage Vc is controlled through the buffer circuit, and the suppression of the impact current is realized.

Further, the starting circuit for resisting overvoltage and surge current is a circuit which can make the slope established by the clamping voltage Vc controlled, and includes but is not limited to RC buffer, digital potentiometer, and any other analog and digital circuit form which can be used for controlling the slope established by the voltage.

Further, according to the overvoltage and impact current resistant starting circuit, the clamping voltage Vc changes the voltage thereof through the buffer circuit to establish the slope, so that the first field effect transistor Q1 enters the Miller platform, and the impact current suppression is realized.

Further, according to the starting circuit for resisting overvoltage and impact current, after the clamping voltage Vc passes through the buffer circuit, the first field-effect transistor Q1 is conducted, and when overvoltage surge occurs, the clamping voltage Vc clamps the output voltage of the first field-effect transistor Q1 at a fixed voltage, so that the overvoltage surge suppression function is realized.

Preferably, the starting circuit for resisting overvoltage and surge current is characterized in that the buffer circuit is formed by connecting a resistor R1 and a capacitor C1 in parallel, a resistor R1 is an input end of the buffer circuit, and a connecting point of the resistor R1 and the capacitor C1 in parallel is an output end of the buffer circuit.

Preferably, the starting circuit for resisting overvoltage and inrush current is characterized in that the buffer circuit is formed by connecting a resistor R1 and a capacitor C1 in series, the resistor R1 is an input end of the buffer circuit, and the capacitor C1 is an output end of the buffer circuit.

The invention has the advantages that: in the whole circuit, the first field effect transistor Q1 is a power device, and other components have low power consumption, so that the efficiency is high. The circuit implementation mode in the prior art uses two sets of circuits to achieve the functions of impact current suppression and overvoltage suppression, and has the advantages of multiple used components, high cost and low reliability.

Drawings

FIG. 1 is a rush current suppression circuit using an inductor;

FIG. 2 is a rush current suppression circuit using an NTC resistor;

FIG. 3 is a rush current suppression circuit using a relay;

FIG. 4 is a schematic block diagram of the overvoltage and inrush current resistant start-up circuit of the present invention;

FIG. 5 shows a method 1 for implementing the buffer circuit according to the present invention;

fig. 6 shows a buffer circuit implementation method 2 according to the present invention.

Detailed Description

The following is a detailed description of embodiments of the present invention, which is implemented on the premise of the technical solution of the present invention, and a detailed implementation scheme and a specific implementation process are given, but the scope of the present invention is not limited to the following description.

As shown in fig. 4, one end of the input end Vi is connected to the drain of the field effect transistor, and the gate of the field effect transistor is connected to the output of the buffer circuit; the output of the clamping voltage circuit is connected to the buffer circuit input.

Specifically, when the power input end Vi generates voltage, the clamp voltage circuit generates voltage Vc, and the slope or time of the Vc voltage is changed under the action of the buffer circuit, so that the field-effect transistor Q1 is in a saturation region and presents a variable resistance characteristic, and the capacitor in the circuit is charged in an RC manner, thereby reducing the impact current, realizing the impact current suppression function, and completing the start in the circuit.

Specifically, when the power input end Vi generates overvoltage surge, the source electrode output voltage of the field effect transistor cannot be suddenly changed due to the action of clamping voltage, and the overvoltage surge resisting function of the circuit is realized.

As shown in fig. 5, one end of the input terminal Vi is connected to the drain of the fet, the buffer circuit is formed by connecting a resistor R1 and a capacitor C1 in parallel, a resistor R1 is the input terminal of the buffer circuit, and the gate of the fet is connected to the output of the buffer circuit; the output of the clamping voltage circuit is connected with a resistor R1 in the buffer circuit, and a resistor R1 is connected with a capacitor C1 in parallel and connected with the grid electrode of a field effect transistor Q1.

Specifically, the output voltage of the fet Q1 is determined by the gate clamp voltage and the voltage of the fet Vgs, calculated according to the circuit requirements. The limiting values of the power supply voltage and the output voltage can be calculated to obtain the amplitude of the clamping voltage and the working time of the impact current suppression circuit.

As shown in fig. 6, one end of the input Vi is connected to the drain of the fet, the buffer circuit is formed by connecting a resistor R1 and a capacitor C1 in series, and the gate of the fet is connected to the output of the buffer circuit; the output of the isolation clamp voltage circuit is connected with the input end of the buffer circuit, namely a resistor R1, and a resistor R1 is connected with a capacitor C1 in series and is connected with the grid electrode of a field effect transistor Q1.

For example, a circuit with an input DC 28V input and an output 100W has a power-on surge current of about 30A. By adopting the invention, the impact current can be reduced to less than 5A.

The above-mentioned embodiments are not intended to limit the present invention, and all changes, substitutions and the like that are made within the principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The starting circuit is characterized by comprising a field effect transistor Q1, a clamping voltage circuit and a buffer circuit, wherein one end of an input end Vi is connected with the drain electrode of a field effect transistor Q1, and the grid electrode of the field effect transistor Q1 is connected with the output of the buffer circuit; the output of the clamping voltage circuit is connected to the buffer circuit input.

2. The starting circuit of claim 1, wherein the clamping voltage Vc outputted from the clamping voltage circuit is used to control the gate of the fet Q1, so as to clamp the output voltage of the fet Q1, and further realize the surge voltage suppression function; the slope established by the clamping voltage Vc is controlled through the buffer circuit, and the suppression of the impact current is realized.

3. The starting circuit of claim 1, wherein the snubber circuit is a circuit capable of controlling the slope of the clamped voltage Vc, and includes but is not limited to RC snubber, digital potentiometer, and any other analog and digital circuit form capable of controlling the slope of the voltage set-up.

4. The starting circuit of claim 2, wherein the clamping voltage Vc changes its voltage through the buffer circuit to establish a slope, so that the first fet Q1 enters the miller stage to suppress the inrush current.

5. The starting circuit of claim 2, wherein the first fet Q1 is turned on after the clamping voltage Vc passes through the buffer circuit, and when an overvoltage surge occurs, the clamping voltage Vc clamps the output voltage of the first fet Q1 to a fixed voltage, thereby achieving an overvoltage surge suppression function.

6. The starting circuit of claim 1, wherein the snubber circuit is formed by connecting a resistor R1 in parallel with a capacitor C1, a resistor R1 is an input terminal of the snubber circuit, and a connection point where the resistor R1 is connected in parallel with the capacitor C1 is an output terminal of the snubber circuit.

7. The starting circuit of claim 1, wherein the snubber circuit is formed by connecting a resistor R1 in series with a capacitor C1, the resistor R1 is an input terminal of the snubber circuit, and the capacitor C1 is an output terminal of the snubber circuit.