CN110911344B - Manufacturing method of semiconductor substrate shallow trench and semiconductor substrate shallow trench structure - Google Patents
Manufacturing method of semiconductor substrate shallow trench and semiconductor substrate shallow trench structure Download PDFInfo
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- CN110911344B CN110911344B CN201811074209.7A CN201811074209A CN110911344B CN 110911344 B CN110911344 B CN 110911344B CN 201811074209 A CN201811074209 A CN 201811074209A CN 110911344 B CN110911344 B CN 110911344B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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Abstract
The application relates to the field of semiconductor device manufacturing, and discloses a method and a structure for manufacturing a shallow trench of a semiconductor substrate, wherein the method comprises the following steps: 1) Providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the shape and the position of a shallow groove; 2) Performing main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window to form a groove structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the groove structure; 3) Performing a bottom penetration step of the cyclic etching, including removing the bottom etching byproducts; 4) A groove wall protection step of cyclic etching is carried out, which comprises the steps of forming a side wall oxide layer on the side wall of the groove structure; 5) And circularly executing the steps 2) to 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
Description
Technical Field
The application relates to the field of semiconductor device manufacturing, in particular to a method for manufacturing a shallow trench of a semiconductor substrate and a shallow trench structure of the semiconductor substrate.
Background
Semiconductor integrated circuits typically include active regions and isolation regions between the active regions, which are formed prior to fabrication of the active devices. With the advent of semiconductor technology into the deep submicron age, the active region isolation layer of semiconductor devices has been mostly fabricated using shallow trench isolation (Shallow Trench Isolation, STI) technology.
With the evolution and progress of semiconductor technology nodes and semiconductor manufacturing tools, the device density on the silicon wafer is continuously increased, the critical dimension is continuously reduced, and in order to ensure better isolation effect, deeper shallow trenches need to be manufactured, and the depth-to-width ratio of the shallow trenches is improved. Referring to fig. 1A, 1B and 1C, since a long etching time is required to increase the depth of the shallow trench, the continuously output bias power may cause flaring of the shallow trench opening and may reduce the etching selectivity; etching byproducts are deposited at the bottom and the opening of the shallow trench, so that etching is finished in advance, and the depth of the shallow trench cannot reach the target etching depth; due to the relation of graphic design, the critical dimensions of the shallow trench openings are different, and the uniformity of the shallow trench depth formed by etching is inconsistent due to the micro-loading effect.
Disclosure of Invention
The application aims to provide a manufacturing method of a shallow trench of a semiconductor substrate and a shallow trench structure of the semiconductor substrate, which can improve the flaring phenomenon of an opening of the shallow trench, enable the depth of the trench to reach the target etching depth and improve the uniformity of the depth of the shallow trench.
In order to achieve the above object, in a first aspect of the present application, there is provided a method for manufacturing a shallow trench in a semiconductor substrate, comprising: 1) Providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the shape and the position of a shallow groove; 2) Performing main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window to form a groove structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the groove structure; 3) Performing a bottom penetration step of the cyclic etching, including removing the bottom etching byproducts; 4) A groove wall protection step of cyclic etching is carried out, which comprises the steps of forming a side wall oxide layer on the side wall of the groove structure; 5) And circularly executing the steps 2) to 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
Optionally, in step 1), a surface protection layer is further formed on the semiconductor substrate, where the surface protection layer is located between the mask layer and the semiconductor substrate, and the surface protection layer has a second etching window corresponding to the first etching window.
Optionally, in step 2), forming a surface etching byproduct on the surface of the mask layer while performing deep etching on the semiconductor substrate; and 3) removing the surface etching byproducts on the surface of the mask layer at the same time of removing the bottom etching byproducts.
Optionally, in step 2), the semiconductor substrate is etched in a deep etching mode by using a pulse bias power output mode.
Optionally, in step 2), the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the semiconductor substrate is etched in a deepening mode by adopting a low-frequency pulse type bias power output mode in the step 2), the 13mHz source power of the reaction instrument used in the step 2) is 2000-3000W, and the 2mHz pulse type bias power is 500-1500W.
Optionally, the bottom etch by-product is removed in step 3) using a pulsed bias power output mode.
Alternatively, the 13mHz source power of the reactor used in step 3) is between 500W and 1500W and the 13mHz pulsed bias power is between 100 and 1000W.
Optionally, in step 3), the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced in step 2) for deep etching the semiconductor substrate includes chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He).
Optionally, the reaction gas introduced in step 3) to remove the bottom etch by-product comprises carbon tetrafluoride (CF) 4 ) And argon (Ar).
Optionally, in step 4), the reaction gas introduced to form the sidewall oxide layer on the sidewall of the trench structure includes oxygen (O) 2 ) And argon (Ar).
Alternatively, the 13mHz source power of the reactor used in step 4) is between 2000 and 3000W.
Optionally, the number of times step 5) is performed is between 4 and 19.
Alternatively, when the shallow trench is formed in the semiconductor substrate, the reaction instruments used in steps 2) to 5) are the same reaction instrument.
Optionally, the shallow trench includes a first shallow trench and a second shallow trench, a width ratio of the second shallow trench to the first shallow trench is between 2 and 7, and a depth ratio of the second shallow trench to the first shallow trench is between 0.7 and 1.3.
The second aspect of the present application provides a method for manufacturing a shallow trench in a semiconductor substrate, comprising: 1) Providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the shape and the position of a shallow groove; 2) Performing a first main etching step, including performing deep etching on the semiconductor substrate through the first etching window to form a groove structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the groove structure; 3) Performing a bottom penetration step, including removing the bottom etch by-product; 4) Performing a groove wall protection step, including forming a side wall oxide layer on the side wall of the groove structure so as to form the shallow groove in the semiconductor substrate; 5) And performing a second main etching step, wherein the second main etching step comprises performing deep etching on the semiconductor substrate through the first etching window.
Optionally, in step 1), a surface protection layer is further formed on the semiconductor substrate, where the surface protection layer is located between the mask layer and the semiconductor substrate, and the surface protection layer has a second etching window corresponding to the first etching window.
Optionally, in the step 2) and the step 5), forming a surface etching byproduct on the surface of the mask layer while performing deep etching on the semiconductor substrate; and 3) removing the surface etching byproducts on the surface of the mask layer at the same time of removing the bottom etching byproducts.
Optionally, the semiconductor substrate is etched in a deep manner in the step 2) and the step 5) by adopting a pulse bias power output mode.
Optionally, in step 2) and step 5), the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the semiconductor substrate is etched in a deep mode by adopting a low-frequency pulse type bias power output mode in the step 2) and the step 5), the 13mHz source power of the reaction instrument used in the step 2) is between 2000W and 3000W, and the 2mHz pulse type bias power is between 500W and 1500W.
Optionally, the bottom etch by-product is removed in step 3) using a pulsed bias power output mode.
Alternatively, the 13mHz source power of the reactor used in step 3) is between 500W and 1500W and the 13mHz pulsed bias power is between 100 and 1000W.
Optionally, in step 3), the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced in the step 2) and the step 5) for deep etching the semiconductor substrate comprises chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He).
Optionally, the reaction gas introduced in step 3) to remove the bottom etch by-product (111) comprises carbon tetrafluoride (CF) 4 ) And argon (Ar).
Optionally, in step 4), the reaction gas introduced to form the sidewall oxide layer on the sidewall of the trench structure includes oxygen (O) 2 ) And argon (Ar).
Alternatively, the 13mHz source power of the reactor used in step 4) is between 2000 and 3000W.
Alternatively, when the shallow trench is formed in the semiconductor substrate, the reaction apparatus used in steps 2) to 5) is implemented as the same reaction apparatus.
A third aspect of the present application provides a shallow trench structure of a semiconductor substrate, comprising: the first shallow groove and the second shallow groove are formed in the semiconductor substrate, the width ratio of the second shallow groove to the first shallow groove is 2-7, and the depth ratio of the second shallow groove to the first shallow groove is 0.7-1.3.
Optionally, a surface protection layer is further formed on the semiconductor substrate, and the surface protection layer is located between the mask layer and the semiconductor substrate.
The manufacturing method of the shallow trench of the semiconductor substrate is circularly carried out in three steps of main etching, bottom penetration and trench wall protection, and by means of a low-frequency pulse bias power output mode, a low duty ratio and a mode of forming a sidewall oxide layer on the trench wall, the flaring phenomenon is relieved in the etching process, byproducts at the bottom and the opening of the shallow trench are effectively removed, the problem of etching termination is avoided, the depth of the trench is ensured to reach the target etching depth, the depth-to-width ratio of the shallow trench is improved, and the depth uniformity of the shallow trench is improved.
Additional features and advantages of the application will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification, illustrate the application and together with the description serve to explain, without limitation, the application. In the drawings:
FIGS. 1A-1C are schematic views of shallow trench structures fabricated according to the prior art;
FIG. 2 is a flow chart of a method for fabricating a shallow trench in a semiconductor substrate according to an embodiment of the present application;
FIG. 3 is a schematic view of a semiconductor substrate fabricated by a semiconductor substrate shallow trench fabrication method according to one embodiment of the present application;
FIG. 4 is a schematic view of another semiconductor substrate fabricated by a semiconductor substrate shallow trench fabrication method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a main etching step in a cyclic etching step in a method for fabricating shallow trenches of a semiconductor substrate according to an embodiment of the present application;
FIGS. 6A and 6B are experimental results of a continuous bias power output mode and a pulsed bias power output mode for a shallow trench main etch step;
FIG. 7A is a schematic diagram of the duty cycle of the pulsed bias power output;
FIG. 7B is an experimental result for a shallow trench main etch step using different duty cycles of pulsed bias power output;
FIG. 8A is a schematic diagram of ion energy distribution at 13.56mHz and 2 mHz;
FIG. 8B is an experimental result of using a 2mHz bias power output mode and a 13mHz bias power output mode for the shallow trench main etch step;
FIG. 9 is a schematic diagram of a bottom penetration step in a cyclical etching step in a method for fabricating shallow trenches of a semiconductor substrate according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a trench wall protection step in a cyclic etching step in a method for fabricating a shallow trench in a semiconductor substrate according to an embodiment of the present application;
Fig. 11 is a schematic view of a shallow trench formed by cyclically performing steps 2) to 4) in a method for fabricating a shallow trench in a semiconductor substrate according to an embodiment of the present application;
FIG. 12 is a schematic view of a shallow trench formed by a method for fabricating a shallow trench in a semiconductor substrate according to one embodiment of the present application;
FIG. 13 is a flow chart of a method for fabricating a shallow trench in a semiconductor substrate according to another embodiment of the present application;
FIG. 14 is a schematic view of a semiconductor substrate fabricated by a semiconductor substrate shallow trench fabrication method according to another embodiment of the present application;
FIG. 15 is a schematic view of another semiconductor substrate fabricated by a semiconductor substrate shallow trench fabrication method according to another embodiment of the present application;
FIG. 16 is a schematic diagram of a main etching step in a method for fabricating a shallow trench in a semiconductor substrate according to another embodiment of the present application;
FIG. 17 is a schematic diagram of a bottom penetration step in a method for fabricating a shallow trench in a semiconductor substrate according to another embodiment of the present application;
FIG. 18 is a schematic diagram showing a trench wall protection step in a method for fabricating a shallow trench in a semiconductor substrate according to another embodiment of the present application;
fig. 19 is a schematic view of a shallow trench formed by a method for manufacturing a shallow trench in a semiconductor substrate according to another embodiment of the present application.
Description of the reference numerals
100 semiconductor substrate 110 trench structure
111 bottom etch by-product 112 sidewall oxide
120 shallow trench 121 first shallow trench
122 second shallow trench 200 mask layer
210 first etch window 220 surface etch byproducts
300 second etched window of surface protection layer 310
Detailed Description
The following describes specific embodiments of the present application in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the application, are not intended to limit the application.
In the present application, unless otherwise indicated, terms of orientation such as "upper/above, lower/below, left/left, right/right" are generally used to refer to upper, lower, left, right as shown with reference to the drawings. "inner and outer" means inner and outer relative to the contour of the respective parts themselves.
In the drawings, the shapes of the illustrations as a result, variations are possible in accordance with manufacturing techniques and/or tolerances. Accordingly, exemplary embodiments of the present application are not limited to the specific shapes shown in the drawings, and may include shape changes caused during manufacturing. Furthermore, the various elements and regions in the figures are only schematically illustrated and thus the present application is not limited to the relative dimensions or distances illustrated in the figures.
As shown in fig. 2, the application provides a method for manufacturing a shallow trench of a semiconductor substrate, which comprises the following steps:
1) Providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the shape and the position of a shallow groove;
2) Performing main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window to form a groove structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the groove structure;
3) Performing a bottom penetration step of the cyclic etching, including removing the bottom etching byproducts;
4) A groove wall protection step of cyclic etching is carried out, which comprises the steps of forming a side wall oxide layer on the side wall of the groove structure;
5) And circularly executing the steps 2) to 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
The application provides a method for manufacturing a shallow trench of a semiconductor substrate, which is described in detail below with reference to the accompanying drawings.
First, step 1) is performed, a semiconductor substrate 100 is provided, and a mask layer 200 is formed on the semiconductor substrate 100, wherein the mask layer 200 has a first etching window 210, and the first etching window 210 defines the shape and position of the shallow trench 120, as shown in fig. 3.
Specifically, a semiconductor substrate 100 is first provided, and the material of the semiconductor substrate 100 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
A mask layer 200 is formed on the semiconductor substrate 100, and the mask layer 200 is formed of a material including, but not limited to, silicon nitride, silicon oxide, and carbon, among other materials having a high selectivity to the semiconductor substrate 100. The mask layer 200 has a first etch window 210, which first etch window 210 may define the shape and location of the shallow trench 120.
Optionally, in step 1), a surface protection layer 300 is further formed on the semiconductor substrate 100, where the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, and the surface protection layer 300 has a second etching window 310 corresponding to the first etching window 210, as shown in fig. 4.
Specifically, a surface protection layer 300 is further formed between the mask layer 200 and the semiconductor substrate 100, for protecting the surface of the semiconductor substrate 100, and materials of the surface protection layer 300 include, but are not limited to, silicon nitride, silicon oxide, carbon, and other materials with a high selectivity to the materials of the semiconductor substrate 100 and the mask layer 200. The surface protection layer 300 has a second etching window 310 coinciding with the first etching window 210.
Next, step 2) is performed, and a main etching step of the cyclic etching is performed, including performing deep etching on the semiconductor substrate 100 through the first etching window 210, so as to form a trench structure 110 in the semiconductor substrate 100 and a bottom etching byproduct 111 at the bottom of the trench structure 110, as shown in fig. 5.
Specifically, the semiconductor substrate 100 is etched in a deep manner through the first etching window 210, so that the trench structure 110 is formed in the semiconductor substrate 100, and non-volatile or difficult-to-remove etching byproducts are generated during the deep etching, and the etching byproducts are accumulated at the bottom of the trench structure 110 and on the surface of the mask layer 200.
Optionally, in step 2), the semiconductor substrate 100 is etched in a pulsed bias power output mode.
Specifically, referring to fig. 6A, the X-axis direction in fig. 6A is the etching time, the Y-axis direction is the depth of the shallow trench, the triangle is marked as a continuous bias power output mode, and the circle is marked as a pulsed bias power output mode. It can be seen from the experimental results that the shallow trench depth has not increased rapidly after the 4 th moment of the etching time using the continuous bias power output mode with an increase in time, indicating that the etching has stopped. The use of the pulsed bias power output mode, in which the etch time is continuously increased from time 1 to time 6, indicates that the use of the pulsed bias power output mode may improve etch termination.
Referring to fig. 6B, the X-axis direction in fig. 6B is etching time, and the Y-axis direction is shallow trench depth load, it can be found from the experimental result that, as time increases, the shallow trench depth load continuously increases, indicating that the non-uniformity of the depth continuously deteriorates, and the shallow trench depth load has exceeded 6 units when the etching time reaches the 6 th moment. And when the pulse bias power output mode is used, the shallow trench depth load is obviously not increased obviously, and when the etching time reaches the 6 th moment, the depth load is about 2 units, and the shallow trench depth load is obviously improved. Therefore, according to the experimental result, the main etching step of the shallow trench selects the pulse bias power output mode.
Because of the increase of the aspect ratio of the shallow trench 120, a long etching time is required, if the continuous output bias power is adopted, the selectivity of the mask layer 200 to silicon is insufficient, and the mask layer 200 is etched while the semiconductor substrate 100 is etched, resulting in a flaring phenomenon. In the embodiment of the application, the flaring phenomenon can be improved by adopting the pulse bias power output mode, the bias power can be quickly converted between the output mode and the closing mode under a certain frequency in the pulse bias power output mode, the consumption of the mask layer 200 can be reduced, the flaring phenomenon can be improved, and the selection ratio of the mask layer 200 to silicon can be improved in the closing mode.
Optionally, in step 2), the duty cycle of the pulsed bias power output is between 10% and 60%.
Specifically, referring to fig. 7A, the duty cycle refers to the ratio of the time of the bias power in the output mode to the total time in one pulse cycle, and the whole etching process has many pulse cycles. The longer the time of the output mode, the larger the duty ratio, and the shorter the time of the output mode, the smaller the duty ratio. If the bias power is always output, the duty cycle is 100% and is considered to be a continuous bias power output. Referring to fig. 7b, the x-axis direction is the duty cycle of the pulsed bias power output and the Y-axis direction is the deep load. From the experimental results, it can be found that the smaller the duty ratio is, the better the depth load can be obtained, and therefore the effect of improving the depth load can be achieved by optimizing the duty ratio. According to the technical scheme of the application, the uniformity of the etching depth of the shallow trench 120 can be improved by adjusting the duty ratio, wherein the smaller the duty ratio is, the better the uniformity of the etching depth of the shallow trench 120 is. Preferably, in the embodiment of the present application, the duty cycle of the pulse bias power output is between 10% and 60%.
Optionally, the semiconductor substrate 100 is etched in a deep manner in the step 2) by using a low-frequency pulse bias power output mode, wherein the 13mHz source power of the reaction apparatus used in the step 2) is 2000W to 3000W, and the 2mHz pulse bias power is 500W to 1500W.
Specifically, referring to fig. 8a, the x-axis direction is ion energy, and the Y-axis direction is ion energy distribution, it is obvious that most of ion energy is greater than 1000eV at low frequency (2 mHz), and most of ion energy is lower than 500eV at high frequency (13.56 mHz). Referring to fig. 8b, the x-axis direction is 2mHz and 13mHz conditions, the main Y-axis direction (left) is shallow trench depth, and the auxiliary Y-axis direction (right) is shallow trench bottom width. From the experimental results, it can be found that under the same etching time, a deeper shallow trench depth can be obtained at 2mHz, the shallow trench depth corresponding to 2mHz is about 2.5 units, and the shallow trench depth corresponding to 13mHz is about 2.2 units. Under the same etching time, a larger bottom width can be obtained at 2mHz, the bottom width corresponding to 2mHz is about 12 units, and the bottom width corresponding to 13mHz is about 6 units. Experimental results prove that the lower frequency has higher ion energy, and ions can reach deeper shallow trench etched silicon substrate. Therefore, according to experimental results, the shallow trench main etching step selects a low-frequency bias power output mode. Preferably, a 2mHz pulse type bias power output mode can be adopted, the bias power is 500-1500W, the cavity temperature of a reaction instrument used in deep etching is 50-80 ℃, the temperature of an electrostatic chuck is 20-70 ℃, the cavity pressure is 5 mT-30 mT, and the 13mHz source power is 2000-3000W.
Optionally, the reaction gas introduced in step 2) for deep etching the semiconductor substrate 100 includes chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He).
Specifically, in the embodiment of the application, the reaction gas introduced during the deep etching includes chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He), wherein chlorine (Cl 2 ) The main etching gas reacts with the semiconductor substrate 100, and the resultant product is carried out by the gas in the reaction apparatus.
Continuing with step 3), a bottom penetration step of the cyclical etch is performed, including removing the bottom etch by-product 111, as shown in FIG. 9.
Specifically, when the semiconductor substrate 100 is etched in a deep manner, a bottom etching byproduct 111 is generated at the bottom of the trench structure 110, and the bottom etching byproduct 111 is not easy to be discharged due to the reduced critical dimension, so that the etching rate is affected, and as the etching time increases, a large amount of bottom etching byproduct 111 accumulates, and etching reactants cannot contact the bottom of the trench structure 110, so that the etching is finished in advance, and the trench structure 110 cannot reach the target etching depth. Therefore, after the deep etch, the bottom etch by-product 111 needs to be removed to ensure that the reactant can contact the bottom of the trench structure 110, ensuring the etching rate and etching depth of the trench structure 110.
Optionally, the bottom etch by-product 111 is removed in step 3) using a pulsed bias power output mode.
Specifically, the pulsed bias power output mode can rapidly switch bias power between the output mode and the off mode at a certain frequency, and bottom etching byproducts 111 are not generated in the off mode, thereby facilitating the discharge of the bottom etching byproducts 111, avoiding the etching termination, improving the etching rate, and ensuring the etching depth.
Optionally, in step 2), a surface etching byproduct 220 is formed on the surface of the mask layer 200 while performing deep etching on the semiconductor substrate 100; in step 3), the surface etch byproducts 220 on the surface of the mask layer 200 are removed simultaneously with the removal of the bottom etch byproducts 111, as shown in fig. 5 and 9.
Specifically, during the deep etching process, when the bottom etching byproduct 111 is discharged from the bottom of the trench structure 110, a part of the bottom etching byproduct 111 accumulates on the surface of the mask layer 200 to form a surface etching byproduct 220, so that for the trench structure 110 with a small critical dimension, reactants for etching the semiconductor substrate 100 are not easy to enter from the opening of the trench structure 110, the etching rate is reduced, and as the etching time increases, the accumulated large amount of surface etching byproduct 220 can block the opening of the trench structure 110 to cause etching termination, and for the trench structure 110 with a large critical dimension, the influence of the surface etching byproduct 220 on the etching depth is small, the reactants for etching the semiconductor substrate 100 can enter the trench structure 110, and the uniformity of the etching depth is poor. Thus, the surface etch byproducts 220 on the surface of the mask layer 200 are removed at the same time as the bottom etch byproducts 111 are removed. The etching stop can be avoided, the etching rate is further improved, the etching depth is ensured, and the uniformity of the etching depth is improved.
Optionally, the chamber temperature of the reaction apparatus used in step 3) is between 50 ℃ and 80 ℃, the temperature of the electrostatic chuck is between 20 ℃ and 70 ℃, the chamber pressure is between 5mT and 30mT, the 13mHz source power is between 500W and 1500W, and the 13mHz pulse bias power is between 100W and 1000W.
Optionally, in step 3), the duty cycle of the pulsed bias power output is between 10% and 60%.
Specifically, the shallow trench 120 etch depth uniformity may be improved by adjusting the duty cycle. The smaller the duty cycle, the better the uniformity of the etch depth for the shallow trench 120. Preferably, the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced in step 3) to remove the bottom etch by-product 111 comprises carbon tetrafluoride (CF) 4 ) And argon (Ar).
Specifically, the fluorine-based gas can easily purge the bottom etch by-product 111 and be carried out by the gases in the reactor.
Continuing with step 4), a trench wall protection step of the cyclical etching is performed, including forming a sidewall oxide layer 112 on the sidewalls of the trench structure 110, as shown in fig. 10.
Specifically, the sidewall oxide layer 112 can protect the sidewall of the trench structure 110, and improve the flaring phenomenon during the main etching step of the cyclic etching.
Optionally, in step 4), the reaction gas introduced to form the sidewall oxide layer 112 on the sidewall of the trench structure 110 includes oxygen (O) 2 ) And argon (Ar).
Specifically, in forming the sidewall oxide layer 112, the gas introduced into the reactor includes oxygen (O 2 ) And argon (Ar), oxygen (O) 2 ) The following reaction occurs with the sidewalls of trench structure 110:
Si(s)+O 2 (g)→SiO 2 (s)
silicon dioxide (SiO) 2 ) The sidewall oxide layer 112 is formed on the sidewall of the trench structure 110, which can protect the sidewall of the trench structure 110, improve the flaring phenomenon during the main etching step of the cyclic etching, and simultaneously can also control the oxygen (O) 2 ) The amount of the height adjusts the angle of the sidewalls of the trench structure 110.
Optionally, the reaction apparatus used in step 4) has a chamber temperature of 50-80 ℃, an electrostatic chuck temperature of 20-70 ℃, a chamber pressure of 5-30 mt, and a 13mhz source power of 2000-3000W.
In step 5), steps 2) to 4) are cyclically performed until the depth of the trench structure 110 reaches a predetermined depth to form the shallow trench 120 in the semiconductor substrate 100, as shown in fig. 11.
Specifically, in order to simultaneously improve the flaring phenomenon of the shallow trench 120 caused by insufficient sidewall protection of the shallow trench 120, and the etch stop and the depth non-uniformity of the shallow trench 120 caused by deposition of the bottom etching by-product 111, more precise control of the etch and the trench wall protection is required, and with the decrease of the critical dimension, the single-step etch has reached the limit of controlling the shallow trench 120. The etching steps are circularly performed by three steps of main etching, bottom penetration and groove wall protection, so that the shallow groove 120 can be controlled more accurately, the flaring phenomenon is improved, the depth of the shallow groove 120 reaches the target etching depth, and the uniformity of the depth of the shallow groove 120 is improved.
Optionally, the number of times step 5) is performed is between 4 and 19.
Specifically, the three steps of main etching, bottom penetration and groove wall protection are circularly performed for 4-19 times, the depth of the groove structure 110 can reach the target depth, the shallow groove 120 is formed, and the depth uniformity of the shallow groove 120 is good.
Alternatively, when the shallow trench 120 is formed in the semiconductor substrate 100, the reaction instruments used in steps 2) to 5) are the same reaction instrument.
Specifically, the three steps of main etching, bottom penetration and groove wall protection use the same reaction instrument, and the shallow groove 120 with good depth uniformity, proper angle and reaching the target etching depth can be etched in a short time by changing the working parameters of the reaction instrument and the gas introduced into the reaction instrument to switch between different steps.
Optionally, the shallow trench 120 includes a first shallow trench 121 and a second shallow trench 122, a width ratio of the second shallow trench 122 to the first shallow trench 121 is between 2 and 7, and a depth ratio of the second shallow trench 122 to the first shallow trench 121 is between 0.7 and 1.3.
Specifically, by the method for manufacturing the shallow trench of the semiconductor substrate provided by the application, shallow trenches 120 with different widths can be manufactured, wherein the shallow trench 120 comprises a first shallow trench 121 and a second shallow trench 122, the ratio of the width of the second shallow trench 122 to the width of the first shallow trench 121 is 2-7, and the ratio of the depth of the second shallow trench 122 to the depth of the first shallow trench 121 is 0.7-1.3, as shown in fig. 12.
As shown in fig. 13, the present application further provides another method for manufacturing a shallow trench of a semiconductor substrate, which includes the following steps: 1) Providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the shape and the position of a shallow groove; 2) Performing a main etching step, including performing deep etching on the semiconductor substrate through the first etching window to form a groove structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the groove structure; 3) Performing a bottom penetration step, including removing the bottom etch by-product; 4) Performing a groove wall protection step, including forming a side wall oxide layer on the side wall of the groove structure so as to form the shallow groove in the semiconductor substrate; 5) And performing a second main etching step, wherein the second main etching step comprises performing deep etching on the semiconductor substrate through the first etching window.
The following will describe in detail another method for manufacturing shallow trenches of a semiconductor substrate according to the present application with reference to the accompanying drawings.
First, step 1) is performed, a semiconductor substrate 100 is provided, and a mask layer 200 is formed on the semiconductor substrate 100, wherein the mask layer 200 has a first etching window 210, and the first etching window 210 defines the shape and position of the shallow trench 120, as shown in fig. 14.
Specifically, a semiconductor substrate 100 is first provided, and the material of the semiconductor substrate 100 includes, but is not limited to, a single crystal or polycrystalline semiconductor material, and may be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. A mask layer 200 is formed on the semiconductor substrate 100, and the mask layer 200 is formed of a material including, but not limited to, silicon nitride, silicon oxide, and carbon, among other materials having a high selectivity to the semiconductor substrate 100. The mask layer 200 has a first etch window 210, which first etch window 210 may define the shape and location of the shallow trench 120.
Optionally, in step 1), a surface protection layer 300 is further formed on the semiconductor substrate 100, where the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, and the surface protection layer 300 has a second etching window 310 corresponding to the first etching window 210, as shown in fig. 15.
Specifically, a surface protection layer 300 is further formed between the mask layer 200 and the semiconductor substrate 100, for protecting the surface of the semiconductor substrate 100, and materials of the surface protection layer 300 include, but are not limited to, silicon nitride, silicon oxide, carbon, and other materials with a high selectivity to the materials of the semiconductor substrate 100 and the mask layer 200. The surface protection layer 300 has a second etching window 310 coinciding with the first etching window 210.
Next, step 2) is performed, and a first main etching step is performed, including performing deep etching on the semiconductor substrate 100 through the first etching window 210, so as to form a trench structure 110 in the semiconductor substrate 100 and a bottom etching byproduct 111 at the bottom of the trench structure 110, as shown in fig. 16.
Specifically, the semiconductor substrate 100 is etched in a deep manner through the first etching window 210, so that the trench structure 110 is formed in the semiconductor substrate 100, and non-volatile or difficult-to-remove etching byproducts are generated during the deep etching, and the etching byproducts are accumulated at the bottom of the trench structure 110 and on the surface of the mask layer 200.
Optionally, in step 2), the semiconductor substrate 100 is etched in a pulsed bias power output mode.
Specifically, referring to fig. 6A, the X-axis direction in fig. 6A is the etching time, the Y-axis direction is the depth of the shallow trench, the triangle is marked as a continuous bias power output mode, and the circle is marked as a pulsed bias power output mode. It can be seen from the experimental results that the shallow trench depth has not increased rapidly after the 4 th moment of the etching time using the continuous bias power output mode with an increase in time, indicating that the etching has stopped. The use of the pulsed bias power output mode, in which the etch time is continuously increased from time 1 to time 6, indicates that the use of the pulsed bias power output mode may improve etch termination.
Referring to fig. 6B, the X-axis direction in fig. 6B is etching time, and the Y-axis direction is shallow trench depth load, it can be found from the experimental result that, as time increases, the shallow trench depth load continuously increases, indicating that the non-uniformity of the depth continuously deteriorates, and the shallow trench depth load has exceeded 6 units when the etching time reaches the 6 th moment. And when the pulse bias power output mode is used, the shallow trench depth load is obviously not increased obviously, and when the etching time reaches the 6 th moment, the depth load is about 2 units, and the shallow trench depth load is obviously improved. Therefore, according to the experimental result, the main etching step of the shallow trench selects the pulse bias power output mode.
Because of the increase of the aspect ratio of the shallow trench 120, a long etching time is required, if the continuous output bias power is adopted, the selectivity of the mask layer 200 to silicon is insufficient, and the mask layer 200 is etched while the semiconductor substrate 100 is etched, resulting in a flaring phenomenon. In the embodiment of the application, the flaring phenomenon can be improved by adopting the pulse bias power output mode, the bias power can be quickly converted between the output mode and the closing mode by adopting the pulse bias power output mode under a certain frequency, and the consumption of the mask layer 200 can be reduced, the flaring phenomenon can be improved, and the selection ratio of the mask layer 200 to silicon can be improved in the closing mode.
Optionally, in step 2), the duty cycle of the pulsed bias power output is between 10% and 60%.
Specifically, referring to fig. 7A, the duty cycle refers to the ratio of the time of the bias power in the output mode to the total time in one pulse cycle, and the whole etching process has many pulse cycles. The longer the time of the output mode means the larger the duty ratio, and the shorter the time of the output mode means the smaller the duty ratio. If the bias power is always output, it means that the duty cycle is 100%, which is regarded as continuous bias power output. Referring to fig. 7b, the x-axis direction is the duty cycle of the pulsed bias power output and the Y-axis direction is the deep load. From the experimental results, it can be found that the smaller the duty ratio is, the better the depth load can be obtained, and therefore the effect of improving the depth load can be achieved by optimizing the duty ratio. According to the technical scheme of the application, the longer the time in the output mode is, the larger the representation duty ratio is. The uniformity of the etching depth of the shallow trench 120 can be improved by adjusting the duty ratio, wherein the smaller the duty ratio is, the better the uniformity of the etching depth of the shallow trench 120 is. Preferably, in the embodiment of the present application, the duty cycle of the pulse bias power output is between 10% and 60%.
Optionally, the semiconductor substrate 100 is etched in a deep manner in the step 2) by using a low-frequency pulse bias power output mode, wherein the 13mHz source power of the reaction apparatus used in the step 2) is 2000W to 3000W, and the 2mHz pulse bias power is 500W to 1500W.
Specifically, referring to fig. 8a, the x-axis direction is ion energy, and the Y-axis direction is ion energy distribution, it is obvious that most of ion energy is greater than 1000eV at low frequency (2 mHz), and most of ion energy is lower than 500eV at high frequency (13.56 mHz). Referring to fig. 8b, the x-axis direction is 2mHz and 13mHz conditions, the main Y-axis direction (left) is shallow trench depth, and the auxiliary Y-axis direction (right) is shallow trench bottom width. From the experimental results, it can be found that under the same etching time, a deeper shallow trench depth can be obtained at 2mHz, the shallow trench depth corresponding to 2mHz is about 2.5 units, and the shallow trench depth corresponding to 13mHz is about 2.2 units. Under the same etching time, a larger bottom width can be obtained at 2mHz, the bottom width corresponding to 2mHz is about 12 units, and the bottom width corresponding to 13mHz is about 6 units. Experimental results prove that the lower frequency has higher ion energy, and ions can reach deeper shallow trench etched silicon substrate. Therefore, according to experimental results, the shallow trench main etching step selects a low-frequency bias power output mode. Preferably, a 2mHz pulse type bias power output mode can be adopted, the bias power is 500-1500W, the cavity temperature of a reaction instrument used in deep etching is 50-80 ℃, the temperature of an electrostatic chuck is 20-70 ℃, the cavity pressure is 5 mT-30 mT, and the 13mHz source power is 2000-3000W.
Optionally, the reaction gas introduced in step 2) for deep etching the semiconductor substrate 100 includes chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He).
Specifically, in the embodiment of the application, the reaction gas introduced during the deep etching includes chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He), wherein chlorine (Cl 2 ) The main etching gas reacts with the semiconductor substrate 100, and the resultant product is carried out by the gas in the reaction apparatus.
Continuing with step 3), a bottom penetration step is performed, including removing the bottom etch by-product 111, as shown in FIG. 17.
Specifically, when the semiconductor substrate 100 is etched in a deep manner, a bottom etching byproduct 111 is generated at the bottom of the trench structure 110, and the bottom etching byproduct 111 is not easy to be discharged due to the reduced critical dimension, so that the etching rate is affected, and as the etching time increases, a large amount of bottom etching byproduct 111 accumulates, and etching reactants cannot contact the bottom of the trench structure 110, so that the etching is finished in advance, and the trench structure 110 cannot reach the target etching depth. Therefore, after the deep etching, the bottom etch by-product 111 needs to be removed to ensure that the reactant can contact the bottom of the trench structure 110, and ensure the etching rate and etching depth of the trench structure 110.
Optionally, the bottom etch by-product 111 is removed in step 3) using a pulsed bias power output mode.
Specifically, the pulsed bias power output mode can rapidly switch bias power between the output mode and the off mode at a certain frequency, and bottom etching byproducts 111 are not generated in the off mode, thereby facilitating the discharge of the bottom etching byproducts 111, avoiding the etching termination, improving the etching rate, and ensuring the etching depth.
Optionally, in step 2), a surface etching byproduct 220 is formed on the surface of the mask layer 200 while performing deep etching on the semiconductor substrate 100; in step 3), the surface etch byproducts 220 on the surface of the mask layer 200 are removed simultaneously with the removal of the bottom etch byproducts 111, as shown in fig. 16 and 17.
Specifically, during the deep etching process, when the bottom etching byproduct 111 is discharged from the bottom of the trench structure 110, a part of the bottom etching byproduct 111 accumulates on the surface of the mask layer 200 to form a surface etching byproduct 220, so that for the trench structure 110 with a small critical dimension, reactants for etching the semiconductor substrate 100 are not easy to enter from the opening of the trench structure 110, the etching rate is reduced, and as the etching time increases, the accumulated large amount of surface etching byproduct 220 can block the opening of the trench structure 110 to cause etching termination, and for the trench structure 110 with a large critical dimension, the influence of the surface etching byproduct 220 on the etching depth is small, the reactants for etching the semiconductor substrate 100 can enter the trench structure 110, and the uniformity of the etching depth is poor. Thus, the surface etch byproducts 220 on the surface of the mask layer 200 are removed at the same time as the bottom etch byproducts 111 are removed. The etching stop can be avoided, the etching rate is further improved, the etching depth is ensured, and the uniformity of the etching depth is improved.
Optionally, the chamber temperature of the reaction apparatus used in step 3) is between 50 ℃ and 80 ℃, the temperature of the electrostatic chuck is between 20 ℃ and 70 ℃, the chamber pressure is between 5mT and 30mT, the 13mHz source power is between 500W and 1500W, and the 13mHz pulse bias power is between 100W and 1000W.
Optionally, in step 3), the duty cycle of the pulsed bias power output is between 10% and 60%.
Specifically, the shallow trench 120 etch depth uniformity may be improved by adjusting the duty cycle. The smaller the duty cycle, the better the uniformity of the etch depth for the shallow trench 120. Preferably, the duty cycle of the pulsed bias power output is between 10% and 60%.
Optionally, the reaction gas introduced in step 3) to remove the bottom etch by-product 111 comprises carbon tetrafluoride (CF) 4 ) Andargon (Ar).
Specifically, the fluorine-based gas can easily purge the bottom etch by-product 111 and be carried out by the gases in the reactor.
Continuing with step 4), a trench wall protection step is performed, including forming a sidewall oxide layer 112 on the sidewalls of the trench structure 110 to form the shallow trench 120 in the semiconductor substrate 100, as shown in fig. 18.
Specifically, after the bottom etching by-product 111 is removed, the sidewall of the trench structure 110 is oxidized, and a sidewall oxide layer 112 is formed on the sidewall, so that the shallow trench 120 is formed, and the sidewall oxide layer 112 can protect the sidewall of the shallow trench 120.
Optionally, in step 4), the reaction gas introduced to form the sidewall oxide layer 112 on the sidewall of the trench structure 110 includes oxygen (O) 2 ) And argon (Ar).
Specifically, in forming the sidewall oxide layer 112, the gas introduced into the reactor includes oxygen (O 2 ) And argon (Ar), oxygen (O) 2 ) The following reaction occurs with the sidewalls of trench structure 110:
Si(s)+O 2 (g)→SiO 2 (s)
silicon dioxide (SiO) 2 ) The sidewall oxide layer 112 is formed on the sidewall of the trench structure 110 to protect the sidewall of the shallow trench 120, and oxygen (O) is introduced by adjusting 2 ) The amount of the height adjusts the angle of the sidewalls of the trench structure 110.
Optionally, the reaction apparatus used in step 4) has a chamber temperature of 50-80 ℃, an electrostatic chuck temperature of 20-70 ℃, a chamber pressure of 5-30 mt, and a 13mhz source power of 2000-3000W.
And then executing step 5), and performing a second main etching step, wherein the second main etching step comprises performing deep etching on the semiconductor substrate through the first etching window.
Specifically, the second main etching step of step 5) in the present application is the same as the first main etching step of step 2), so that description thereof will be omitted. The etching may be performed using existing etching techniques after step 5) is performed, or steps 3) and 4) may not be performed after the shallow trench 120 depth reaches the design requirement.
Alternatively, when the shallow trench 120 is formed in the semiconductor substrate 100, the reaction apparatus used in steps 2) to 5) is the same reaction apparatus.
Specifically, the three steps of main etching, bottom penetration and groove wall protection use the same reaction instrument, and the shallow groove 120 with good depth uniformity, proper angle and reaching the target etching depth can be etched in a short time by changing the working parameters of the reaction instrument and the gas introduced into the reaction instrument to switch between different steps.
Optionally, the shallow trench 120 includes a first shallow trench 121 and a second shallow trench 122, where a width ratio of the second shallow trench 122 to the first shallow trench 121 is between 2 and 7, and a depth ratio of the second shallow trench 122 to the first shallow trench 121 is between 0.7 and 1.3, as shown in fig. 19.
Specifically, by the method for manufacturing shallow trenches of the semiconductor substrate, shallow trenches 120 with different widths can be manufactured, wherein the ratio of the widths of the second shallow trench 122 to the first shallow trench 121 is 2-7, and the ratio of the depths of the second shallow trench 122 to the first shallow trench 121 is 0.7-1.3.
As shown in fig. 12, the present application further provides a semiconductor substrate shallow trench structure, which is formed by adopting the method for manufacturing a semiconductor substrate shallow trench provided by the present application, and the semiconductor substrate shallow trench structure includes: a first shallow trench 121 and a second shallow trench 122 formed in the semiconductor substrate 100, wherein the ratio of the width of the second shallow trench 122 to the first shallow trench 121 is 2-7, a mask layer 200 is formed on the semiconductor substrate, and the ratio of the depth of the second shallow trench 122 to the first shallow trench 121 is 0.7-1.3.
Optionally, a surface protection layer 300 is further formed on the semiconductor substrate 100, and the surface protection layer 300 is located between the mask layer 200 and the semiconductor substrate 100, as shown in fig. 12.
It should be noted that, the steps of the method for manufacturing a shallow trench in a semiconductor substrate described in the foregoing embodiments are all steps necessary for reflecting the technical solution of the present application and solving the technical problem of the present application, but are not limited to the above steps, and those skilled in the art will understand that other steps that are known may be further included in the method for manufacturing a shallow trench in a semiconductor substrate, and these conventional known steps are not described in detail in the present application for conciseness of the specification of the present application, but should also be considered as falling within the scope of protection of the present application.
The preferred embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the scope of the technical concept of the present application, and all the simple modifications belong to the protection scope of the present application.
In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. The various possible combinations of the application are not described in detail in order to avoid unnecessary repetition.
Moreover, any combination of the various embodiments of the application can be made without departing from the spirit of the application, which should also be considered as disclosed herein.
Claims (18)
1. The method for manufacturing the shallow trench of the semiconductor substrate is characterized by comprising the following steps of:
1) Providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the shape and the position of a shallow groove;
2) Performing main etching step of cyclic etching, including performing deep etching on the semiconductor substrate through the first etching window by adopting a pulse bias power output mode to form a groove structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the groove structure;
3) The bottom penetration step of the circular etching is carried out, wherein a pulse bias power output mode is adopted, and reaction gas which reacts with the bottom etching byproducts is introduced to remove the bottom etching byproducts and is carried out by gas in a reaction instrument;
4) A groove wall protection step of cyclic etching is carried out, which comprises the steps of forming a side wall oxide layer on the side wall of the groove structure;
5) And circularly executing the steps 2) to 4) until the depth of the groove structure reaches a preset depth so as to form the shallow groove in the semiconductor substrate.
2. The method of claim 1, wherein in step 1), a surface protection layer is further formed on the semiconductor substrate, the surface protection layer being located between the mask layer and the semiconductor substrate, the surface protection layer having a second etching window corresponding to the first etching window.
3. The method according to claim 2, wherein in the step 2), a surface etching byproduct is formed on the surface of the mask layer while performing deep etching on the semiconductor substrate;
and 3) removing the surface etching byproducts on the surface of the mask layer at the same time of removing the bottom etching byproducts.
4. The method of manufacturing shallow trenches of a semiconductor substrate according to claim 2, wherein the duty cycle of the pulsed bias power output in step 2) is between 10% and 60%; the duty cycle of the pulsed bias power output in step 3) is between 10% and 60%.
5. The method for manufacturing shallow trenches of a semiconductor substrate according to claim 2, wherein in step 2), the semiconductor substrate is deeply etched by using a low-frequency pulse bias power output mode, 13mHz source power of a reaction apparatus used in step 2) is 2000W to 3000W, and 2 hz pulse bias power is 500W to 1500W; the 13mHz source power of the reaction instrument used in the step 3) is 500-1500W, and the 13mHz pulse bias power is 100-1000W; the 13mHz source power of the reaction instrument used in the step 4) is between 2000 and 3000W.
6. The method of manufacturing a shallow trench in a semiconductor substrate according to claim 2, wherein the reaction gas introduced in step 2) for deep etching the semiconductor substrate comprises chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He); the reaction gas introduced in step 3) for removing the bottom etching byproducts comprises carbon tetrafluoride (CF) 4 ) And argon (Ar); in step 4), forming the sidewall oxide layer on the sidewall of the trench structure, wherein the reaction gas introduced into the sidewall oxide layer comprises oxygen (O) 2 ) And argon (Ar).
7. The method of claim 2, wherein the step 5) is performed for a number of times ranging from 4 to 19.
8. The method according to any one of claims 1 to 7, wherein the reaction apparatuses used in steps 2) to 5) are the same reaction apparatus when the shallow trench is formed in the semiconductor substrate.
9. The method of claim 2, wherein the shallow trench comprises a first shallow trench and a second shallow trench, wherein a width ratio of the second shallow trench to the first shallow trench is between 2 and 7, and a depth ratio of the second shallow trench to the first shallow trench is between 0.7 and 1.3.
10. The method for manufacturing the shallow trench of the semiconductor substrate is characterized by comprising the following steps of:
1) Providing a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the mask layer is provided with a first etching window, and the first etching window defines the shape and the position of a shallow groove;
2) Performing a first main etching step, including performing deep etching on the semiconductor substrate through the first etching window by adopting a pulse bias power output mode so as to form a groove structure in the semiconductor substrate and a bottom etching byproduct at the bottom of the groove structure;
3) Performing a bottom penetration step, including adopting a pulse bias power output mode, and introducing a reaction gas reacting with the bottom etching byproducts to remove the bottom etching byproducts and carry out the reaction gas by a gas in a reaction instrument;
4) Performing a groove wall protection step, including forming a side wall oxide layer on the side wall of the groove structure so as to form the shallow groove in the semiconductor substrate;
5) And performing a second main etching step, wherein the second main etching step comprises performing deep etching on the semiconductor substrate through the first etching window.
11. The method of claim 10, wherein in step 1), a surface protection layer is further formed on the semiconductor substrate, the surface protection layer being located between the mask layer and the semiconductor substrate, the surface protection layer having a second etching window corresponding to the first etching window.
12. The method of claim 11, wherein in step 2) and step 5), surface etching byproducts are formed on the surface of the mask layer while performing deep etching on the semiconductor substrate;
and 3) removing the surface etching byproducts on the surface of the mask layer at the same time of removing the bottom etching byproducts.
13. The method of claim 11, wherein the duty cycle of the pulsed bias power output in step 2) and step 5) is between 10% and 60%; the duty cycle of the pulsed bias power output in step 3) is between 10% and 60%.
14. The method for manufacturing shallow trenches on a semiconductor substrate according to claim 11, wherein the semiconductor substrate is etched in a deep manner by using a low-frequency pulse bias power output mode in step 2) and step 5), the 13mHz source power of the reaction apparatus used in step 2) and step 5) is 2000W to 3000W, and the 2mHz pulse bias power is 500W to 1500W; the 13mHz source power of the reaction instrument used in the step 3) is 500-1500W, and the 13mHz pulse bias power is 100-1000W; the 13mHz source power of the reaction instrument used in the step 4) is between 2000 and 3000W.
15. The method of manufacturing a shallow trench in a semiconductor substrate according to claim 11, wherein the reaction gas introduced in step 2) and step 5) for deep etching the semiconductor substrate comprises chlorine (Cl) 2 ) Oxygen (O) 2 ) And helium (He), the reaction gas introduced in step 3) to remove the bottom etch by-product comprises carbon tetrafluoride (CF) 4 ) And argon (Ar), wherein the reaction gas introduced in the step 4 for forming the side wall oxide layer on the side wall of the groove structure comprises oxygen (O) 2 ) And argon (Ar).
16. The method according to any one of claims 10 to 15, wherein the reaction equipment used in steps 2) to 5) is the same reaction equipment when the shallow trench is formed in the semiconductor substrate.
17. A semiconductor substrate shallow trench structure fabricated by the semiconductor substrate shallow trench fabrication method of claim 1, comprising:
the semiconductor device comprises a first shallow trench and a second shallow trench formed in a semiconductor substrate, wherein a mask layer is formed on the semiconductor substrate, the width ratio of the second shallow trench to the first shallow trench is 2-7, and the depth ratio of the second shallow trench to the first shallow trench is 0.7-1.3.
18. The shallow trench structure of a semiconductor substrate according to claim 17, wherein a surface protection layer is further formed on the semiconductor substrate, the surface protection layer being located between the mask layer and the semiconductor substrate.
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| US11915933B2 (en) | 2020-09-18 | 2024-02-27 | Changxin Memory Technologies, Inc. | Manufacturing method of semiconductor structure |
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| WO2015074621A1 (en) * | 2013-11-25 | 2015-05-28 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method for controlling micro-loading effect of depth of shallow trenches |
| CN106653675A (en) * | 2015-08-28 | 2017-05-10 | 中芯国际集成电路制造(北京)有限公司 | Method of forming isolation structure of shallow trench |
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