CN110911295A - Bare chip and silicon wafer - Google Patents
Bare chip and silicon wafer Download PDFInfo
- Publication number
- CN110911295A CN110911295A CN201811086151.8A CN201811086151A CN110911295A CN 110911295 A CN110911295 A CN 110911295A CN 201811086151 A CN201811086151 A CN 201811086151A CN 110911295 A CN110911295 A CN 110911295A
- Authority
- CN
- China
- Prior art keywords
- test
- holes
- test holes
- redundant
- bare chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title abstract description 15
- 229910052710 silicon Inorganic materials 0.000 title abstract description 15
- 239000010703 silicon Substances 0.000 title abstract description 15
- 238000012360 testing method Methods 0.000 claims abstract description 179
- 238000011990 functional testing Methods 0.000 claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 150000002739 metals Chemical class 0.000 claims description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 28
- 230000007547 defect Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
Abstract
The embodiment of the invention discloses a bare chip and a silicon wafer. The die includes: the at least two redundancy test holes are arranged on the top layer metal of the bare chip and are respectively connected with different function test holes of the bare chip; the distance between any two redundant test holes is larger than the distance between two function test holes connected with the redundant test holes, and the redundant test holes are used for replacing the function test holes connected with the redundant test holes to be connected with the test pin cards corresponding to the bare chips. The technical scheme of the embodiment of the invention solves the technical defects of large manufacturing difficulty and high manufacturing cost of the test pin card caused by small distance between the functional test holes in the bare chip in the prior art, and increases the distance between the test pins in the test pin card by adding the redundant test holes with large distance between the holes on the bare chip, thereby reducing the manufacturing difficulty of the test pin card and further reducing the manufacturing cost of the test pin card.
Description
Technical Field
The embodiment of the invention relates to the technical field of bare chip testing, in particular to a bare chip and a silicon wafer.
Background
A die is a set of integrated circuits formed by subjecting a silicon wafer to semiconductor manufacturing processes such as oxidation, photolithography, diffusion, epitaxy, and evaporation of aluminum. In general, a single silicon wafer can be fabricated with thousands of dies. When all the dies on the crystalline silicon wafer are manufactured, all the dies need to be subjected to functional testing through the test pin card, and the dies are packaged after the functional testing is passed.
Generally, the test pin card is directly inserted into a functional test hole in the die to perform functional test on the die. Because the size of the bare chip is smaller, the distance between the function test holes on the bare chip is smaller, and thousands of bare chips are densely and densely arranged on one silicon wafer, the arrangement of the test pins on the test pin card is correspondingly denser, and the distance between the test pins is also very small.
In the process of implementing the invention, the inventor finds that the prior art has the following defects: because the distance between the function test holes on the bare chip is very short, the manufacturing difficulty of the test pin card is higher, and the manufacturing cost of the test pin card is further improved.
Disclosure of Invention
In view of this, embodiments of the present invention provide a die and a silicon wafer to reduce the difficulty in manufacturing a test probe card of the silicon wafer.
In a first aspect, an embodiment of the present invention provides a die, including:
the at least two redundancy test holes are arranged on the top layer metal of the bare chip and are respectively connected with different function test holes of the bare chip;
the distance between any two redundant test holes is larger than the distance between two connected functional test holes, and the redundant test holes are used for replacing the connected functional test holes to be connected with the test pin cards corresponding to the bare chips.
In the above die, optionally, the area of the redundant test hole is equal to or larger than the area of the functional test hole connected thereto.
In the above bare chip, optionally, the function test hole includes at least two adjacent bonding holes, where the bonding holes are used for wire bonding;
the redundant test holes are not used for routing.
In the above bare chip, optionally, the distance between any two redundant test holes is greater than a set distance threshold, and the area of the bare chip is greater than a set area threshold, where the set distance threshold matches the set area threshold.
In the above die, optionally, the redundancy test hole and the functional test hole connected thereto are connected through the top layer metal.
In the above die, optionally, at least one of the redundancy test holes provides a connection point in at least one other layer of metal than the top layer of metal;
the redundant test holes and the functional test holes connected with the redundant test holes are connected through the top layer metal and other layers of metals except the top layer metal.
In a second aspect, an embodiment of the present invention provides a silicon wafer, including:
at least one die according to any of the embodiments of the present invention.
The embodiment of the invention provides a bare chip and a silicon wafer, wherein the bare chip comprises at least two redundancy test holes which are arranged on top metal of the bare chip and are respectively connected with different function test holes of the bare chip, the distance between any two redundancy test holes is larger than the distance between the two function test holes connected with the redundancy test holes, the redundancy test holes are used for replacing the function test holes connected with the redundancy test holes to be connected with test pin cards corresponding to the bare chip, the technical defects that the test pin cards are difficult to manufacture and high in manufacturing cost due to the fact that the distance between the function test holes in the bare chip is smaller in the prior art are solved, and the distance between the test pins in the test pin cards is increased by adding the redundancy test holes with larger hole distances on the bare chip, so that the manufacturing difficulty of the test pin cards is reduced, and the manufacturing cost of the test pin cards is further reduced.
Drawings
Fig. 1 is a top view of a die according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1 is a top view of a die according to an embodiment of the invention. The die of the present embodiment specifically includes:
the test pin card comprises at least two redundancy test holes which are arranged on top layer metal of the bare chip and are respectively connected with different function test holes of the bare chip, wherein the distance between any two redundancy test holes is larger than the distance between two function test holes connected with the redundancy test holes, and the redundancy test holes are used for replacing the function test holes connected with the redundancy test holes to be connected with the test pin card corresponding to the bare chip.
As shown in fig. 1, the round holes numbered 1-11 are functional test holes, the round holes numbered 12-16 are redundant test holes, the functional test holes numbered 1-7 are bonding holes for wire bonding, and the functional test holes numbered 8-11 are holes only used for functional testing. It is exemplarily shown in fig. 1 that five redundancy test holes are provided for the die, wherein 3 redundancy test holes are provided for 3 bonding holes ( round holes 4, 6 and 7) for wire bonding, and 2 redundancy test holes are provided for holes (round holes 9 and 10) for functional test only.
It should be noted that the shape and position of the functional test holes, the shape and position of the redundant test holes, the positional relationship and area relationship between the functional test holes and the redundant test holes, and the positions and paths of the connecting lines shown in fig. 1 are all exemplary representations, and do not have any limiting effect on the dies described in this embodiment.
In this embodiment, a die is specifically a set of integrated circuits formed by performing semiconductor manufacturing processes such as oxidation, photolithography, diffusion, epitaxy, and evaporation of aluminum on a silicon wafer. Generally, the die is not packaged directly after fabrication, but needs to be packaged after passing functional testing.
Specifically, all dies on a silicon wafer are generally functionally tested simultaneously using test pin cards (the test pin cards are inserted into all functional test holes of all dies in the silicon wafer). The bare chip is provided with a function test hole on the top layer metal so as to be matched with the test pin card for function test. The functional test holes on the die may include only bonding holes for wire bonding, and may also include holes for functional test only while including bonding holes.
It can be understood that the die generally has a higher integration level, and the electronic components in the die are arranged more densely, so that the bonding holes for wire bonding in the die are also arranged more closely, and the spacing between the bonding holes is also shorter. In addition, due to limitations in the size of the die, the arrangement position of the electronic components in the die, and the like, the distance between the holes for only the functional test, and the distance between the holes for only the functional test and the bonding holes are short.
Since the distance between the bonding holes, the distance between the holes for only the function test, and the distance between the holes for only the function test and the bonding holes are short, the distance between the test pins in the test pin card is short. It can be understood that the shorter the distance between the test pins in the test pin card, the higher the manufacturing accuracy of the test pin card and thus the higher the manufacturing cost of the test pin card.
Therefore, in the embodiment, at least two redundant test holes connected with different functional test holes of the bare chip are arranged on the top metal of the bare chip, and the redundant test holes are used for replacing the functional test holes connected with the redundant test holes to be connected with the corresponding test pin cards of the bare chip. That is, the positions and sizes of the test pins on the test pin card do not need to be completely set corresponding to the functional test holes, but may be partially or completely set corresponding to the redundant test holes. Furthermore, the distance between any two redundant test holes is larger than the distance between two functional test holes connected with the redundant test holes (for example, the distance between the redundant test holes can be larger than 400um), so that the distance between a part of or all test pins in the test pin card can be correspondingly increased, and the manufacturing precision and the manufacturing cost of the test pin card are further reduced.
Further, in order to reduce the manufacturing cost of the test pin card more, redundant test holes connected with all the functional test holes on the bare chip can be correspondingly arranged. However, due to the limitations of the area of the die, the positions of the electronic components in the die, and the positions of the connecting lines in the die, some dies may not be able to set the connected redundant test holes for all the functional test holes, and at this time, the connected redundant test holes should be set for the functional test holes with relatively shorter spacing as much as possible, so as to reduce the manufacturing cost of the test pin card to the maximum.
In this embodiment, the redundant test holes may be disposed in the top metal layer and connection points of the redundant test holes may be disposed in other metal layers through connection lines. It can be understood that, since many connection lines are staggered in each layer of metal of the die, it is difficult to ensure that all the redundant test holes can be connected to the functional test holes through the top layer of metal. Therefore, it is sometimes necessary to communicate redundant test wells with functional test wells in other layers of metal. All redundant test wells are shown in fig. 1 as being connected to functional test wells by a top metal layer, for example only.
The embodiment of the invention provides a bare chip and a silicon wafer, wherein the bare chip comprises at least two redundancy test holes which are arranged on top metal of the bare chip and are respectively connected with different function test holes of the bare chip, the distance between any two redundancy test holes is larger than the distance between the two function test holes connected with the redundancy test holes, the redundancy test holes are used for replacing the function test holes connected with the redundancy test holes to be connected with test pin cards corresponding to the bare chip, the technical defects that the test pin cards are difficult to manufacture and high in manufacturing cost due to the fact that the distance between the function test holes in the bare chip is smaller in the prior art are solved, and the distance between the test pins in the test pin cards is increased by adding the redundancy test holes with larger hole distances on the bare chip, so that the manufacturing difficulty of the test pin cards is reduced, and the manufacturing cost of the test pin cards is further reduced.
On the basis of the above embodiment, the area of the redundant test hole may be equal to or larger than the area of the functional test hole connected thereto.
It will be appreciated that the thinner the test pins in the test pin card, the higher the cost of manufacturing the test pin card. Because the size of the test pin is determined by the area of the functional test hole, the larger the area of the redundant test hole for replacing the functional test hole and connecting the test pin corresponding to the bare chip is, the larger the test pin can be correspondingly set, and the manufacturing cost of the test pin card can be further reduced. Of course, the size of the die, the location of the bond wires in the top metal layer, and the size and location of the electronic components in the top metal layer may limit the area of the redundant test holes. Further, the areas of the different redundant test holes may be the same or different.
On the basis of the embodiment, the function test holes can comprise at least two adjacent bonding holes, wherein the bonding holes are used for routing; the redundant test holes are not used for routing.
Generally, most of the functional test holes of the die are bonding holes for wire bonding, and the spacing between adjacent bonding holes is generally small, wherein the bonding holes specifically refer to holes located on the die and used for connecting with pins after the die is packaged. Therefore, in this embodiment, two redundant testing holes connected to at least two adjacent bonding holes (the two redundant testing holes are not used for routing, but are only used for connecting to the test pin card to perform a functional test on the bare chip) are disposed in at least two adjacent bonding holes, so that the distance between two adjacent testing pins in the test pin card can be increased more effectively, and the manufacturing cost of the test pin card is further reduced.
On the basis of the embodiment, the distance between any two redundant test holes is larger than a set distance threshold value, and the area of the bare chip is larger than a set area threshold value, wherein the set distance threshold value is matched with the set area threshold value.
It will be appreciated that the spacing and number of redundant test holes is not arbitrarily set and should be adapted to the area of the die. In this embodiment, when the distance between any two redundant test holes is greater than the set distance threshold, the area of the die should be greater than the set area threshold, so as to ensure that the redundant test holes can be effectively arranged in the die in a manner that the distance between the redundant test holes is greater than the set distance threshold.
On the basis of the above embodiment, the redundant test wells and the functional test wells connected thereto are connected by the top layer metal.
In this embodiment, all redundant test holes all link to each other with the function test hole through top layer metal, rather than linking to each other through other layers of metals beyond the top layer metal, so set up and just need not to set up the tie point of redundant test hole in above-mentioned other layers of metals through the connecting wire, reduced the preparation degree of difficulty of redundant test hole, and then reduced the preparation degree of difficulty of bare chip.
On the basis of the embodiment, at least one redundant test hole is provided with a connecting point in at least one other layer of metal except the top layer of metal; the redundant test holes and the functional test holes connected with the redundant test holes are connected through the top metal and/or through other layers of metals except the top metal.
It can be understood that if more redundant test holes are added, for example, a corresponding redundant test hole is added corresponding to each functional test hole, then, because some connecting wires and electronic components are already arranged in the top metal layer, it may be difficult to connect all the redundant test holes to the corresponding functional test holes through the top metal layer. At this time, it is necessary to implement connection between one or more redundant test holes and the functional test hole in another layer of metal other than the top layer of metal, and accordingly, it is necessary to provide connection points of the redundant test holes in the another layer of metal through connection lines. Further, the connection of the redundant test holes to the functional test holes may be implemented in a plurality of different above-mentioned other layers of metal. Therefore, more redundant test holes can be added, so that the manufacturing cost of the test pin card is further reduced.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (7)
1. A die, comprising:
the at least two redundancy test holes are arranged on the top layer metal of the bare chip and are respectively connected with different function test holes of the bare chip;
the distance between any two redundant test holes is larger than the distance between two connected functional test holes, and the redundant test holes are used for replacing the connected functional test holes to be connected with the test pin cards corresponding to the bare chips.
2. The die of claim 1, wherein the area of the redundant test hole is equal to or greater than the area of the functional test hole connected thereto.
3. The die of claim 1, wherein the functional test holes comprise at least two adjacent bonding holes, wherein the bonding holes are used for wire bonding;
the redundant test holes are not used for routing.
4. The die of claim 1, wherein a pitch of any two of the redundant test holes is greater than a set distance threshold, and an area of the die is greater than a set area threshold, wherein the set distance threshold matches the set area threshold.
5. The die of any of claims 1-4, wherein the redundancy test holes and the functional test holes connected thereto are connected through the top layer metal.
6. The die of any of claims 1-4, wherein at least one of the redundant test holes provides a connection point in at least one other layer of metal than the top layer of metal;
the redundant test holes and the functional test holes connected with the redundant test holes are connected through the top layer metal and other layers of metals except the top layer metal.
7. A crystalline silicon wafer, comprising:
at least one die of any of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811086151.8A CN110911295A (en) | 2018-09-18 | 2018-09-18 | Bare chip and silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811086151.8A CN110911295A (en) | 2018-09-18 | 2018-09-18 | Bare chip and silicon wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110911295A true CN110911295A (en) | 2020-03-24 |
Family
ID=69813512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811086151.8A Pending CN110911295A (en) | 2018-09-18 | 2018-09-18 | Bare chip and silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110911295A (en) |
-
2018
- 2018-09-18 CN CN201811086151.8A patent/CN110911295A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8664540B2 (en) | Interposer testing using dummy connections | |
| US8956889B2 (en) | Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC) | |
| US10679912B2 (en) | Wafer scale testing and initialization of small die chips | |
| US20150255373A1 (en) | Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer | |
| US7998853B1 (en) | Semiconductor device with through substrate vias | |
| US11119146B1 (en) | Testing of bonded wafers and structures for testing bonded wafers | |
| US20080231302A1 (en) | Wafer translator having metallization pattern providing high density interdigitated contact pads for component | |
| CN111444666A (en) | Method for extracting and winding transistor pins in MO L process | |
| US20090008799A1 (en) | Dual mirror chips, wafer including the dual mirror chips, multi-chip packages, methods of fabricating the dual mirror chip, the wafer, and multichip packages, and a method for testing the dual mirror chips | |
| US8860448B2 (en) | Test schemes and apparatus for passive interposers | |
| US20070035318A1 (en) | Donut-type parallel probe card and method of testing semiconductor wafer using same | |
| JP4592634B2 (en) | Semiconductor device | |
| US8312407B2 (en) | Integration of open space/dummy metal at CAD for physical debug of new silicon | |
| CN116338413B (en) | Testing method and testing device for system on chip | |
| CN116344441B (en) | Chip packaging method and computer readable storage medium | |
| CN110911295A (en) | Bare chip and silicon wafer | |
| US20200303268A1 (en) | Semiconductor device including residual test pattern | |
| CN102023236A (en) | Test structure and test method | |
| WO2008127541A1 (en) | Fully tested wafers having bond pads undamaged by probing and applications thereof | |
| Wang et al. | Prebond testing and test-path design for the silicon interposer in 2.5-D ICs | |
| JPH09127188A (en) | Method for forming integrated circuit and system for inspecting die on wafer | |
| JP2009289767A (en) | Manufacturing method of semiconductor device, and the semiconductor device | |
| CN111863755A (en) | Semiconductor structure and preparation method thereof | |
| US11257723B2 (en) | Inspection system and method for inspecting semiconductor package, and method of fabricating semiconductor package | |
| CN111444668B (en) | Method for carrying out layout wiring on transistors in array to be tested one by one |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Applicant after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Applicant before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
|
| CB02 | Change of applicant information |