CN110909661A

CN110909661A - Fingerprint identification display panel and fingerprint identification display device

Info

Publication number: CN110909661A
Application number: CN201911136250.7A
Authority: CN
Inventors: 邹宗骏; 孙莹; 许育民
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-11-19
Filing date: 2019-11-19
Publication date: 2020-03-24
Anticipated expiration: 2039-11-19
Also published as: CN110909661B

Abstract

The invention provides a fingerprint identification display panel and a fingerprint identification display device, which comprise a scanning circuit, wherein the scanning circuit comprises a plurality of cascaded shift registers, each shift register comprises a first node and a second node, and the level of signals of the first node and the second node in the same shift register are opposite; the fingerprint identification display panel further comprises a plurality of fingerprint identification units, each fingerprint identification unit comprises a first selection control end and a second selection control end, the first selection control end is electrically connected with the first node of one of the shift registers, and the second selection control end is electrically connected with the second node of one of the shift registers. The invention can effectively reduce the frames of the fingerprint identification display panel and the fingerprint identification display device.

Description

Fingerprint identification display panel and fingerprint identification display device

[ technical field ] A method for producing a semiconductor device

The present invention relates to the field of technologies, and in particular, to a fingerprint identification display panel and a fingerprint identification display device including the same.

[ background of the invention ]

The fingerprint of a human body has uniqueness and invariance, so that the safety performance of fingerprint identification is stronger, and meanwhile, the fingerprint identification is simple to operate, so that the fingerprint identification is widely applied to various fields, such as the technical field of display. In the field of display technology, taking a mobile phone as an example, when the mobile phone is unlocked or a specific application program of the mobile phone is opened, the operation can be completed through fingerprint identification.

However, fingerprint identification requires to add a fingerprint identification driving circuit connected to a corresponding fingerprint identification sensing unit, and in the prior art, the fingerprint identification driving circuit is disposed in a frame area of the display device. However, the frame region of the display device is further provided with a gate driving circuit for driving display, and then the fingerprint identification driving circuit is arranged in the frame region of the display device, so that not only the width of the frame of the display device is increased and the display device is not in line with the development trend of narrow frames, but also the distribution of the gate driving circuit for driving display is affected, and further the display effect of the display device is possibly affected.

[ summary of the invention ]

In order to solve the above technical problems, the present invention provides a fingerprint identification display panel and a fingerprint identification display device including the fingerprint identification display panel.

In a first aspect, an embodiment of the present invention provides a fingerprint identification display panel, including a scanning circuit, where the scanning circuit includes a plurality of cascaded shift registers, each shift register includes a first node and a second node, and the levels of signals of the first node and the second node in the same shift register are opposite; the fingerprint identification display panel further comprises a plurality of fingerprint identification units, each fingerprint identification unit comprises a first selection control end and a second selection control end, the first selection control end is electrically connected with the first node of one of the shift registers, and the second selection control end is electrically connected with the second node of one of the shift registers.

In a second aspect, an embodiment of the present invention provides a fingerprint identification display panel, including a first scanning circuit and a second scanning circuit, where the first scanning circuit and the second scanning circuit each include: a plurality of cascaded shift registers, wherein each shift register comprises a first node and a second node, and the level of signals of the first node and the second node in the same shift register are opposite; the fingerprint identification display panel further comprises a plurality of fingerprint identification units, each fingerprint identification unit comprises a first selection control end and a second selection control end, the first selection control end is electrically connected with the first node of one shift register of the first scanning circuit, and the second selection control end is electrically connected with the second node of one shift register of the second scanning circuit; alternatively, the first selection control terminal is electrically connected to the first node of one of the shift registers of the second scanning circuit, and the second selection control terminal is electrically connected to the second node of one of the shift registers of the first scanning circuit.

In a third aspect, an embodiment of the present invention further provides a fingerprint identification display device, including the fingerprint identification display panel provided in the first aspect or the second aspect.

Compared with the prior art, the fingerprint identification display panel and the fingerprint identification display device provided by the embodiment of the invention have the advantages that two control ends in the fingerprint identification unit are connected to two different nodes of the shift register, namely, at least part of the shift register in the grid drive circuit for driving display is multiplexed into the fingerprint identification drive circuit, so that the arrangement of the fingerprint identification drive circuit is reduced, and the frames of the fingerprint identification display panel and the fingerprint identification display device can be greatly reduced.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic top view of a fingerprint identification display panel according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a timing diagram corresponding to the shift register shown in FIG. 3;

FIG. 5 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another shift register according to an embodiment of the present invention;

fig. 7 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

FIG. 8 is a timing signal diagram corresponding to the shift register shown in FIG. 7;

FIG. 9 is a schematic top view of another fingerprint identification display panel according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of the structure of the shift register and scan module of FIG. 9;

fig. 11 is a schematic circuit diagram of a shift register and an output module according to an embodiment of the present invention;

FIG. 12 is a timing signal diagram corresponding to the shift register and output block shown in FIG. 11;

fig. 13 is a schematic diagram of a circuit configuration of a fingerprint identification unit and a connection between output terminals of the fingerprint identification unit according to an embodiment of the present invention;

FIG. 14 is a timing signal diagram for each port of the circuit configuration shown in FIG. 13 in which the fingerprint identification unit and the output of the fingerprint identification unit are connected;

FIG. 15 is a schematic diagram of a shift register and a fingerprint identification unit of FIG. 1;

FIG. 16 is a schematic top view of a fingerprint identification display panel according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of the connection of two cascaded shift registers of FIG. 16 to a fingerprinting unit;

FIG. 18 is a schematic top view of a fingerprint identification display panel according to another embodiment of the present invention;

FIG. 19 is a schematic diagram of the two shift registers of FIG. 18 in the first and second scanning circuits, respectively, coupled to a fingerprint identification unit;

FIG. 20 is a timing signal diagram for the two shift registers of FIG. 19;

fig. 21 is a schematic structural diagram of a fingerprint identification display device according to an embodiment of the present invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, etc. may be used herein to describe devices in accordance with embodiments of the present invention, these devices should not be limited by these terms. These terms are only used to distinguish one device from another. For example, a first device may also be referred to as a second device, and similarly, a second device may also be referred to as a first device, without departing from the scope of embodiments of the present invention.

In view of the problems in the fingerprint identification display device mentioned in the background section, an embodiment of the present invention provides a fingerprint identification display panel, including a scan circuit including a plurality of shift registers connected in cascade, each shift register including a first node and a second node, the levels of signals of the first node and the second node in the same shift register being opposite; the fingerprint identification display panel further comprises a plurality of fingerprint identification units, each fingerprint identification unit comprises a first selection control end and a second selection control end, the first selection control end is electrically connected with a first node of one shift register, and the second selection control end is electrically connected with a second node of one shift register.

Referring to fig. 1, fig. 1 is a schematic top view of a fingerprint identification display panel according to an embodiment of the present invention, the fingerprint identification display panel includes a display area AA and a non-display area NA surrounding the display area AA, a scanning circuit 100 is disposed in the non-display area NA, the scanning circuit 100 includes a plurality of cascaded shift registers 110, each shift register 110 includes a first node EA and a second node EB, and the levels of signals of the first node EA and the second node EB in the same shift register 110 are opposite; the fingerprint recognition display panel further includes a plurality of fingerprint recognition units 120, each fingerprint recognition unit 120 including a first selection control terminal SEL1 and a second selection control terminal SEL2, the first selection control terminal SEL1 being electrically connected to the first node EA of one shift register 110, and the second selection control terminal SEL2 being electrically connected to the second node EB of one shift register 110. Here, the phrase "the first selection control terminal SEL1 is electrically connected to the first node EA of one shift register 110, and the second selection control terminal SEL2 is electrically connected to the second node EB of one shift register 110" means that the first selection control terminal SEL1 and the second selection control terminal SEL2 of each fingerprint recognition unit 120 may be electrically connected to the first node EA and the second node EB of one shift register 110, respectively, or the first selection control terminal SEL1 of each fingerprint recognition unit 120 is electrically connected to the first node EA of one shift register 110, and the second selection control terminal SEL2 thereof is electrically connected to the second node EB of the other shift register 110.

Compared with the prior art, according to the fingerprint identification display panel and the fingerprint identification display device provided by the embodiment of the invention, two control ends in the fingerprint identification unit 120 are connected to two different nodes of the shift register 110, which is equivalent to multiplexing at least part of the shift registers in the gate driving circuit for driving display into the fingerprint identification driving circuit, so that the arrangement of the fingerprint identification driving circuit is reduced, and the frame of the fingerprint identification display panel can be greatly reduced.

Specifically, the cascaded shift registers 110 are respectively the 1 st to nth shift registers, a signal input terminal IN of the ith shift register is connected to the cascade terminal NEXT of the i-1 st shift register, and the signal input terminal IN of the 1 st shift register is connected to the start trigger signal terminal STV, where N is an integer greater than or equal to 2, and i is an integer greater than 1 and less than or equal to N. As in fig. 1, a 1 st shift register and an nth shift register are exemplarily shown.

Next, specific alternative structures of the shift register provided in the embodiment of the present invention will be described with reference to the drawings.

In an alternative implementation manner, please refer to fig. 2, fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention, in which the shift register 110 includes a node control circuit 111, a reset circuit 112, and an output circuit 113.

The node control circuit 111 is electrically connected to the reset circuit 112 and the output circuit 113 through a first node EA, and the node control circuit 111 is electrically connected to the output circuit 113 through a second node EB; the node control circuit 111 is configured to control a level of a signal of the second node EB to be opposite to a level of a signal of the first node EA according to a signal of the signal input terminal IN or a signal of the first node EA; the reset circuit 112 is used for providing a signal of a first reference signal terminal V1 to the first node EA according to the control of the signal of the first clock signal terminal CK 1; the output circuit 113 is configured to provide the signal of the second clock signal terminal CK2 to the signal output terminal GOUT of the shift register 110 according to the control of the signal of the second node EB, and is further configured to provide the signal of the second reference signal terminal V2 to the signal output terminal GOUT according to the control of the signal of the first node EA.

Referring to fig. 3, fig. 3 is a schematic circuit structure diagram of a shift register according to an embodiment of the present invention. On the basis of the shift register shown in fig. 2, the node control circuit 111 may alternatively include a first transistor T1, a second transistor T2, and a third transistor T3; a gate of the first transistor T1 is connected to the third clock signal terminal CK3, a first pole of the first transistor T1 is connected to the signal input terminal IN, a second pole of the first transistor T1 is connected to the second node EB, and the first transistor T1 is configured to selectively transmit a signal of the signal input terminal IN to the second node EB according to control of a signal of the third clock signal terminal CK 3; a gate of the second transistor T2 is connected to the first node EA, a first pole of the second transistor T2 is connected to the second reference signal terminal V2, and a second pole of the second transistor T2 is connected to the second node EB; a gate of the third transistor T3 is coupled to the signal input terminal IN, a first pole of the third transistor T3 is coupled to the second reference signal terminal V2, and a second pole of the third transistor T3 is coupled to the first node EA.

Alternatively, the reset module 112 may include a fourth transistor T4; a gate of the fourth transistor T4 is connected to the first clock signal terminal CK1, a first pole of the fourth transistor T4 is connected to the first reference signal terminal V1, and a second pole of the fourth transistor T4 is connected to the first node EA.

Alternatively, the output circuit 113 may include a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2; a gate of the fifth transistor T5 is connected to the second node EB, a first pole of the fifth transistor T5 is connected to the second clock signal terminal CK2, and a second pole of the fifth transistor T5 is connected to the signal output terminal GOUT; a gate of the sixth transistor T6 is connected to the first node EA, a first pole of the sixth transistor T6 is connected to the second reference signal terminal V2, and a second pole of the sixth transistor T6 is connected to the signal output terminal GOUT; a first plate of the first capacitor C1 is connected to the second node EB, and a second plate of the first capacitor C1 is connected to the signal output terminal GOUT; the first plate of the second capacitor C2 is connected to the first node EA, and the second plate of the second capacitor C2 is connected to the second reference signal terminal V2.

Next, the operation of the shift register shown in fig. 3 will be described with reference to a timing chart. Referring to fig. 4, fig. 4 is a timing signal diagram corresponding to the shift register shown in fig. 3. The shift register may include three stages of t1, t2, and t3 in an operation stage of normal display. In this embodiment, all the transistors are N-type transistors as an example.

At the stage t1, the signal input terminal IN and the third clock signal terminal CK3 provide a high level signal, and the first clock signal terminal CK1 and the second clock signal terminal CK2 provide a low level signal. The high level signal of the signal input terminal IN controls the third transistor T3 to be turned on, so that the low level signal of the second reference signal terminal V2 is transmitted to the first node EA, and the signal of the first node EA is a low level signal; the high level signal of the third clock signal terminal CK3 controls the first transistor T1 to be turned on, so that the high level signal of the signal input terminal IN is transmitted to the second node EB, so that the signal of the second node EB is a high level signal, and thus is opposite to the level of the signal of the first node EA; meanwhile, the high level signal of the second node EB controls the fifth transistor T5 to be turned on, so that the low level signal of the second clock signal terminal CK2 is transmitted to the signal output terminal GOUT; the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are in an off state.

At the stage t2, the second clock signal terminal CK2 provides a high level signal, and the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 provide a low level signal. Due to the function of the first capacitor C1, the signals at the second node EB and the gate of the fifth transistor T5 are kept at the high level signal, the fifth transistor T5 is kept turned on, the high level signal at the second clock signal terminal CK2 is transmitted to the signal output terminal GOUT through the fifth transistor T5, and the signal output terminal GOUT outputs an effective high level signal; due to the second capacitance C2, the signal of the first node EA remains a low level signal, thus being opposite to the level of the signal of the second node EB; the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are in an off state.

At the stage t3, the first clock signal terminal CK1 provides a high level signal, and the signal input terminal IN, the second clock signal terminal CK2 and the third clock signal terminal CK3 provide a low level signal. The high level signal of the first clock signal terminal CK1 controls the fourth transistor T4 to be turned on, so that the high level signal of the first reference signal terminal V1 is transmitted to the first node EA, and the signal of the first node EA is a high level signal; the high level signal of the first node EA controls the second transistor T2 to be turned on, so that the low level signal of the second reference signal terminal V2 is transmitted to the second node EB, and the signal of the second node EB is a low level signal, so as to be opposite to the level of the signal of the first node EA; meanwhile, the high level signal of the first node EA controls the sixth transistor T6 to be turned on, so that the low level signal of the second reference signal terminal V2 is transmitted to the signal output terminal GOUT; the first transistor T1, the third transistor T3, and the fifth transistor T5 are in an off state.

Referring to fig. 5, fig. 5 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, and the same points as those of the shift register shown in fig. 3 are not repeated, except that, on the basis of the shift register shown in fig. 3, the node control circuit 111 further includes a seventh transistor T7 and an eighth transistor T8; a gate of the seventh transistor T7 is connected to the first clock signal terminal CK1, a first pole of the seventh transistor T7 is connected to the signal input terminal IN, a second pole of the seventh transistor T7 is connected to the second node EB, and the seventh transistor T7 is configured to selectively transmit a signal of the signal input terminal IN to the second node EB according to control of a signal of the first clock signal terminal CK1, so as to stabilize a signal of the second node EB; the gate of the eighth transistor T8 is connected to the second node EB, the first pole of the eighth transistor T8 is connected to the second reference signal terminal V2, the second pole of the eighth transistor T8 is connected to the first node EA, and the eighth transistor T8 is configured to transmit the signal of the second reference signal terminal V2 to the first node EA according to the control of the signal of the second node EB, so as to stabilize the signal of the first node EA. The output circuit 113 further includes a ninth transistor T9, a gate of the ninth transistor T9 is connected to the first reference signal terminal V1, a first pole of the ninth transistor T9 is connected to the second node EB, a second pole of the ninth transistor T9 is connected to the gate of the fifth transistor T5, and the ninth transistor T9 is configured to transmit a signal of the second node EB to the gate of the fifth transistor T5 according to the control of the signal of the first reference signal terminal V1, and further maintain the level of the second node EB when the second node EB is pulled high.

With reference to fig. 4 and 5, in the present embodiment, the timing signals corresponding to the shift register are the same as those in fig. 4, and the shift register may still include three stages t1, t2 and t3 during the normal operation stage.

At the stage t1, the signal input terminal IN and the third clock signal terminal CK3 provide a high level signal, and the first clock signal terminal CK1 and the second clock signal terminal CK2 provide a low level signal. The high level signal of the signal input terminal IN controls the third transistor T3 to be turned on, so that the low level signal of the second reference signal terminal V2 is transmitted to the first node EA, and the signal of the first node EA is a low level signal; the high level signal of the third clock signal terminal CK3 controls the first transistor T1 to be turned on, so that the high level signal of the signal input terminal IN is transmitted to the second node EB, so that the signal of the second node EB is a high level signal, and thus is opposite to the level of the signal of the first node EA; the high level signal of the second node EB controls the eighth transistor T8 to be turned on, so that the low level signal of the second reference signal terminal V2 is transmitted to the first node EA, and the signal of the first node EA is more stable; the high level signal of the first reference signal terminal V1 controls the ninth transistor T9 to be turned on, such that the high level signal of the second node EB is transmitted to the gate of the fifth transistor T5, and the fifth transistor T5 is turned on, such that the low level signal of the second clock signal terminal CK2 is transmitted to the signal output terminal GOUT; the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are in an off state.

At the stage t2, the second clock signal terminal CK2 provides a high level signal, and the signal input terminal IN, the first clock signal terminal CK1 and the third clock signal terminal CK3 provide a low level signal. The high level signal of the first reference signal terminal V1 controls the ninth transistor T9 to be continuously turned on, due to the function of the first capacitor C1, signals of the second node EB and the gate of the fourth transistor T4 are kept as high level signals, the fifth transistor T5 and the eighth transistor T8 are kept to be turned on, the low level signal of the second reference signal terminal V2 is transmitted to the first node EA through the eighth transistor T8, and the signal of the first node EA is a low level signal, so that the level of the signal of the second node EB is opposite; meanwhile, a high level signal of the second clock signal terminal CK2 is transmitted to the signal output terminal GOUT through the fifth transistor T5, and the signal output terminal GOUT outputs an effective high level signal; the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are in an off state.

At the stage t3, the first clock signal terminal CK1 provides a high level signal, and the signal input terminal IN, the second clock signal terminal CK2 and the third clock signal terminal CK3 provide a low level signal. The first clock signal terminal CK1 controls the fourth transistor T4 and the seventh transistor T7 to be turned on, the high level signal of the first reference signal terminal V1 is transmitted to the first node EA through the fourth transistor T4, and the signal of the first node EA is a high level signal; the low level signal of the signal input terminal IN is transmitted to the second node EB through the seventh transistor T7, and the signal of the second node EB is a low level signal so as to be opposite to the level of the signal of the first node EA; the high level signal of the first node EA controls the second transistor T2 and the sixth transistor T6 to be turned on, and the low level signal of the second reference signal terminal V2 is transmitted to the second node EB through the second transistor T2 to stabilize the low level signal of the second node EB; the low level signal of the second reference signal terminal V2 is transmitted to the signal output terminal GOUT through the sixth transistor T6; the high level signal of the first reference signal terminal V1 controls the ninth transistor T9 to be continuously turned on, so that the low level signal of the second node EB is transmitted to the gate of the fifth transistor T5, and the fifth transistor T5 is turned off; the first transistor T1, the third transistor T3, and the eighth transistor T8 are in an off state.

Further, referring to fig. 6, fig. 6 is a schematic structural diagram of another shift register according to an embodiment of the present invention, IN which, based on the shift registers shown IN fig. 2, fig. 3 and fig. 5, the signal input terminal IN may include a first signal input terminal INF and a second signal input terminal INB, the first clock signal terminal CK1 may include a first sub-clock signal terminal CKV1 and a second sub-clock signal terminal CKV2, the shift register further includes a scan control circuit 114, the scan control circuit 114 is configured to provide a signal of the first signal input terminal INF to the node control circuit 111 and provide a signal of the first sub-clock signal terminal CKV1 to the reset circuit 112 according to the control of the positive scan control signal terminal U2D; and also serves to supply the signal of the second input signal terminal INB to the node control circuit 111 and the signal of the second sub-clock signal terminal CKV2 to the reset circuit 112 according to the control of the anti-scan control signal terminal D2U.

Specifically, referring to fig. 7, fig. 7 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, fig. 8 is a timing signal diagram corresponding to the shift register shown in fig. 7, in this embodiment, a scan control circuit 114 is added to the shift register shown in fig. 5 as an example, and the scan control circuit 114 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13; a gate of the tenth transistor T10 is connected to the positive scan control signal terminal U2D, a first pole of the tenth transistor T10 is connected to the first signal input terminal INF, a second pole of the tenth transistor T10 is connected to the first pole of the first transistor T1, the first pole of the seventh transistor T7, and the gate of the third transistor T3; a gate of the eleventh transistor T11 is connected to the reverse-scan control signal terminal D2U, a first pole of the eleventh transistor T11 is connected to the second signal input terminal INB, a second pole of the eleventh transistor T11 is connected to the first pole of the first transistor T1, the first pole of the seventh transistor T7, and a gate of the third transistor T3; a gate of the twelfth transistor T12 is connected to the positive scan control signal terminal U2D, a first pole of the twelfth transistor T12 is connected to the first sub-clock signal terminal CKV1, and a second pole of the twelfth transistor T12 is connected to a gate of the fourth transistor T4 and a gate of the seventh transistor T7; a gate of the thirteenth transistor T13 is connected to the reverse scan control signal terminal D2U, a first pole of the thirteenth transistor T13 is connected to the second sub-clock signal terminal CKV2, and a second pole of the thirteenth transistor T13 is connected to a gate of the fourth transistor T4 and a gate of the seventh transistor T7.

With reference to fig. 8, in the present embodiment, the shift register may include three stages of t1, t2, t3 and t4 during the working stage of normal display. Next, the operation phase will be described by taking forward scan as an example, in the forward scan, the forward scan control signal terminal U2D always provides a high level signal, the reverse scan control signal terminal D2U always provides a low level signal, the tenth transistor T10 and the twelfth transistor T12 always maintain the on state, and the eleventh transistor T11 and the thirteenth transistor T13 always maintain the off state.

At the stage t1, the first signal input terminal INF and the third clock signal terminal CK3 provide a high level signal, and the first sub-clock signal terminal CKV1, the second sub-clock signal terminal CKV2 and the second clock signal terminal CK2 provide a low level signal. The high-level signal of the first signal input terminal INF controls the third transistor T3 to be turned on, so that the low-level signal of the second reference signal terminal V2 is transmitted to the first node EA, and the signal of the first node EA is a low-level signal; the high level signal of the third clock signal terminal CK3 controls the first transistor T1 to be turned on, so that the high level signal of the first signal input terminal INF is transmitted to the second node EB through the tenth transistor T10 and the first transistor T1, so that the signal of the second node EB is a high level signal, thereby being opposite to the level of the signal of the first node EA; the high level signal of the second node EB controls the eighth transistor T8 to be turned on, so that the low level signal of the second reference signal terminal V2 is transmitted to the first node EA, and the signal of the first node EA is more stable; the high level signal of the first reference signal terminal V1 controls the ninth transistor T9 to be turned on, such that the high level signal of the second node EB is transmitted to the gate of the fifth transistor T5, and the fifth transistor T5 is turned on, such that the low level signal of the second clock signal terminal CK2 is transmitted to the signal output terminal GOUT; the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are in an off state.

At the stage T2, the second sub-clock signal terminal CKV2 provides a high level signal, the first signal input terminal INF, the third clock signal terminal CK3, the first sub-clock signal terminal CKV1 and the second clock signal terminal CK2 all provide a low level signal, the low level signal of the first signal input terminal INF controls the third transistor T3 to be turned off, the low level signal of the third clock signal terminal CK3 controls the first transistor T1 to be turned off and to be kept in a turned-off state, the high level signal of the first reference signal terminal V1 controls the ninth transistor T9 to be continuously turned on, the second node EB is in a floating state, signals of the second node EB and the gate of the fifth transistor T5 are kept as high level signals due to the first capacitor C1, the fifth transistor T5 and the eighth transistor T8 are kept to be turned on, the low level signal of the second reference signal terminal V2 is transmitted to the first node EA through the eighth transistor T8, and the signal of the first node EA is kept at a low level signal of the first node EA, so as to be opposite to the level of the signal of the second node EB; the low level signal of the second clock signal terminal CK2 is transmitted to the signal output terminal GOUT through the fifth transistor T5; the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in an off state.

At the stage t3, the second clock signal terminal CK2 provides a high level signal, and the first signal input terminal INF, the first sub-clock signal terminal CKV1, the second sub-clock signal terminal CKV2 and the third clock signal terminal CK3 provide a low level signal. The high level signal of the first reference signal terminal V1 controls the ninth transistor T9 to be continuously turned on, the second node EB is still in a floating state, due to the effect of the first capacitor C1, signals of the second node EB and the gate of the fifth transistor T5 are kept as high level signals, the fifth transistor T5 and the eighth transistor T8 are kept on, the low level signal of the second reference signal terminal V2 is transmitted to the first node EA through the eighth transistor T8, and the signal of the first node EA is kept as a low level signal, so that the level of the signal of the second node EB is opposite; meanwhile, a high level signal of the second clock signal terminal CK2 is transmitted to the signal output terminal GOUT through the fifth transistor T5, and the signal output terminal GOUT outputs an effective high level signal; the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are in an off state.

At the stage t4, the first sub-clock signal terminal CKV1 provides a high level signal, and the first signal input terminal INF, the second sub-clock signal terminal CKV2, the second clock signal terminal CK2 and the third clock signal terminal CK3 provide a low level signal. The first sub-clock signal terminal CKV1 controls the fourth transistor T4 and the seventh transistor T7 to be turned on, the high level signal of the first reference signal terminal V1 is transmitted to the first node EA through the fourth transistor T4, and the signal of the first node EA is a high level signal; the low level signal of the first signal input terminal INF is transmitted to the second node EB through the seventh transistor T7, and the signal of the second node EB is a low level signal so as to be opposite to the level of the signal of the first node EA; the high level signal of the first node EA controls the second transistor T2 and the fifth transistor T5 to be turned on, and the low level signal of the second reference signal terminal V2 is transmitted to the second node EB through the second transistor T2 to stabilize the low level signal of the second node EB; the low level signal of the second reference signal terminal V2 is transmitted to the signal output terminal GOUT through the sixth transistor T6; the high level signal of the first reference signal terminal V1 controls the ninth transistor T9 to be continuously turned on, so that the low level signal of the second node EB is transmitted to the gate of the fifth transistor T5, and the fifth transistor T5 is turned off; the first transistor T1, the third transistor T3, and the eighth transistor T8 are in an off state.

It should be noted that, when the shift register of the scanning circuit adopts the shift register shown in fig. 6 or fig. 7, a first signal input terminal of the ith shift register is connected to the cascade terminal of the ith-1 shift register, a first signal input terminal of the 1 st shift register is connected to the forward start trigger signal terminal, a second signal input terminal of the kth-1 shift register is connected to the cascade terminal of the kth shift register, and a second signal input terminal of the nth shift register is connected to the reverse start trigger signal terminal to switch between forward scanning and reverse scanning, where i and k are integers greater than 1 and less than or equal to N.

It should be noted that, IN the embodiments shown IN fig. 2 to fig. 7, the signal input terminal IN is an input terminal IN of the shift register, and the signal output terminal GOUT is a cascade terminal NEXT of the shift register.

In another alternative implementation, please refer to fig. 9 and 10, fig. 9 is a schematic top view of another fingerprint identification display panel according to an embodiment of the present invention, in this implementation, the scan circuit 100 further includes an output module 140 electrically connected to each shift register 110, fig. 10 is a schematic structural diagram of the shift register and the scan module in fig. 9, and the shift register 110 further includes an input module 115 and a latch module 116; the input module 115 is electrically connected to the latch module 116 through the first node EA; the output terminal NEXT (and the cascade terminal NEXT) of the latch module 116 is connected to the second node EB; the input module 115 is configured to generate a scan signal according to an on signal accessed from a signal input terminal IN (i.e., the input terminal IN); the latch module 116 is configured to generate an on signal according to the scan signal and latch the on signal. The output module 140 is used for scanning the scan line 130 according to the signal output by the latch module 116.

Specifically, with continuing reference to fig. 11, fig. 11 is a schematic circuit diagram of a shift register and an output module according to an embodiment of the present invention, in which the input module 115 includes a first clock inverter P1 and a first inverter M1; the input terminal of the first clock inverter P1 is electrically connected to the signal input terminal IN for receiving the turn-on signal, the output terminal of the first clock inverter P1 is electrically connected to the latch module 116 through the first node EA, the input terminal of the first inverter M1 and the second control terminal CN1 of the first clock inverter P1 are both connected to the first clock signal terminal CK1, and the output terminal of the first inverter M2 is connected to the first control terminal CP1 of the first clock inverter P1.

The latch module 116 includes a second inverter M2 and a second clock inverter P2; an input terminal of the second inverter M2 and an output terminal of the second clock inverter P2 are both connected to the first node EA, an output terminal of the second inverter M2 and an input terminal of the second clock inverter P2 are both connected to the second node EB, a first control terminal CP2 of the second clock inverter P2 is connected to the first clock signal terminal CK1, and a second control terminal CN2 of the second clock inverter P2 is connected to an output terminal of the first inverter M1.

The output module 140 includes a NAND gate NAND and an inverter module 141, a first input of the NAND gate NAND is connected to the output of the latch module 116, a second input of the NAND gate NAND is connected to the second clock signal terminal CK2, an output of the NAND gate NAND is connected to an input of the inverter module 141, the inverter module 141 includes an odd number of inverters connected in series with each other, such as 3 inverters M3, M4 and M5 connected in series with each other in fig. 10, and an output of the inverter module 141 is connected to the scan line 130.

Next, the operation principle of the shift register shown in fig. 11 will be described with reference to a timing chart. Referring to fig. 12, fig. 12 is a timing signal diagram of the shift register and the output module shown in fig. 11. The shift register may include five stages of t1, t2, t3, t4, and t5 in an operation stage of normal display.

At the stage t1, the signal input terminal IN and the first clock signal terminal CK1 provide a high level signal, and the second clock signal terminal CK2 provides a low level signal. The on signal of the signal input terminal IN at the high level is input to the input terminal of the first clock inverter P1 of the input module 115; the high level signal of the first clock signal terminal CK1 is converted into a low level signal after passing through the first inverter M1, and then the low level signal transmitted to the first control terminal CP1 of the first clock inverter P1 and the high level signal transmitted to the second control terminal CN1 of the first clock inverter P1 control the first clock inverter P1 to be turned on, the first clock inverter P1 converts the turn-on signal into a low level signal and outputs the low level signal to the first node EA, so that the signal of the first node EA is a low level signal; then, a low level signal of the Ea node passes through a second inverter M2 and is converted into a high level opening signal, and the high level opening signal is output to a second node EB, so that the signal of the second node EB is a high level signal and is opposite to the level of the signal of the first node Ea; at this time, the second clock inverter P2 is in an off state; the high level signal of the second node EB and the low level signal of the second clock signal terminal CK2 control the NAND gate NAND to output the high level signal, which is converted into the low level signal by the inverter module 141 and output by the output terminal GOUT of the output module 140.

At the stage t2, the signal input terminal IN provides a high level signal, and the first clock signal terminal CK1 and the second clock signal terminal CK2 provide a low level signal. The low level signal of the first clock signal terminal CK1 is converted into a high level signal through the first inverter M1, the high level signal is transmitted to the first control terminal CP1 of the first clock inverter P1, and the second control terminal CN1 of the first clock inverter P1 receives the low level signal of the first clock signal terminal CK1, so that the first clock inverter P1 is turned off; the low level signal transmitted to the first control terminal CP1 of the second clocked inverter P2 and the high level signal transmitted to the second control terminal CN2 of the second clocked inverter P2 control the second clocked inverter P2 to be turned on, the second clocked inverter P2 converts the on signal of the second node EB into a low level signal and outputs the low level signal to the first node EA, and the signal of the first node EA is maintained as a low level signal and is opposite to the level of the signal of the second node EB; the high level signal of the second node EB and the low level signal of the second clock signal terminal CK2 control the NAND gate NAND to output the high level signal, which is converted into the low level signal by the inverter module 141 and output by the output terminal GOUT of the output module 140.

At the stage t3, the signal input terminal IN and the second clock signal terminal CK2 provide a high level signal, and the first clock signal terminal CK1 provides a low level signal. Since the signal levels of the signal input terminal IN and the first clock signal terminal CK1 are not changed, the level of the signal of the first node EA is opposite to that of the signal of the second node EB; the high level signal of the second node EB and the high level signal of the second clock signal terminal CK2 control the NAND gate NAND to output the low level signal, which is converted into the high level signal by the inverter module 141 and output by the output terminal GOUT of the output module 140.

At the stage t4, the signal input terminal IN provides a high level signal, and the first clock signal terminal CK1 and the second clock signal terminal CK2 provide a low level signal. The conduction of the shift register 110 and the output module 140 is consistent with the phase t 2.

At the stage t5, the signal input terminal IN and the second clock signal terminal CK2 provide a low level signal, and the first clock signal terminal CK1 provides a high level signal. The low level signal of the signal input terminal IN is input to the input terminal of the first clock inverter P1 of the input module 115; the high level signal of the first clock signal terminal CK1 is converted into a low level signal after passing through the first inverter M1, and then the low level signal transmitted to the first control terminal CP1 of the first clock inverter P1 and the high level signal transmitted to the second control terminal CN1 of the first clock inverter P1 control the first clock inverter P1 to be turned on, the first clock inverter P1 converts the low level signal into a high level signal and outputs the high level signal to the first node EA, so that the signal of the first node EA is a high level signal; then, the high level signal of the first node EA is converted into a low level signal through the second inverter M2 and is output to the second node EB, so that the signal of the second node EB is a low level signal and is opposite to the level of the signal of the first node EA; at this time, the second clock inverter P2 is in an off state; the low level signal of the second node EB and the low level signal of the second clock signal terminal CK2 control the NAND gate NAND to output the high level signal, which is converted into the low level signal by the inverter module 141 and output by the output terminal GOUT of the output module 140.

In each of the above embodiments, the levels of the signals of the first node and the second node are opposite, so that the first selection control terminal of the fingerprint identification unit is electrically connected to the first node of one shift register, and the second selection control terminal of the fingerprint identification unit is electrically connected to the second node of one shift register, so as to reduce the number of the fingerprint identification driving circuits, and reduce the number of the frames of the fingerprint identification display panel.

In an alternative implementation manner, please refer to fig. 13, where fig. 13 is a schematic diagram of a circuit structure of a fingerprint identification unit and a connection between an output terminal of the fingerprint identification unit according to an embodiment of the present invention, where the fingerprint identification unit 120 may specifically include: a photodiode D, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, a storage capacitor C, a first selection control terminal SEL1, a second selection control terminal SEL2, a third selection control terminal SEL3, a reference voltage signal terminal Vbias, a driving voltage signal terminal VDD, and a photo signal output terminal Vout, wherein an anode of the photodiode D is connected to the reference voltage signal terminal Vbias, and a cathode of the photodiode D is connected to a third node E3; a gate of the fourteenth transistor T14 is connected to the third selection control terminal SEL3, a first pole of the fourteenth transistor T14 is connected to the third node E3, and a second pole of the fourteenth transistor T14 is connected to the fourth node E4; a gate of the fifteenth transistor T15 is connected to the first selection control terminal SEL1, a first pole of the fifteenth transistor T15 is connected to the fourth node E4, and a second pole of the fifteenth transistor T15 is connected to the driving voltage signal terminal VDD; a gate of the sixteenth transistor T16 is connected to the fourth node E4, a first pole of the sixteenth transistor T16 is connected to a first pole of the seventeenth transistor T17, and a second pole of the sixteenth transistor T16 is connected to the driving voltage signal terminal VDD; a gate of the seventeenth transistor T17 is connected to the second selection control terminal SEL2, and a second pole of the seventeenth transistor T17 is connected to the photo signal output terminal Vout; the first plate of the storage capacitor C is connected to the fourth node E4, and the second plate of the storage capacitor C is connected to the reference voltage signal terminal Vbias.

It should be noted that, in this embodiment, the photoelectric signal output terminal Vout of the fingerprint identification unit 120 may be connected to the selection module 150, so as to selectively export the signal output by the fingerprint identification unit 120 to the signal processing unit, thereby reducing the influence of noise signals. Specifically, the selection module 150 may include a first selection transistor T18, a second selection transistor T19, a noise read control terminal Cds-N, and a signal read control terminal Cds-S; a gate of the first selection transistor T18 is connected to the noise read control terminal Cds-N, a first pole of the first selection transistor T18 is connected to the photo signal output terminal Vout of the fingerprint recognition unit 120, and a second pole of the first selection transistor T18 is connected to the signal processing unit; the gate of the second selection transistor T19 is connected to the signal read control terminal Cds-S, the first pole of the second selection transistor T19 is connected to the photo signal output terminal Vout of the fingerprint recognition unit 120, and the second pole of the second selection transistor T19 is connected to the signal processing unit. Here, the signal processing unit is not shown in the figure, and is configured to process the read signal output by the fingerprint identification unit 120, and may be integrated in a driving chip of the fingerprint identification display panel, which is not described herein again.

The operation of the fingerprint recognition unit shown in fig. 14 will be explained with reference to the timing chart. Referring to fig. 14, fig. 14 is a timing signal diagram corresponding to each port of the circuit structure in which the fingerprint identification unit shown in fig. 13 and the output terminal of the fingerprint identification unit are connected. Referring to fig. 13 and 14, the fingerprint recognition phase includes a reset phase t11, an exposure phase t12, a charge transfer phase t14, and a signal output phase t 15.

In the reset stage T11, the first selection control terminal SEL1 turns on the fifteenth transistor T15, the driving voltage signal of the driving voltage signal terminal VDD is transmitted to the fourth node E4, and the third selection control terminal SEL3 controls the fourteenth transistor T14 to turn on.

In the exposure period T12, the fourteenth transistor T14 is turned off by the third selection control terminal SEL3, the fifteenth transistor T15 is turned on by the first selection control terminal SEL1, and the photodiode D generates the charge Q under the action of light and transmits the charge Q to the third node E3.

In the charge transfer stage T14, the fourteenth transistor T14 is controlled to be turned on by the third selection control terminal SEL3, the fifteenth transistor T15 is turned off by the first selection control terminal SEL1, and the charge Q at the third node E3 is transferred to the fourth node E4.

In the signal output stage T15, the third selection control terminal SEL3 controls the fourteenth transistor T14 to be turned off, the fourth node E4 controls the sixteenth transistor T16 to be turned on, and the second selection control terminal SEL2 controls the seventeenth transistor T17 to be turned on, so that the fingerprint identification signal is transmitted to the photoelectric signal output terminal Vout.

In addition, to reduce the influence of the noise signal, a noise output stage T13 may be further included after the exposure stage T12 before the charge transfer stage T14, in which the fourteenth transistor T14 is kept turned off, the first selection control terminal SEL1 controls the fifteenth transistor T15 to be turned off, the second selection control terminal SEL2 controls the seventeenth transistor T17 to be turned on, and the noise signal is transmitted to the photo signal output terminal Vout.

In the noise output stage T13, the noise reading control terminal Cds-N controls the first selection transistor T18 to be turned on, and the noise signal is transmitted to the signal processing unit; in the signal output stage T15, the signal reading control end Cds-S controls the conduction of the second selection transistor T19, and the fingerprint identification signal is transmitted to the signal processing unit and processed by the signal processing unit to obtain the de-noised fingerprint identification signal.

When the fingerprint identification unit 120 in the fingerprint identification display panel provided in fig. 1 adopts the structure shown in fig. 13, in the same fingerprint identification unit, the first selection control terminal SEL1 is electrically connected to the first node of one shift register, the second selection control terminal SEL1 is electrically connected to the second node of one shift register, and the signal of the third selection control terminal SEL3 needs to be provided separately, for example, the signal can be provided by a driving chip of the fingerprint identification display panel, which is not described in detail herein.

As can be seen from the circuit structure and the operation principle of the fingerprint identification unit, the low level signal duration period of the first selection control terminal SEL1 and the high level signal duration period of the second selection control terminal SEL2 are partially overlapped, and the partially overlapped time periods at least include the noise output stage t13, the charge transfer stage t14 and the signal output stage t 15. Therefore, for the same fingerprint identification unit, the duration of the low-level signal of the first node electrically connected with the first selection control end of the fingerprint identification unit is defined as a first time period, the duration of the high-level signal of the second node electrically connected with the second selection control end of the fingerprint identification unit is defined as a second time period, and the first time period and the second time period are at least partially overlapped.

In an optional implementation manner, in the same fingerprint identification unit, the first selection control terminal and the second selection control terminal are electrically connected to a first node and a second node of one shift register, respectively, that is, the first selection control terminal is electrically connected to the first node of one shift register, and the second selection control terminal is electrically connected to the second node of the same shift register, where the first time period and the second time period completely overlap. The fingerprint recognition display panel shown in fig. 1 and 9 is connected in this way. Specifically, referring to fig. 15, fig. 15 is a schematic diagram illustrating a shift register and a fingerprint identification unit in fig. 1, where the structure of the shift register is illustrated by taking the shift register shown in fig. 7 as an example, the first selection control terminal SEL1 of the fingerprint identification unit 120 is electrically connected to the first node EA of the shift register 110, and the second selection control terminal SEL2 of the fingerprint identification unit 120 is electrically connected to the second node EB of the shift register 110.

In an alternative embodiment, referring to fig. 13 and 14, when the signal of the second selection control terminal SEL2 changes from low level to high level, the seventeenth transistor T117 changes from off to on, and the gate voltage of the seventeenth transistor T17 jumps, which may cause the second pole of the seventeenth transistor T17 to generate signal fluctuation, so that the photo signal output terminal Vout generates signal fluctuation, and if the signal of the first selection control terminal SEL1 changes from high level to low level and starts noise reading or signal reading, an erroneous fluctuation signal may be collected, which affects the accuracy of fingerprint identification. Therefore, it is optional that the first period and the second period do not completely overlap. Specifically, the start time of the second period may precede the start time of the first period, so as to eliminate the influence of the gate voltage jump of the seventeenth transistor T17.

In order to realize that the first time period and the second time period are not completely overlapped, for the cascaded shift registers from 1 st to nth, a first selection control end of at least one fingerprint identification unit is electrically connected with the first node of the mth shift register, and a second selection control end of the at least one fingerprint identification unit is electrically connected with the second node of the nth shift register, wherein m and N are integers which are greater than or equal to 1 and less than or equal to N, and m is not equal to N, that is, for the same fingerprint identification unit, the first selection control end is electrically connected with the first node of one shift register, and the second selection control end is electrically connected with the second node of the other shift register.

Further, for cascaded shift registers 1 to N, a first selection control terminal of at least one fingerprint identification unit can be electrically connected with a first node of the m-th shift register, and a second selection control terminal of the at least one fingerprint identification unit is electrically connected with a second node of the m-1 shift register, wherein m is greater than 1. Specifically, referring to fig. 16 and 17, fig. 16 is a schematic top view of another fingerprint identification display panel according to an embodiment of the present invention, fig. 17 is a schematic diagram of two cascaded shift registers in fig. 16 connected to a fingerprint identification unit, and the structure of the shift register is described by taking the shift register shown in fig. 7 as an example. In this embodiment, the first selection control terminal SEL1 of the fingerprint identification unit 120 is electrically connected to the first node EAm of the m-th shift register 110, the second selection control terminal SEL2 of the fingerprint identification unit 120 is electrically connected to the second node EBm-1 of the m-1 th shift register 110, and the timing signal diagram corresponding to the m-th shift register 110 and the m-1 th shift register 110 can refer to fig. 8, where the clock signal terminals of the two shift registers are shared, and therefore, the clock signal terminals shared with the m-1 th shift register are indicated in parentheses of the reference numerals of the clock signal terminals of the m-th shift register in the drawing. The specific working principle of the two shift registers can refer to the description of one shift register corresponding to fig. 8 in the working stage of normal display, and is not described herein again. It can be seen that a first time period corresponding to a low level signal of the first node EAm of the mth shift register 110 and a second time period corresponding to a high level signal of the second node EBm-1 of the m-1 shift register 110 partially overlap but do not completely overlap, and a start time of the second time period precedes a start time of the first time period, so that an influence of a gate voltage jump of the seventeenth transistor T17 in the fingerprint identification unit 120 can be eliminated. In this embodiment, the structure of the shift register is described by taking the structure of the shift register shown in fig. 7 as an example, but in other alternative embodiments of the present invention, the structure of the shift register may be the structure of the shift register shown in fig. 3, 5, or 11, or may be the structure of another qualified shift register, and will not be described in detail here. When the shift register shown in fig. 11 is used, the scan circuit further includes an output module electrically connected to each shift register, which can be referred to fig. 11 specifically and is not described herein again.

Referring to fig. 18, fig. 18 is a schematic top view of another fingerprint identification display panel according to an embodiment of the present invention, where the fingerprint identification display panel includes a display area AA and a non-display area NA surrounding the display area AA, a first scanning circuit 101 and a second scanning circuit 102 are disposed in the non-display area NA, the first scanning circuit 101 and the second scanning circuit 102 both include a plurality of cascaded shift registers 110, each shift register 110 includes a first node EA and a second node EB, and signals of the first node EA and the second node EB in the same shift register 110 have opposite levels; the fingerprint recognition display panel further includes a plurality of fingerprint recognition units 120, each fingerprint recognition unit 120 including a first selection control terminal SEL1 and a second selection control terminal SEL2, the first selection control terminal SEL1 being electrically connected to a first node EA of one shift register 110 of the first scanning circuit 101, the second selection control terminal SEL2 being electrically connected to a second node EB of one shift register 110 of the second scanning circuit 102; alternatively, the first selection control terminal SEL1 is electrically connected to the first node EA of the one shift register 110 of the second scanning circuit 102, and the second selection control terminal SEL2 is electrically connected to the second node EB of the one shift register 110 of the first scanning circuit 101.

In this embodiment, unlike the embodiment shown in fig. 1, the first scanning circuit 101 and the second scanning circuit 102 are separated from each other, and as shown in fig. 18, the first scanning circuit 101 and the second scanning circuit 102 are respectively located in the non-display area NA on two opposite sides of the display area AA, and two control terminals in the fingerprint identification unit 120 are respectively connected to the first node and the second node of the first scanning circuit 101 and the second scanning circuit 102, so that the number of the fingerprint identification driving circuits is also reduced, and the frame of the fingerprint identification display panel can be reduced to a large extent.

Specifically, the cascaded shift registers 110 of the first scan circuit 101 are respectively the 1 st to 2a +1 st shift registers, and the cascaded shift registers 101 of the second scan circuit 102 are respectively the 2 nd to 2a +2 nd shift registers; the input end IN of the jth shift register is connected with the cascade terminal NEXT of the jth-2 shift register, the input end IN of the 1 st shift register is connected with the first start trigger signal terminal STV1, and the input end IN of the 2 nd shift register is connected with the second start trigger signal terminal STV2, wherein a is an integer greater than or equal to 1, and j is an integer greater than 2 and less than or equal to 2a + 2. As in fig. 18, the 1 st shift register, the 2 nd shift register, the 2a +1 th shift register, and the 2a +2 th shift register are exemplarily shown.

The circuit structure of the fingerprint identification unit 120 in this embodiment may adopt the circuit structure of the fingerprint identification unit shown in fig. 13, and similarly, for the same fingerprint identification unit, the duration of the low-level signal of the first node EA electrically connected to the first selection control terminal SEL1 of the fingerprint identification unit 120 is defined as a first time period, the duration of the high-level signal of the second node EB electrically connected to the second selection control terminal SEL2 of the fingerprint identification unit 120 is defined as a second time period, and the first time period and the second time period at least partially overlap. It may be selected that the first time period and the second time period do not completely overlap. Specifically, the start time of the second period may precede the start time of the first period, so as to eliminate the influence of the gate voltage jump of the seventeenth transistor T17.

In order to realize that the first time period and the second time period do not completely overlap, a first selection control terminal SEL1 of at least one fingerprint identification unit 120 may be electrically connected to a first node EA2p +2 of the 2p +2 shift register, and a second selection control terminal SEL2 of the at least one fingerprint identification unit 120 may be electrically connected to a second node EB2p +1 of the 2p +1 shift register, where p is an integer greater than or equal to 0 and less than or equal to a; alternatively, the first selection control terminal SEL1 of at least one fingerprint identification unit 120 is electrically connected to the first node EA2q +1 of the 2q +1 th shift register, and the second selection control terminal SEL2 of the at least one fingerprint identification unit 120 is electrically connected to the second node EB2q of the 2q shift register, where q is an integer greater than or equal to 1 and less than or equal to a.

Specifically, reference may be made to fig. 19 and fig. 20, where fig. 19 is a schematic diagram of fig. 18 in which two shift registers respectively located in the first scanning circuit and the second scanning circuit are connected to a fingerprint identification unit, fig. 20 is a timing signal diagram corresponding to the two shift registers in fig. 19, where clock signal terminals of the two shift registers are shared, so that clock signal terminals corresponding to the shared clock signal terminals of the 2p +1 shift register are marked in parentheses of reference numerals of clock signal terminals of the 2p +2 shift register in the drawing, and the structure of the shift register is described by taking the shift register shown in fig. 7 as an example. In the present embodiment, an example will be described in which "the first selection control terminal SEL1 of the fingerprint recognition unit 120 is electrically connected to the first node EA2p +2 of the 2p +2 th shift register, and the second selection control terminal SEL2 of the fingerprint recognition unit 120 is electrically connected to the second node EB2p +1 of the 2p +1 th shift register". For the specific working principle corresponding to the 2p +1 th shift register and the 2p +2 th shift register, reference may be made to the description of one shift register corresponding to fig. 8 at the working stage of normal display, which is not described herein again. It can be seen that a first time period corresponding to a low level signal of the first node EAm of the 2p +2 shift register and a second time period corresponding to a high level signal of the second node EB2p +1 of the 2p +1 shift register partially overlap but do not completely overlap, and a start time of the second time period precedes a start time of the first time period, so that an influence of a gate voltage transition of the seventeenth transistor T17 in the fingerprint recognition unit 120 can be eliminated.

In this embodiment, the structure of the shift register is described by taking the structure of the shift register shown in fig. 7 as an example, but in other alternative embodiments of the present invention, the structure of the shift register may be the structure of the shift register shown in fig. 3, 5, or 11, or may be the structure of another qualified shift register, and will not be described in detail here. When the shift register shown in fig. 11 is used, the first scan circuit and the second scan circuit further include an output module electrically connected to each shift register, which can be referred to fig. 11 specifically, and details thereof are not repeated here.

It should be noted that, the area for implementing fingerprint identification is a fingerprint identification area, and the fingerprint identification unit in the above embodiment is located in the fingerprint identification area. The fingerprint identification district can overlap with the display area part, can realize the local fingerprint identification function of full-screen display module assembly through the fingerprint identification district. The fingerprint identification district also can overlap completely with the display area, and the fingerprint identification unit is covered with the display area promptly, and finger touch all can trigger the fingerprint identification unit and carry out fingerprint identification in arbitrary position on the screen, realizes full-screen fingerprint identification function, makes fingerprint identification's precision higher more convenient and fast. In addition, in the above embodiments, the display area is further provided with a data line (not shown in the figure), and the gate line and the data line are crossed in an insulating manner to define a plurality of sub-pixels for displaying.

Based on the same inventive concept, an embodiment of the present invention further provides a fingerprint identification display device, fig. 21 is a schematic structural diagram of the fingerprint identification display device provided in the embodiment of the present invention, and referring to fig. 21, the fingerprint identification display device includes the fingerprint identification display panel 200 provided in any of the above embodiments of the present invention, and may further include structures such as a backlight module, which are not shown in fig. 21, and are not described herein again. The light source for fingerprint identification may be disposed on the backlight module, but the present invention is not limited thereto. In this embodiment, the fingerprint identification display device is a mobile phone, and in other optional embodiments of the present invention, the fingerprint identification display device may be any device having display and fingerprint identification functions, such as a tablet computer and a notebook computer.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A fingerprint identification display panel comprising a scanning circuit, wherein the scanning circuit comprises:

a plurality of cascaded shift registers, wherein each shift register comprises a first node and a second node, and the level of signals of the first node and the second node in the same shift register are opposite;

the fingerprint identification display panel further comprises a plurality of fingerprint identification units, each fingerprint identification unit comprises a first selection control end and a second selection control end, the first selection control end is electrically connected with the first node of one of the shift registers, and the second selection control end is electrically connected with the second node of one of the shift registers.

2. The fingerprint identification display panel of claim 1, wherein the cascaded shift registers are respectively shift registers 1 to N, an input terminal of the ith shift register is connected to a cascaded terminal of the i-1 th shift register, and an input terminal of the 1 st shift register is connected to a start trigger signal terminal, where N is an integer greater than or equal to 2, and i is an integer greater than 1 and less than or equal to N.

3. The fingerprint recognition display panel of claim 2,

the shift register also comprises a node control circuit, a reset circuit and an output circuit;

the node control circuit is electrically connected with the reset circuit and the output circuit through the first node, and the node control circuit is electrically connected with the output circuit through the second node;

the node control circuit is used for controlling the level of the signal of the second node to be opposite to that of the signal of the first node according to the signal of a signal input end or the signal of the first node;

the reset circuit is used for providing a signal of a first reference signal end to the first node according to the control of the signal of the first clock signal end;

the output circuit is used for providing a signal of a second clock signal end to the signal output end of the shift register according to the control of the signal of the second node; and is further configured to provide the signal of the second reference signal terminal to the signal output terminal according to the control of the signal of the first node.

4. The fingerprint recognition display panel of claim 3, wherein the node control circuit comprises a first transistor, a second transistor, and a third transistor;

a first pole of the first transistor is connected to the signal input end, a second pole of the first transistor is connected to the second node, and the first transistor is used for selectively transmitting a signal of the signal input end to the second node according to the control of a signal of a third clock signal end;

a gate of the second transistor is connected to the first node, a first pole of the second transistor is connected to the second reference signal terminal, and a second pole of the second transistor is connected to the second node;

a gate of the third transistor is coupled to the first signal input terminal, a first pole of the third transistor is coupled to the second reference signal terminal, and a second pole of the third transistor is coupled to the first node.

5. The fingerprint identification display panel of claim 3 wherein the reset module comprises a fourth transistor;

a gate of the fourth transistor is connected to the first clock signal terminal, a first pole of the fourth transistor is connected to the first reference signal terminal, and a second pole of the fourth transistor is connected to the first node.

6. The fingerprint recognition display panel of claim 3, wherein the output circuit comprises a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor;

a gate of a fifth transistor is connected to the second node, a first pole of the fifth transistor is connected to the second clock signal terminal, and a second pole of the fifth transistor is connected to the signal output terminal;

a gate of a sixth transistor is connected to the first node, a first pole of the sixth transistor is connected to the second reference signal terminal, and a second pole of the sixth transistor is connected to the signal output terminal;

a first plate of the first capacitor is connected to the first node, and a second plate of the first capacitor is connected to the second reference signal terminal;

the first plate of the second capacitor is connected to the second node, and the second plate of the second capacitor is connected to the signal output end.

7. The fingerprint recognition display panel of claim 2,

the shift register also comprises an input module and a latch module;

the input module is electrically connected with the latch module through the first node;

the output end of the latch module is connected to the second node;

the input module is used for generating a scanning signal according to the accessed starting signal;

the latch module is used for generating the starting signal according to the scanning signal and latching the starting signal.

8. The fingerprint recognition display panel of claim 7, wherein the input module comprises a first clock inverter and a first inverter;

the input end of the first clock phase inverter is electrically connected to the signal input end to access the starting signal, the output end of the first clock phase inverter is electrically connected with the latch module through the first node, the input end of the first phase inverter and the second control end of the first clock phase inverter are both connected to the first clock signal end, and the output end of the first phase inverter is connected to the first control end of the first clock phase inverter.

9. The fingerprint recognition display panel of claim 8, wherein the latch module comprises: a second inverter and a second clock inverter;

the input end of the second phase inverter and the output end of the second clock phase inverter are both connected to the first node, the output end of the second phase inverter and the input end of the second clock phase inverter are both connected to the second node, the first control end of the second clock inverter is connected to the first clock signal end, and the second control end of the second clock inverter is connected to the output end of the first phase inverter.

10. The panel of claim 9, wherein the scan circuit further comprises an output module electrically connected to an output of each of the latch modules;

the output module comprises a NAND gate and an inverter module, a first input end of the NAND gate is connected to an output end of the latch module, a second input end of the NAND gate is connected to a second clock signal end, an output end of the NAND gate is connected to an input end of the inverter module, and the inverter module comprises an odd number of inverters which are connected in series.

11. The fingerprint identification display panel of claim 2, wherein for the same fingerprint identification unit, the duration of the low level signal of a first node electrically connected to the first selection control terminal of the fingerprint identification unit is a first time period, the duration of the high level signal of a second node electrically connected to the second selection control terminal of the fingerprint identification unit is a second time period, and the first time period and the second time period at least partially overlap.

12. The fingerprint recognition display panel of claim 11, wherein the first time period and the second time period do not completely overlap.

13. The panel of claim 12, wherein the first selection control terminal of at least one of the fingerprint recognition units is electrically connected to the first node of an m-th shift register, and the second selection control terminal of the at least one of the fingerprint recognition units is electrically connected to the second node of an N-th shift register, where m and N are integers greater than or equal to 1 and less than or equal to N, and m ≠ N.

14. The panel of claim 12, wherein the first selection control terminal of at least one of the fingerprint recognition units is electrically connected to the first node of an m-th shift register, and the second selection control terminal of the at least one of the fingerprint recognition units is electrically connected to the second node of an m-1 th shift register, where m > 1.

15. The fingerprint recognition display panel of claim 1, wherein the fingerprint recognition unit further comprises a third selection control terminal, a photodiode, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, a storage capacitor, a reference voltage signal terminal, a driving voltage signal terminal, and a signal output terminal;

the anode of the photodiode is connected with the reference voltage signal end, and the cathode of the photodiode is connected with a third node; a gate of the fourteenth transistor is connected to the first selection control terminal, a first pole of the fourteenth transistor is connected to the third node, and a second pole of the fourteenth transistor is connected to a fourth node; a gate of the fifteenth transistor is connected to the second selection control terminal, a first pole of the second transistor is connected to the fourth node, and a second pole of the fifteenth transistor is connected to the driving voltage signal terminal; a gate of the sixteenth transistor is connected to the fourth node, a first pole of the sixteenth transistor is connected to a first pole of the seventeenth transistor, and a second pole of the sixteenth transistor is connected to the driving voltage signal terminal; a gate of the seventeenth transistor is connected to the third selection control terminal, and a second pole of the seventeenth transistor is connected to the signal output terminal; the first plate of the storage capacitor is connected to the fourth node, and the second plate of the storage capacitor is connected to the reference voltage signal terminal.

16. A fingerprint identification display panel comprising a first scanning circuit and a second scanning circuit, wherein each of the first scanning circuit and the second scanning circuit comprises:

the fingerprint identification display panel further comprises a plurality of fingerprint identification units, each fingerprint identification unit comprises a first selection control end and a second selection control end, the first selection control end is electrically connected with the first node of one shift register of the first scanning circuit, and the second selection control end is electrically connected with the second node of one shift register of the second scanning circuit; alternatively, the first and second electrodes may be,

the first selection control terminal is electrically connected to the first node of one of the shift registers of the second scanning circuit, and the second selection control terminal is electrically connected to the second node of one of the shift registers of the first scanning circuit.

17. The fingerprint recognition display panel of claim 16, wherein the cascaded plurality of shift registers of the first scanning circuit are 1 st to 2a +1 th shift registers, respectively, and the cascaded plurality of shift registers of the second scanning circuit are 2 nd to 2a +2 th shift registers, respectively; the input end of the jth shift register is connected with the cascade end of the jth-2 shift register, the input end of the 1 st shift register is connected with the first start trigger signal end, and the input end of the 2 nd shift register is connected with the second start trigger signal end, wherein a is an integer larger than or equal to 1, and j is an integer larger than 2 and smaller than or equal to 2a + 2.

18. The fingerprint recognition display panel of claim 17, wherein for the same fingerprint recognition unit, the duration of the low level signal of a first node to which the first selection control terminal of the fingerprint recognition unit is electrically connected is a first time period, and the duration of the high level signal of a second node to which the second selection control terminal of the fingerprint recognition unit is electrically connected is a second time period, and the first time period and the second time period at least partially overlap.

19. The fingerprint identification display panel of claim 18 wherein the first selection control terminal of at least one of the fingerprint identification units is electrically connected to the first node of the 2p +2 th shift register, and the second selection control terminal of the at least one of the fingerprint identification units is electrically connected to the second node of the 2p +1 th shift register, wherein p is an integer greater than or equal to 0 and less than or equal to a; alternatively, the first and second electrodes may be,

the first selection control terminal of at least one of the fingerprint identification units is electrically connected with the first node of the 2q +1 th shift register, and the second selection control terminal of the at least one of the fingerprint identification units is electrically connected with the second node of the 2q shift register, wherein q is an integer greater than or equal to 1 and less than or equal to a.

20. A fingerprint recognition display device comprising the fingerprint recognition display panel according to any one of claims 1 to 19.