CN110908847A - Abnormity recovery method, system, electronic equipment and storage medium - Google Patents
Abnormity recovery method, system, electronic equipment and storage medium Download PDFInfo
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- CN110908847A CN110908847A CN201911157911.4A CN201911157911A CN110908847A CN 110908847 A CN110908847 A CN 110908847A CN 201911157911 A CN201911157911 A CN 201911157911A CN 110908847 A CN110908847 A CN 110908847A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
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Abstract
The application discloses an exception recovery method, which is applied to electronic equipment comprising a first BIOS Flash chip and a second BIOS Flash chip, and comprises the following steps: selecting to a first BIOS Flash chip or a second BIOS Flash chip according to the priority by using the SPI switch; after the electronic equipment normally enters an operating system, judging whether a chip currently selected by the SPI switch is a first BIOS Flash chip or not; if not, executing refreshing operation on the first BIOS Flash chip in the recovery mode, and updating the initialization Engine of the first BIOS Flash chip. The BIOS abnormity detection method and the BIOS abnormity detection device can detect BIOS abnormity, improve abnormal recovery efficiency and improve equipment stability. The application also discloses an abnormality recovery system, a storage medium and an electronic device, which have the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to an exception recovery method and system, an electronic device, and a storage medium.
Background
With the coming of the internet 5G era, internet of things communication is leading the world, and various small and medium-sized devices such as network terminals, external switches and router devices are continuously promoted. Compared with a server, the devices do not need the performance of x86 series CPUs, only need to be added by some low-power-consumption CPUs, can normally enter an OS (operating system) and load related modules to operate, and do not need to be added by a large management system like BMC (baseboard management controller), so that the innovative Engine Innovation Engine is the first choice of the devices, the innovative Engine Innovation Engine only needs to be simply monitored and obtained by a Sensor, the operation of related input and output pins is controlled, and the firmware version can be upgraded in band.
The portable device has low requirement on monitoring management, but has extremely high requirement on the reliability and the stability of the system, requires the normal starting of the dual-mirror BIOS, can perform autonomous switching, and can recover by using the slave-mirror BIOS after the master-mirror BIOS has a problem.
Therefore, how to detect the BIOS abnormality and improve the recovery efficiency of the abnormality, and improve the stability of the device is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide an exception recovery method, an exception recovery system, an electronic device and a storage medium, which can detect BIOS exception, improve exception recovery efficiency and improve device stability.
In order to solve the above technical problem, the present application provides an exception recovery method, which is applied to an electronic device including a first BIOS Flash chip and a second BIOS Flash chip, and the exception recovery method includes:
selecting to the first BIOS Flash chip or the second BIOS Flash chip according to the priority by using the SPI switch so as to start an operating system of the electronic equipment; the priority of the first BIOS Flash chip is higher than that of the second BIOS Flash chip;
after the electronic equipment normally enters an operating system, judging whether a chip currently selected by the SPI switch is the first BIOS Flash chip or not;
if not, setting a management engine running in the SOC chip into a recovery mode by sending an IPMI instruction, and executing a refreshing operation on the first BIOS Flash chip in the recovery mode;
controlling an Innovation Engine Innovation Engine running in the SOC chip to enter a ROM boot extension mode, controlling the SPI switch to select to the first BIOS Flash chip, and updating the Innovation Engine Innovation Engine of the first BIOS Flash chip by using backup firmware in the ROM boot extension mode; the Innovation Engine is an embedded core system based on a PCH chip or an embedded core system based on an SOC chip.
Optionally, the selecting, by using the SPI switch, to the first BIOS Flash chip or the second BIOS Flash chip according to the priority order so as to start the operating system of the electronic device includes:
selecting the first BIOS Flash chip by using the SPI switch chip, starting the electronic equipment by using the first BIOS Flash chip, and executing power-on self-detection operation;
judging whether the power-on self-test operation is abnormal or not;
if so, selecting to the second BIOS Flash chip by using the SPI switch chip, and starting the electronic equipment through the second BIOS Flash chip so as to start an operating system of the electronic equipment;
if not, the operation system of the electronic equipment is judged to be started up.
Optionally, when the power-on self-test operation is performed, the method further includes:
controlling the level output by the target GPIO pin to be switched from high level to low level, and recording the duration of the target GPIO pin continuously outputting the low level;
correspondingly, the step of judging whether the power-on self-test operation is abnormal or not comprises the following steps:
judging whether the duration of the target GPIO pin continuously outputting the low level is greater than the preset duration;
if yes, controlling the electronic equipment to execute restarting operation by using the CPLD, and recording the restarting times;
and when the restarting times is larger than or equal to a preset value, judging that the power-on self-test operation is abnormal.
Optionally, the executing the refresh operation on the first BIOS Flash chip in the recovery mode includes:
and refreshing the BIOS image file stored in the operating system to the first BIOSFlash chip in the recovery mode.
Optionally, the executing the refresh operation on the first BIOS Flash chip in the recovery mode includes:
and refreshing all Flash files of the second BIOS Flash chip to the first BIOS Flash chip in the recovery mode.
Optionally, after refreshing the Innovation Engine, the method further includes:
and restarting the operating system of the electronic equipment by using the refreshed first BIOS Flash chip.
The application also provides an abnormality recovery system, which is applied to electronic equipment comprising a first BIOS Flash chip and a second BIOS Flash chip, and comprises:
the starting module is used for selecting the first BIOS Flash chip or the second BIOS Flash chip according to the priority by utilizing the SPI switch so as to start the operating system of the electronic equipment; the priority of the first BIOS Flash chip is higher than that of the second BIOS Flash chip;
the chip selection determining module is used for judging whether the chip currently selected by the SPI switch is the first BIOS Flash chip or not after the electronic equipment normally enters an operating system;
the chip refreshing module is used for setting a management engine running in the SOC chip into a recovery mode by sending an IPMI instruction when the chip currently selected by the SPI switch is not the first BIOS Flash chip, and executing refreshing operation on the first BIOS Flash chip in the recovery mode;
the firmware updating module is used for controlling an Innovation Engine Innovation Engine running in the SOC chip to enter a ROM boot extension mode, controlling the SPI switch to select the first BIOS Flash chip in a chip mode, and updating the Innovation Engine Innovation Engine of the first BIOS Flash chip by using backup firmware in the ROM boot extension mode; the Innovation Engine is an embedded core system based on a PCH chip or an embedded core system based on an SOC chip.
Optionally, the starting module includes:
the power-on self-detection unit is used for selecting the first BIOS Flash chip by utilizing the SPI switch chip, starting the electronic equipment through the first BIOS Flash chip and executing power-on self-detection operation;
the judging unit is used for judging whether the power-on self-test operation is abnormal or not; if so, selecting to the second BIOS Flash chip by using the SPI switch chip, and starting the electronic equipment through the second BIOS Flash chip so as to start an operating system of the electronic equipment; if not, the operation system of the electronic equipment is judged to be started up.
The application also provides a storage medium, on which a computer program is stored, which when executed implements the steps performed by the above-mentioned anomaly recovery method.
The application also provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the execution of the abnormal recovery method when calling the computer program in the memory.
The application provides an exception recovery method which is applied to electronic equipment comprising a first BIOS Flash chip and a second BIOS Flash chip and comprises the following steps: selecting to the first BIOS Flash chip or the second BIOS Flash chip according to the priority by using the SPI switch so as to start an operating system of the electronic equipment; the priority of the first BIOS Flash chip is higher than that of the second BIOS Flash chip; after the electronic equipment normally enters an operating system, judging whether a chip currently selected by the SPI switch is the first BIOS Flash chip or not; if not, setting a management engine running in the SOC chip into a recovery mode by sending an IPMI instruction, and executing a refreshing operation on the first BIOS Flash chip in the recovery mode; and controlling an Innovation Engine Innovation Engine running in the SOC chip to enter a ROM boot extension mode, controlling the SPI switch to select to the first BIOS Flash chip, and updating the Innovation Engine Innovation Engine of the first BIOS Flash chip by using backup firmware in the ROM boot extension mode.
The electronic equipment comprises a first BIOS Flash chip and a second BIOS Flash chip, and when the electronic equipment is started, the electronic equipment can enter an operating system through the first BIOS Flash chip and the second BIOS Flash chip. The first BIOS Flash chip in this embodiment is a main chip, and this embodiment preferentially enters the operating system through the main chip. After the operating system is entered, if the SPI switch selects the chip currently and the second BIOS Flash chip is used for indicating that the first BIOS Flash chip has a fault. In this embodiment, the management Engine is set to the recovery mode, the refresh operation is performed on the first BIOS Flash chip in the recovery mode, and the firmware of the Innovation Engine is updated to implement the abnormal recovery of the first BIOS Flash chip, so that the electronic device can enter the operating system by using the first BIOS Flash chip. The scheme can detect the BIOS abnormity, improve the abnormal recovery efficiency and improve the stability of equipment. The application also provides an abnormality recovery system, a storage medium and an electronic device, which have the beneficial effects and are not repeated herein.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of an exception recovery method according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an electronic device provided in this embodiment;
FIG. 3 is a flowchart illustrating an IE-based BIOS recovery method according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of an abnormality recovery system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of an exception recovery method according to an embodiment of the present disclosure.
The specific steps may include:
s101: selecting the first BIOS Flash chip or the second BIOS Flash chip according to the priority by using an SPI switch so as to start an operating system of the electronic equipment;
the embodiment can be applied to electronic equipment comprising a first BIOS Flash chip and a second BIOS Flash chip. Referring to fig. 2, fig. 2 is a schematic structural diagram of an electronic device provided in this embodiment, in which each of the first BIOS Flash chip and the second BIOS Flash chip may include a BIOS (Basic Input Output System), an ME (Management Engine/Innovation Engine), and an IE (Innovation Engine). The IE is a BMC (Baseboard Management Controller) monitoring engine, and the IE is an embedded core System of a PCH (Platform Controller Hub) or SOC (System on Chip), and is based on a very small 32-bit kernel library and has some privileges and input/output interfaces of the IE itself. The IE is a simplified BMC monitoring and Management system and only has functions of partial IPMI (Intelligent Platform Management Interface), Redfish, LAN and the like. SPI Serial Peripheral Interface (SPI Interface) Switch in fig. 2, namely SPI Switch, Main FW, namely Main firmware. The SPI switch is connected with a first BIOS Flash chip through a CS0 interface or connected with a second BIOS Flash chip through a CS1 interface.
In this embodiment, the priority of the first BIOS Flash chip is higher than that of the second BIOS Flash chip, that is, when the operating system of the electronic device is started, the SPI switch preferentially selects the first BIOS Flash chip, and the Innovation Engine of the first BIOS Flash chip is run in the SOC chip. When the first BIOS Flash chip is abnormal, the SPI switch can be selected to the second BIOS Flash chip, and the Innovation Engine of the second BIOS Flash chip is operated in the SOC chip. After the SPI switch chip is selected to the first BIOS Flash chip or the second BIOS Flash chip, the operating system can be normally entered after the Power On Self Test (POST) is normal through the BMC.
S102: after the electronic equipment normally enters an operating system, judging whether a chip currently selected by the SPI switch is the first BIOS Flash chip or not; if yes, ending the process, otherwise, entering S103;
the method comprises the steps that on the basis that the electronic equipment normally enters an operating system, whether a chip selected by an SPI switch currently is the first BIOS Flash chip or not is established, if yes, the first BIOS Flash chip is normal, and an Innovation Engine Innovation Engine running in an SOC chip is the Innovation Engine in the first BIOS Flash chip; if not, the first BIOS Flash chip is abnormal, and the Innovation Engine Innovation Engine running in the SOC chip is the Innovation Engine in the second BIOS Flash chip. If the first BIOS Flash chip is normal, the flow of this embodiment may be ended; if the first BIOS Flash chip is abnormal, the abnormal recovery may be performed through the related steps of S103 and S104.
S103: setting a management engine running in an SOC chip into a recovery mode by sending an IPMI instruction, and executing a refreshing operation on the first BIOS Flash chip in the recovery mode;
the method comprises the following steps that on the basis that the first BIOS Flash chip is abnormal, an IPMI instruction is sent to set a management engine running in the SOC chip to be in a recovery mode. And the recovery mode is a recovery mode, and data or a system in the first BIOS Flash chip can be modified in the recovery mode. In the recovery mode, the embodiment may refresh a normal BIOS file to the first BIOS Flash chip. The method can be specifically realized by the following two ways: the first method is as follows: refreshing the BIOS image file stored in the operating system to the first BIOSFlash chip in the recovery mode; the second method comprises the following steps: and refreshing all Flash files of the second BIOS Flash chip to the first BIOS Flash chip in the recovery mode.
S104: and controlling an Innovation Engine Innovation Engine running in the SOC chip to enter a ROM boot extension mode, controlling the SPI switch to select to the first BIOS Flash chip, and updating the Innovation Engine Innovation Engine of the first BIOS Flash chip by using backup firmware in the ROM boot extension mode.
After the first BIOS Flash chip is refreshed, the present embodiment may further control an Innovation Engine running in the SOC chip to enter a ROM boot extension mode. The ROM boot extension mode is a ROM boot extension mode in which firmware update operation can be performed. When the Innovation Engine used in this embodiment is an IE Engine, the ROM Boot Extension mode refers to the IE Boot loader phase uboot. As a possible implementation manner, after the Innovation Engine is refreshed, the operating system of the electronic device may be restarted by using the refreshed first BIOS Flash chip.
In this embodiment, the electronic device includes a first BIOS Flash chip and a second BIOS Flash chip, and the electronic device can enter the operating system through the first BIOS Flash chip and the second BIOS Flash chip when being started. The first BIOS Flash chip in this embodiment is a main chip, and this embodiment preferentially enters the operating system through the main chip. After the operating system is entered, if the SPI switch selects the chip currently and the second BIOS Flash chip is used for indicating that the first BIOS Flash chip has a fault. In this embodiment, the management Engine is set to the recovery mode, the refresh operation is performed on the first BIOS Flash chip in the recovery mode, and the firmware of the Innovation Engine is updated to implement the abnormal recovery of the first BIOS Flash chip, so that the electronic device can enter the operating system by using the first BIOS Flash chip. The scheme can detect the BIOS abnormity, improve the abnormal recovery efficiency and improve the stability of equipment.
As a further introduction to the corresponding embodiment of fig. 1, the operation of S101 starting the operating system of the electronic device may include the following steps:
step 1: selecting the first BIOS Flash chip by using the SPI switch chip, starting the electronic equipment by using the first BIOS Flash chip, and executing power-on self-test operation;
step 2: judging whether the power-on self-test operation is abnormal or not; if yes, entering step 3; if not, entering the step 4;
and step 3: selecting the second BIOS Flash chip by using the SPI switch chip, and starting the electronic equipment by using the second BIOS Flash chip so as to start an operating system of the electronic equipment;
and 4, step 4: and judging that the starting of the operating system of the electronic equipment is finished.
Further, in the process of executing the power-on self-test operation in the step 1, the level output by the target GPIO pin may be controlled to be switched from a high level to a low level, and the duration of the target GPIO pin continuously outputting the low level is recorded; correspondingly, the process of determining whether the power-on self-test operation is abnormal in step 2 may be: judging whether the duration of the target GPIO pin continuously outputting the low level is greater than the preset duration; if yes, controlling the electronic equipment to execute restarting operation by using the CPLD, and recording the restarting times; and when the restarting times is larger than or equal to a preset value, judging that the power-on self-test operation is abnormal.
The flow described in the above embodiment is explained below by an embodiment in practical use. Referring to fig. 3, fig. 3 is a flowchart illustrating an IE-based BIOS recovery method according to an embodiment of the present disclosure.
The embodiment can be applied to the external machine equipment of the Switch, the external machine equipment of the Switch is based on an autonomous switching system of double BIOS flashes, two flashes of Primary BIOS and Golden BIOS exist, autonomous switching is carried out through SPI Switch, and each Flash of the BIOS is divided into a BIOS partition, an ME partition and an IE partition; the system is started from a Primary BIOS by default, the GPIO pin is pulled down and pulled up according to the starting running condition, the CPLD judges whether the level value of the corresponding GPIO pin meets the normal requirement or not within the specified time, so that the system is restarted, and the chip selection signal is operated to be switched to a Golden BIOS to be normally started to an OS; the method comprises the steps that a related script is only run once under an OS (operating system), whether the BIOS runs is judged, if the BIOS runs, a related IPMI command is sent to an IE (Internet protocol interface) to set an ME (management entity) mode, a Primary BIOS is refreshed, the IE enters the RBE mode, a GPIO (general purpose input/output) pin is operated to inform a CPLD (complex programmable logic device) to switch a chip selection signal, and the GPIO pin is pulled up; IE will read backup IE FW, update the main IE, after restarting next time, BIOS will switch to Primary BIOS to start.
In the embodiment, the Dual BIOS is divided into a Primary BIOS and a Golden BIOS, the autonomous switching is carried out through an SPISwitch, the BIOS is started as the Primary BIOS by default, when the pin of the GPIO1 is set high in the starting process of the system, and when POST data is finished, the pin of the GPIO1 is pulled low; IE initializes GPIO2 pin high by default each time the system is started.
When the system is started, the CPLD starts a timer, judges whether the GPIO1 pin is always high within 1 minute, and if not, the CPLD is normally started; if yes, starting the system to be abnormal, then repeatedly restarting the CPLD control system for 10 times, or if the CPLD control system is abnormal, switching the Switch chip to the Golden BIOS, then restarting the system, and pulling down the pin of # BF72(GPIO 38).
After switching to Golden BIOS, normally entering an operating system OS, running a related script (the script runs once at each start-up), judging which BIOS is in use in the script, and once finding that # BF72(GPIO38) is low, sending a related IPMI OEM command to IE to inform the IE to carry out BIOS refreshing operation.
After receiving an IPMI instruction of an OS, the IPMI instruction is sent to an ME, the ME is set to be in a Recovery mode, and meanwhile, the IE enters an RBE mode; IE reads the whole Flash file from Golden Flash in RBE mode and stores it, then pulls down GPIO2 pin to inform CPLD (Complex Programmable Logic Device) to switch chip selection signal to Primary BIOS Flash, pulls up # BF72(GPIO38) pin to inform OS and IE, finally IE refreshes the whole Primary Flash. Once the refresh is complete, the IE will pull high the GPIO2 pin.
The autonomous switching system using the double-BIOS Flash has two flashes, namely Primary BIOS and Golden BIOS, and after the Primary mirror image BIOS has a problem, the system can be recovered by using the secondary mirror image BIOS.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an abnormality recovery system according to an embodiment of the present disclosure, where the embodiment is applied to an electronic device including a first BIOS Flash chip and a second BIOS Flash chip, and the abnormality recovery system includes:
the starting module 100 is configured to select the first BIOS Flash chip or the second BIOS Flash chip according to the priority by using the SPI switch, so as to start an operating system of the electronic device; the priority of the first BIOS Flash chip is higher than that of the second BIOS Flash chip;
the chip selection determining module 200 is configured to determine whether a chip currently selected by the SPI switch is the first BIOS Flash chip after the electronic device normally enters an operating system;
the chip refreshing module 300 is configured to set a management engine running in the SOC chip to a recovery mode by sending an IPMI instruction when the currently selected chip of the SPI switch is not the first BIOS Flash chip, and perform a refreshing operation on the first BIOS Flash chip in the recovery mode;
and the firmware updating module 400 is configured to control the Innovation Engine running in the SOC chip to enter a ROM boot extension mode, control the SPI switch to select the first BIOS Flash chip, and update the Innovation Engine of the first BIOS Flash chip with backup firmware in the ROM boot extension mode.
In this embodiment, the electronic device includes a first BIOS Flash chip and a second BIOS Flash chip, and the electronic device can enter the operating system through the first BIOS Flash chip and the second BIOS Flash chip when being started. The first BIOS Flash chip in this embodiment is a main chip, and this embodiment preferentially enters the operating system through the main chip. After the operating system is entered, if the SPI switch selects the chip currently and the second BIOS Flash chip is used for indicating that the first BIOS Flash chip has a fault. In this embodiment, the management Engine is set to the recovery mode, the refresh operation is performed on the first BIOS Flash chip in the recovery mode, and the firmware of the Innovation Engine is updated to implement the abnormal recovery of the first BIOS Flash chip, so that the electronic device can enter the operating system by using the first BIOS Flash chip. The scheme can detect the BIOS abnormity, improve the abnormal recovery efficiency and improve the stability of equipment.
Further, the Innovation Engine is an embedded core system based on a PCH chip or an embedded core system based on an SOC chip.
Further, the starting module 100 includes:
the power-on self-detection unit is used for selecting the first BIOS Flash chip by utilizing the SPI switch chip, starting the electronic equipment through the first BIOS Flash chip and executing power-on self-detection operation;
the judging unit is used for judging whether the power-on self-test operation is abnormal or not; if so, selecting to the second BIOS Flash chip by using the SPI switch chip, and starting the electronic equipment through the second BIOS Flash chip so as to start an operating system of the electronic equipment; if not, the operation system of the electronic equipment is judged to be started up.
Further, the method also comprises the following steps:
the time length recording module is used for controlling the level output by the target GPIO pin to be switched from a high level to a low level and recording the time length of the target GPIO pin continuously outputting the low level when the power-on self-test operation is executed;
correspondingly, the judging unit is used for judging whether the duration of the low level continuously output by the target GPIO pin is greater than the preset duration; if yes, controlling the electronic equipment to execute restarting operation by using the CPLD, and recording the restarting times; and the power-on self-test operation module is also used for judging that the power-on self-test operation is abnormal when the restarting times is more than or equal to a preset value.
Further, the chip refresh module 300 is specifically a module for refreshing the BIOS image file stored in the operating system to the first BIOS Flash chip in the recovery mode.
Further, the chip refresh module 300 is specifically a module for refreshing all Flash files of the second BIOS Flash chip to the first BIOS Flash chip in the recovery mode.
Further, the method also comprises the following steps:
and the restarting module is used for restarting the operating system of the electronic equipment by utilizing the refreshed first BIOS Flash chip after refreshing the Innovation Engine Innovation Engine.
Since the embodiment of the system part corresponds to the embodiment of the method part, the embodiment of the system part is described with reference to the embodiment of the method part, and is not repeated here.
The present application also provides a storage medium having a computer program stored thereon, which when executed, may implement the steps provided by the above-described embodiments. The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The application further provides an electronic device, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided by the foregoing embodiments when calling the computer program in the memory. Of course, the electronic device may also include various network interfaces, power supplies, and the like.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. An exception recovery method is applied to an electronic device comprising a first BIOS Flash chip and a second BIOS Flash chip, and comprises the following steps:
selecting to the first BIOS Flash chip or the second BIOS Flash chip according to the priority by using the SPI switch so as to start an operating system of the electronic equipment; the priority of the first BIOS Flash chip is higher than that of the second BIOS Flash chip;
after the electronic equipment normally enters an operating system, judging whether a chip currently selected by the SPI switch is the first BIOS Flash chip or not;
if not, setting a management engine running in the SOC chip into a recovery mode by sending an IPMI instruction, and executing a refreshing operation on the first BIOS Flash chip in the recovery mode;
controlling an Innovation Engine Innovation Engine running in the SOC chip to enter a ROM boot extension mode, controlling the SPI switch to select to the first BIOS Flash chip, and updating the Innovation Engine Innovation Engine of the first BIOS Flash chip by using backup firmware in the ROM boot extension mode;
the Innovation Engine Innovation Engine is an embedded core system based on a PCH chip or an embedded core system based on an SOC chip.
2. The method for recovering from the abnormality according to claim 1, wherein the using the SPI switch to select the first BIOS Flash chip or the second BIOS Flash chip according to the priority order so as to start an operating system of the electronic device includes:
selecting the first BIOS Flash chip by using the SPI switch chip, starting the electronic equipment by using the first BIOS Flash chip, and executing power-on self-detection operation;
judging whether the power-on self-test operation is abnormal or not;
if so, selecting to the second BIOS Flash chip by using the SPI switch chip, and starting the electronic equipment through the second BIOS Flash chip so as to start an operating system of the electronic equipment;
if not, the operation system of the electronic equipment is judged to be started up.
3. The method for recovering from an abnormality according to claim 2, when performing a power-on self-test operation, further comprising:
controlling the level output by the target GPIO pin to be switched from high level to low level, and recording the duration of the target GPIO pin continuously outputting the low level;
correspondingly, the step of judging whether the power-on self-test operation is abnormal or not comprises the following steps:
judging whether the duration of the target GPIO pin continuously outputting the low level is greater than the preset duration;
if yes, controlling the electronic equipment to execute restarting operation by using the CPLD, and recording the restarting times;
and when the restarting times is larger than or equal to a preset value, judging that the power-on self-test operation is abnormal.
4. The method of claim 1, wherein performing a refresh operation on the first bios flash chip in the recovery mode comprises:
and refreshing the BIOS image file stored in the operating system to the first BIOSFlash chip in the recovery mode.
5. The method of claim 1, wherein performing a refresh operation on the first bios flash chip in the recovery mode comprises:
and refreshing all Flash files of the second BIOS Flash chip to the first BIOS Flash chip in the recovery mode.
6. The exception recovery method according to any one of claims 1 to 5, further comprising, after refreshing said Innovation Engine:
and restarting the operating system of the electronic equipment by using the refreshed first BIOS Flash chip.
7. An abnormality recovery system, applied to an electronic device including a first BIOS Flash chip and a second BIOS Flash chip, comprising:
the starting module is used for selecting the first BIOS Flash chip or the second BIOS Flash chip according to the priority by utilizing the SPI switch so as to start the operating system of the electronic equipment; the priority of the first BIOS Flash chip is higher than that of the second BIOS Flash chip;
the chip selection determining module is used for judging whether the chip currently selected by the SPI switch is the first BIOS Flash chip or not after the electronic equipment normally enters an operating system;
the chip refreshing module is used for setting a management engine running in the SOC chip into a recovery mode by sending an IPMI instruction when the chip currently selected by the SPI switch is not the first BIOS Flash chip, and executing refreshing operation on the first BIOS Flash chip in the recovery mode;
the firmware updating module is used for controlling an Innovation Engine Innovation Engine running in the SOC chip to enter a ROM boot extension mode, controlling the SPI switch to select the first BIOS Flash chip in a chip mode, and updating the Innovation Engine Innovation Engine of the first BIOS Flash chip by using backup firmware in the ROM boot extension mode;
the Innovation Engine Innovation Engine is an embedded core system based on a PCH chip or an embedded core system based on an SOC chip.
8. The system for recovering from an abnormality according to claim 7, wherein said starting module includes:
the power-on self-detection unit is used for selecting the first BIOS Flash chip by utilizing the SPI switch chip, starting the electronic equipment through the first BIOS Flash chip and executing power-on self-detection operation;
the judging unit is used for judging whether the power-on self-test operation is abnormal or not; if so, selecting to the second BIOS Flash chip by using the SPI switch chip, and starting the electronic equipment through the second BIOS Flash chip so as to start an operating system of the electronic equipment; if not, the operation system of the electronic equipment is judged to be started up.
9. An electronic device comprising a memory in which a computer program is stored and a processor which, when calling the computer program in the memory, implements the steps of the method for recovering an exception as claimed in any one of claims 1 to 7.
10. A storage medium having stored thereon computer-executable instructions which, when loaded and executed by a processor, carry out the steps of the method of recovering from an abnormality as set forth in any one of claims 1 to 7.
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