CN110908593B - Storage space erasing method and device, storage equipment and storage medium - Google Patents
Storage space erasing method and device, storage equipment and storage medium Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004590 computer program Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 7
- 238000007667 floating Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses a storage space erasing method, a storage space erasing device, storage equipment and a storage medium. The method comprises the following steps: receiving an erase command, wherein the erase command comprises an erase address; according to the erasing address, obtaining the address of a target storage space stored in the register, wherein the number of the target storage spaces is two or more; and erasing the data in the target storage space. The invention erases the data in the plurality of target storage spaces by storing the addresses of the plurality of target storage spaces to be erased through the register, thereby realizing the effect of erasing the data in the plurality of storage spaces at one time and improving the erasing efficiency.
Description
Technical Field
Embodiments of the present invention relate to data processing technologies, and in particular, to a method and apparatus for erasing a storage space, a storage device, and a storage medium.
Background
Nand flash memory is a nonvolatile memory, which stores data by performing read-write erasing operation on a memory unit, has the advantages of high writing speed, large storage capacity and the like, is widely used in electronic products, and along with the massive use of flash memory, the performance requirements of the flash memory are continuously improved.
In the conventional Nand flash memory, when each memory block (block) in the memory is erased, only one block is erased at a time, so that the erase efficiency of the block is not high.
Disclosure of Invention
The invention provides a storage space erasing method, a storage space erasing device, storage equipment and a storage medium, so as to realize the increase of the erasing efficiency of a block.
In a first aspect, an embodiment of the present invention provides a method for erasing a storage space, including:
receiving an erase command, wherein the erase command comprises an erase address;
according to the erasing address, obtaining the address of a target storage space stored in the register, wherein the number of the target storage spaces is two or more;
and erasing the data in the target storage space.
Optionally, before the obtaining the address of the target storage space stored in the register, the method further includes:
receiving an input selection instruction;
selecting a space to be erased from the storage space of the memory as the target storage space according to the selection instruction; taking the address of the space to be erased as the address of the target storage space;
and storing the address of the target storage space into a register.
Optionally, the obtaining, according to the erase address, an address of a target storage space stored in the register includes:
judging whether the erasing address is the address of the register;
and when the erasing address is the address of the register, acquiring the address of the target storage space stored in the register.
Optionally, the storage space is a block.
In a second aspect, an embodiment of the present invention further provides a storage space erasing apparatus, including:
the first receiving module is used for receiving an erasing instruction, wherein the erasing instruction comprises an erasing address;
the acquisition module is used for acquiring the addresses of the target storage spaces stored in the register according to the erasing addresses, wherein the number of the target storage spaces is two or more;
and the erasing module is used for erasing the data in the target storage space.
Optionally, the apparatus further includes:
the second receiving module is used for receiving an input selection instruction;
the selecting module is used for selecting a space to be erased from the storage space of the memory as the target storage space according to the selecting instruction; taking the address of the space to be erased as the address of the target storage space;
and the storing module is used for storing the address of the target storage space into a register.
Optionally, the acquiring module includes:
a judging sub-module for judging whether the erasing address is the address of the register;
and the acquisition sub-module is used for acquiring the address of the target storage space stored in the register when the erasure address is the address of the register.
Optionally, the storage space is a block.
In a third aspect, an embodiment of the present invention further provides a storage device, including: a memory, a controller, an input device, and a register;
the input port of the input device is used for receiving an erasing instruction input by a user; the output interface of the input device is connected with the input port of the controller, and the output port of the controller is respectively connected with the input port of the memory and the input port of the register;
the register stores addresses of target storage spaces, and the number of the target storage spaces is two or more; and the controller erases the data in the target storage space corresponding to the address in the register according to the erasing instruction received by the input device.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, wherein the program, when executed by a processor, implements a storage space erasing method according to any one of the first aspects.
The invention erases the data in the plurality of target storage spaces by storing the addresses of the plurality of target storage spaces to be erased through the register, thereby realizing the effect of erasing the data in the plurality of storage spaces at one time and improving the erasing efficiency.
Drawings
FIG. 1 is a flowchart of a method for erasing a memory space according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory and registers in accordance with a first embodiment of the invention;
FIG. 3 is a flowchart of a method for erasing a memory space according to a first embodiment of the present invention;
FIG. 4 is a flowchart of a method for erasing a memory space according to a first embodiment of the present invention;
FIG. 5 is a flowchart of a method for erasing a memory space according to a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a memory space erasing device according to a third embodiment of the present invention;
FIG. 7 is a schematic diagram of a memory space erasing device according to a third embodiment of the present invention;
FIG. 8 is a schematic diagram of a memory space erasing device according to a third embodiment of the present invention;
fig. 9 is a schematic structural diagram of a memory device according to a fourth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a flowchart of a method for erasing a memory space according to an embodiment of the present invention, where the method may be executed by a memory space erasing device, and specifically includes the following steps:
step 101, receiving an erasing instruction.
Here, the erase instruction includes an erase address. The erase command may be triggered by a programming code entered by a user.
The erase address can be obtained in two ways: optionally, directly acquiring the erasing address; optionally, acquiring an erasure identifier; and acquiring an erasure address according to the erasure identifier.
The present embodiment provides two data erasure modes. Optionally, erasing the data in a single storage space; optionally, the data of multiple storage spaces are erased at the same time, wherein the multiple storage spaces can be either continuous space or discontinuous space. Which data erasure mode is used is dependent on the erasure address.
Step 102, according to the erasing address, the address of the target storage space stored in the register is obtained.
The number of target storage spaces is two or more. As shown in fig. 2, registers may store addresses of target memory spaces (e.g., block1, block5, and block 7) in a stack.
Step 103, erasing the data in the target storage space.
Taking Nand flash memory as an example, a floating gate is arranged between a gate and a silicon substrate, the floating gate is formed by sandwiching silicon dioxide material by nitride, and the internal memory structure comprises a metal-oxide-semiconductor-field effect transistor, and the field effect transistor comprises a source electrode, a drain electrode and a gate electrode. The principle of writing data into the memory is as follows: the control gate voltage is used to inject electrons in the P-well into the floating gate to achieve data storage. Therefore, erasing the data in the target memory space is achieved by erasing electrons of the floating gate.
The invention erases the data in the plurality of target storage spaces by storing the addresses of the plurality of target storage spaces to be erased through the register, thereby realizing the effect of erasing the data in the plurality of storage spaces at one time and improving the erasing efficiency.
Based on the above technical solution, as shown in fig. 3, before step 102, the method further includes:
step 104, receiving an input selection instruction.
Step 105, selecting a space to be erased from the storage space of the memory as a target storage space according to the selection instruction; and taking the address of the space to be erased as the address of the target storage space.
The space to be erased is a memory space in a non-space state, i.e., a memory space in which data has been written and is not erased.
And 106, storing the address of the target storage space into a register.
As shown in fig. 2, three memory spaces of block1, block5 and block7 are selected from the memory, addresses of the three memory spaces are acquired, and the addresses are stored in a register in a stack manner.
Further, the embodiment further includes:
receiving an input deleting instruction, wherein the deleting instruction carries an address of a first storage space;
and deleting the address of the first storage space from the memory according to the deleting instruction.
Based on the above technical solution, as shown in fig. 4, step 102 may include:
step 1021, determine if the erase address is the address of the register.
In this embodiment, the erase address may be an address of a register or an address of a memory space.
Step 1022, when the erasure address is the address of the register, the address of the target storage space in the register is obtained.
Based on the technical scheme, the storage space is a block.
The preferred register of this embodiment is a FIFO register.
Example two
Fig. 5 is a flowchart of a method for erasing a memory space according to a second embodiment of the present invention, where the method may be performed by a memory space erasing device, and the device is applied to a memory device, and the method specifically includes the following steps:
step 201, receiving an input selection instruction.
Step 202, selecting a block to be erased from the blocks of the memory as a target block according to a selection instruction; and taking the address of the block to be erased as the address of the target block.
Step 203, receiving an erase command, where the erase command carries an erase address.
Step 204, determine whether the erase address is an address of a register. If yes, go to step 205; if not, step 207 is performed.
Step 205, obtain the address of the target block in the register.
And 206, according to the address of the target block, erasing the data in the target block.
Step 207, erasing the data of the block corresponding to the erase address according to the erase address.
The memory space erasing device provided by the embodiment of the invention can execute the memory space erasing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the executing method.
Example III
Fig. 6 is a schematic structural diagram of a memory space erasing device according to a third embodiment of the present invention, which specifically includes the following modules:
a first receiving module 301, configured to receive an erase command, where the erase command includes an erase address;
an obtaining module 302, configured to obtain, according to the erase address, an address of a target storage space stored in the register, where the number of the target storage spaces is two or more;
and the erasing module 303 is used for erasing the data in the target storage space.
The invention erases the data in the plurality of target storage spaces by storing the addresses of the plurality of target storage spaces to be erased through the register, thereby realizing the effect of erasing the data in the plurality of storage spaces at one time and improving the erasing efficiency.
Optionally, as shown in fig. 7, the apparatus further includes:
a second receiving module 304, configured to receive an input selection instruction;
a selecting module 305, configured to select, according to the selection instruction, a space to be erased from the storage spaces of the memory as the target storage space; taking the address of the space to be erased as the address of the target storage space;
a storing module 306, configured to store the address of the target storage space into a register.
Optionally, as shown in fig. 8, the obtaining module 302 includes:
a judging submodule 3021 for judging whether the erase address is an address of the register;
and an acquisition submodule 3022 for acquiring the address of the target storage space stored in the register when the erase address is the address of the register.
Optionally, the storage space is a block.
Example IV
Fig. 9 is a schematic structural diagram of a storage device according to a fourth embodiment of the present invention, and as shown in fig. 9, the storage device includes a controller 70, a memory 71, an input device 72, and a register 73; the number of controllers 70 in the storage device may be one or more, one controller 70 being taken as an example in fig. 9; the controller 70, memory 71, input means 72 and registers 73 in the storage device may be connected by a bus or other means, in fig. 9 by way of example.
Specifically, the input port of the input device 72 is used for receiving an erase command input by a user; an output interface of the input device 72 is connected to an input port of the controller 70, and an output port of the controller 70 is connected to an input port of the memory 71 and an input port of the register 73, respectively.
The memory 71 is a computer readable storage medium, and may be used to store a software program, a computer executable program, and modules, such as program instructions/modules (e.g., the first receiving module 301, the acquiring module 302, and the erasing module 303 in the memory space erasing device) corresponding to the memory space erasing method in the embodiment of the present invention. The controller 70 performs various functional applications of the storage device and data processing, i.e., implements the above-described storage space erasing method, by running software programs, instructions, and modules stored in the memory 71.
Specifically, the controller 70 erases the data in the target storage space corresponding to the address in the register 37 according to the erase command received by the input device 72. Here, the target storage space is a space of the memory 71.
The memory 71 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functions; the storage data area may store data created according to the use of the terminal, etc. In addition, memory 71 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some examples, memory 71 may further include memory remotely located relative to controller 70, which may be connected to the storage device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 72 is operable to receive an input erase command. The register 73 is used to store the addresses of the target storage spaces, the number of which is two or more.
Further, the register 73 is a FIFO register.
Example five
A fifth embodiment of the present invention also provides a storage medium containing computer-executable instructions, which when executed by a computer controller, are for performing a storage space erasing method, the method comprising:
receiving an erase command, wherein the erase command comprises an erase address;
according to the erasing address, obtaining the address of a target storage space stored in the register, wherein the number of the target storage spaces is two or more;
and erasing the data in the target storage space.
Of course, the storage medium containing the computer executable instructions provided in the embodiments of the present invention is not limited to the above-described method operations, and may also perform the related operations in the storage space erasing method provided in any embodiment of the present invention.
From the above description of embodiments, it will be clear to a person skilled in the art that the present invention may be implemented by means of software and necessary general purpose hardware, but of course also by means of hardware, although in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, etc., and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments of the present invention.
It should be noted that, in the above-mentioned embodiments of the search apparatus, each unit and module included are only divided according to the functional logic, but not limited to the above-mentioned division, as long as the corresponding functions can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (8)
1. A method of erasing a memory space, comprising:
receiving an erase instruction, wherein the erase instruction comprises an erase address;
according to the erasing address, obtaining the address of a target storage space stored in a register, wherein the number of the target storage space is two or more;
the step of obtaining the address of the target storage space stored in the register according to the erasing address comprises the following steps:
judging whether the erasing address is the address of the register;
when the erasure address is the address of the register, acquiring the address of the target storage space stored in the register; the address of the target storage space is stored in a register in a stack mode;
and simultaneously erasing the data in a plurality of target storage spaces.
2. The method of claim 1, wherein prior to the retrieving the address of the target memory space stored in the register, the method further comprises:
receiving an input selection instruction;
selecting a space to be erased from the storage space of the memory as the target storage space according to the selection instruction; taking the address of the space to be erased as the address of the target storage space;
and storing the address of the target storage space into a register.
3. The method of claim 1, wherein the memory space is a memory block.
4. A memory space erasing apparatus, comprising:
the first receiving module is used for receiving an erasing instruction, wherein the erasing instruction comprises an erasing address;
the acquisition module is used for acquiring the addresses of the target storage spaces stored in the register according to the erasing addresses, wherein the number of the target storage spaces is two or more;
the acquisition module comprises:
a judging sub-module for judging whether the erasing address is the address of the register;
an obtaining sub-module, configured to obtain, when the erase address is an address of the register, an address of the target storage space stored in the register; the address of the target storage space is stored in a register in a stack mode;
and the erasing module is used for simultaneously erasing the data in a plurality of target storage spaces.
5. The apparatus of claim 4, wherein the apparatus further comprises:
the second receiving module is used for receiving an input selection instruction;
the selecting module is used for selecting a space to be erased from the storage space of the memory as the target storage space according to the selecting instruction; taking the address of the space to be erased as the address of the target storage space;
and the storing module is used for storing the address of the target storage space into a register.
6. The apparatus of claim 4, wherein the memory space is a memory block.
7. A memory device, comprising: a memory, a controller, an input device, and a register;
the input port of the input device is used for receiving an erasing instruction input by a user; the output interface of the input device is connected with the input port of the controller, and the output port of the controller is respectively connected with the input port of the memory and the input port of the register;
the register stores addresses of target storage spaces, and the number of the target storage spaces is two or more; the controller simultaneously erases the data of a plurality of target storage spaces corresponding to the addresses in the register according to the erasing instruction received by the input device;
the controller simultaneously erases the data of a plurality of target storage spaces corresponding to the addresses in the register according to the erasing instruction received by the input device, and the method comprises the following steps:
the erase instruction includes an erase address;
the controller judges whether the erasure address is an address of the register;
when the erasure address is the address of the register, the controller acquires the address of the target storage space stored in the register; the address of the target storage space is stored in a register in a stack mode;
and the controller simultaneously erases the data of a plurality of target storage spaces corresponding to the addresses in the register.
8. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements a memory space erasing method as claimed in any one of claims 1-3.
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