CN110895501B - Serial port switching method and system thereof - Google Patents

Serial port switching method and system thereof Download PDF

Info

Publication number
CN110895501B
CN110895501B CN201910496342.XA CN201910496342A CN110895501B CN 110895501 B CN110895501 B CN 110895501B CN 201910496342 A CN201910496342 A CN 201910496342A CN 110895501 B CN110895501 B CN 110895501B
Authority
CN
China
Prior art keywords
identification information
target identification
target
serial port
output mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910496342.XA
Other languages
Chinese (zh)
Other versions
CN110895501A (en
Inventor
黄林翔宇
郑熔
郭煜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yanxiang Smart Iot Technology Co ltd
Original Assignee
Yanxiang Smart Iot Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yanxiang Smart Iot Technology Co ltd filed Critical Yanxiang Smart Iot Technology Co ltd
Priority to CN201910496342.XA priority Critical patent/CN110895501B/en
Publication of CN110895501A publication Critical patent/CN110895501A/en
Application granted granted Critical
Publication of CN110895501B publication Critical patent/CN110895501B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/18Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002Serial port, e.g. RS232C

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention provides a serial port switching method and a serial port switching system. The method comprises the following steps: the system control device acquires a chip selection instruction of a serial port, wherein the chip selection instruction comprises: first target identification information of the target output channel and second target identification information of the target output mode; the system control device determines a target output channel according to the first target identification information; the system control device switches the output channel executed by the serial port to a target output channel; the system control device sends the second target identification information to the transceiver chip; the transceiver chip determines a target output mode according to the second target identification information; the transceiver chip switches the output mode of the serial port execution to the target output mode. The invention can flexibly switch the output channel and the output mode of the serial port, can switch the output channel and the output mode of the serial port through software under the conditions of not changing external connection and not opening a case, and simultaneously uses a system control device for programming, and has modularized operation and high portability.

Description

Serial port switching method and system thereof
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a serial port switching method and a system thereof.
Background
Serial communication is applied to various production, living and industrial environments in a large number, common serial communication modes include RS232, RS422 and RS485, various serial communication modes are commonly used, and an output channel and an output mode of each serial port are fixed under normal conditions. The manufacturer sets the output channels and the output modes of each serial port when designing the product according to the actual demands of customers, namely, one serial port corresponds to one serial port output channel, and one serial port output channel corresponds to one serial port output mode.
Therefore, the current serial port switching mode is not flexible enough. On one hand, the output channels of the serial ports are limited by hardware connection, and when a certain serial port has hardware faults, a new output channel can be selected only by changing the external serial port connection; on the other hand, when the user has other serial port mode demands, the serial port communication mode needs to be switched through the jumper cap, however, when the serial port communication mode needs to be switched, the case needs to be opened, the jumper cap is replaced, the switching process is complex, and the environment applicability and the flexibility are poor in use.
Disclosure of Invention
The serial port switching method and the serial port switching system can flexibly switch the output channel and the output mode of the serial port, can switch the output channel and the output mode of the serial port through software under the conditions of not changing external connection and not opening a case, and simultaneously uses a system control device for programming, and has high portability due to modularized operation.
In a first aspect, the present invention provides a serial port switching method, including:
the system control device obtains a chip selection instruction of the serial port, wherein the chip selection instruction comprises the following steps: first target identification information of the target output channel and second target identification information of the target output mode;
The system control device determines a target output channel according to the first target identification information;
The system control device switches the output channel executed by the serial port to a target output channel;
the system control device sends the second target identification information to a transceiver chip;
The transceiver chip determines a target output mode according to the second target identification information;
The transceiver chip switches the output mode executed by the serial port to a target output mode.
Optionally, the step of sending the second target identification information to the transceiver chip by the system control device includes: the system control device converts the second target identification information into new second target identification information and then sends the new second target identification information to the transceiver chip;
the step of determining a target output mode by the transceiver chip according to the second target identification information includes:
and the transceiver chip determines a target output mode according to the new second target identification information.
Optionally, the step of determining, by the system control device, a target output channel according to the first target identification information includes:
The system control device inquires an output channel corresponding to the first target identification information according to the first target identification information and a corresponding table of the target identification information and the output channel of the output channel;
The system control device takes the output channel obtained by inquiry as a target output channel.
Optionally, the step of determining, by the transceiver chip, a target output mode according to the second target identification information includes:
the transceiver chip inquires an output mode corresponding to the second target identification information according to the second target identification information and a corresponding table of the target identification information and the output mode of the output mode;
the transceiver chip takes the output mode obtained by query as a target output mode.
Optionally, the step of acquiring the chip selection instruction of the serial port by the system control device includes:
The system control device obtains a chip selection instruction of the serial port which is changed by a user through the BIOS from the BIOS ROM.
In a second aspect, the present invention further provides a serial port switching system, including:
The system control device is configured to acquire a chip selection instruction of the serial port, wherein the chip selection instruction comprises: first target identification information of the target output channel and second target identification information of the target output mode; determining a target output channel according to the first target identification information; switching the output channel executed by the serial port to a target output channel; transmitting the second target identification information to a transceiver chip;
A transceiver chip configured to determine a target output mode based on the second target identification information; and switching the output mode executed by the serial port to a target output mode.
Optionally, the system control device is further configured to convert the second target identification information into new second target identification information and send the new second target identification information to the transceiver chip;
The transceiver chip is further configured to determine a target output mode based on the new second target identification information.
Optionally, the system control device is further configured to query the output channel corresponding to the first target identification information according to the first target identification information and a corresponding table of the target identification information of the output channel and the output channel; and taking the output channel obtained by query as a target output channel.
Optionally, the transceiver chip is further configured to query an output mode corresponding to the second target identification information according to the second target identification information and a table of target identification information and output modes of the output mode; and taking the output mode obtained by query as a target output mode.
Optionally, the system control device is further configured to obtain a chip selection instruction of the serial port modified by the user through the BIOS from the BIOS ROM.
The serial port switching method and the serial port switching system provided by the embodiment of the invention can flexibly switch the output channel and the output mode of the serial port, can switch the output channel and the output mode of the serial port through software under the conditions of not changing external connection and not opening a case, and simultaneously uses a system control device for programming, and has the advantages of modularized operation and high portability.
Drawings
FIG. 1 is a schematic flow chart of a serial port switching method according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of a serial port switching method according to an embodiment of the present application;
fig. 3 is a schematic diagram of connection relation of a serial port switching system according to an embodiment of the present application;
fig. 4 is a schematic diagram of connection relation of a serial port switching system according to an embodiment of the present application;
Fig. 5 is a schematic diagram of a connection relationship between a serial port real interface and an output channel defined in a serial port according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
First, terms related to the present invention will be explained.
RS232: the EIA-RS-232C standard (232, RS232 for short) is a serial data communication interface standard formulated by the American society EIA (Electronic Industry Association) for electronic industry, and RS-232 is defined as a single-ended standard for increasing communication distance in low-rate serial communication, and adopts an unbalanced transmission mode, namely single-ended communication.
RS422: RS-422 is a single-machine transmission, multi-machine reception, unidirectional, balanced transmission specification, named TIA/EIA-422-a standard.
RS485: in order to expand the application range, the EIA sets an RS-485 standard based on RS-422 in 1983, increases the multipoint and bidirectional communication capability, namely, allows a plurality of transmitters to be connected to the same bus, increases the driving capability and collision protection characteristics of the transmitters, and expands the common mode range of the bus.
Super io: the I/O chip is responsible for providing serial and parallel interfaces, a floppy disk drive, a keyboard and a mouse and other control interfaces.
FIFO: (First Input First Output), i.e., a first-in first-out queue.
BIOS: (Basic Input Output System), i.e., basic input output system.
GPIO: (General Purpose Input Output), a general purpose input/output interface.
FPGA (Field-Programmable GATE ARRAY), a Field Programmable gate array, is implemented in parallel and appears as a semi-custom circuit in the Field of Application Specific Integrated Circuits (ASICs).
SP339: the multi-protocol transceiver chip can realize flexible switching of different modes of RS232/RS422/RS485 of a serial port.
In the present application, the system control device may be ARM (Advanced RISC Machine) chips, DSP (DIGITAL SIGNAL Processing) chips, or FPGAs, and in the embodiment of the present application, FPGAs are taken as an example.
In a first aspect, the present application provides a serial port switching method, referring to fig. 1, fig. 1 shows a schematic flowchart of a serial port switching method according to an embodiment of the present application, where the serial port switching method includes the following steps:
step S101: the FPGA acquires a chip selection instruction of a serial port, wherein the chip selection instruction comprises the following steps: first target identification information of the target output channel and second target identification information of the target output mode.
In an alternative embodiment, the step of obtaining, by the FPGA, a chip select instruction of a serial port includes: and the FPGA acquires a chip selection instruction of the serial port which is changed by the user through the BIOS from the BIOS ROM.
Specifically, the first target identification information of the target output channel and the second target identification information of the target output mode are registered in the BIOS ROM, and if the user wants to switch between the output channel and the output mode of the serial port, the user only needs to change the chip selection instruction in the BIOS ROM through the BIOS.
Step S102: and the FPGA determines a target output channel according to the first target identification information.
In an alternative embodiment, the step of determining, by the FPGA, a target output channel according to the first target identification information includes: and the FPGA queries the output channel corresponding to the first target identification information according to the first target identification information and a corresponding table of the target identification information of the output channel and the output channel.
For example, the output channel of the serial port includes: COM1, COM2, COM3 and COM4. The BIOS ROM comprises the following components: two registers of CONFIG1 and CONFIG0 are used for registering target identification information of an output channel, and each register is registered with a one-bit binary number; the first target identification information is a binary number, wherein the corresponding relation between the output channel of the serial port and the target identification information is shown in table 1, and table 1 shows the corresponding relation between the target identification information of the output channel and the output channel according to an embodiment of the present application.
TABLE 1
And under the condition that the first target identification information is 00, the output channel obtained by query is COM1.
And under the condition that the first target identification information is 01, the output channel obtained by query is COM2.
In the case that the first target identification information is 10, the output channel obtained by query is COM3.
In the case that the first target identification information is 11, the output channel obtained by query is COM4.
When a hardware fault occurs in a serial port actual interface, serial port output channel selection can be directly performed in the BIOS, namely, switching is performed among COM1, COM2, COM3 and COM4, and a required serial port communication mode is switched to other serial ports, so that normal operation of communication is ensured, and the reliability is high.
In an alternative embodiment, the target identification information of all the output channels is common target identification information, that is, all the output channels are set to be COM1, and in this case, in order to avoid the serial port from receiving and transmitting faults, the serial port can only accept a single sending task. For example, a broadcast system may have multiple speakers playing the same sound information at the same time.
Step S103: and the FPGA switches the output channel executed by the serial port to a target output channel.
In an alternative embodiment, the FPGA uses the queried output channel as the target output channel.
Step S104: and the FPGA sends the second target identification information to a transceiver chip.
In an alternative embodiment, the step of the FPGA sending the second target identification information to a transceiver chip includes: the FPGA converts the second target identification information into new second target identification information and sends the new second target identification information to a transceiver chip.
The transceiver chip is SP339, because the communication mode of BIOS is SPI, and SP339 can not carry out SPI's communication mode, need use FPGA to carry out information transfer to the chip selection instruction after the conversion can carry out high-low level operation to two PIN feet of SP 339.
Step S105: and the transceiver chip determines a target output mode according to the second target identification information.
The step of determining a target output mode by the transceiver chip according to the second target identification information includes: and the transceiver chip determines a target output mode according to the new second target identification information.
Because the communication mode of the BIOS is SPI, and the SP339 cannot perform SPI communication mode, information transfer is required to be performed by using the FPGA, so that the new second target identification information is the target identification information of the second target identification information after the second target identification information is converted by the FPGA.
In an alternative embodiment, the step of determining, by the transceiver chip, a target output mode according to the second target identification information includes: and the transceiver chip inquires the output mode corresponding to the second target identification information according to the second target identification information and a corresponding table of the target identification information and the output mode of the output mode.
For example, the output modes of the serial port include: RS232 LOOP BACK, RS232, RS422 and RS485, wherein the RS232 LOOP BACK is a TX-RX data transmission mode, and can judge the consistency of sending and receiving data, namely a serial port self-test mode.
The transceiver chip comprises: the MODE1 register and the MODE0 register are used for registering target identification information of an output MODE, and each register is registered with a one-bit binary number; the second target identification information is a binary number, wherein the corresponding relation between the output mode of the serial port and the target identification information is shown in table 2, and table 2 shows the corresponding table between the target identification information of the output mode and the output mode according to an embodiment of the present application.
TABLE 2
And under the condition that the second target identification information is 00, the output mode obtained by query is RS232 LOOP BACK.
And under the condition that the second target identification information is 01, the output mode obtained by query is RS232.
And under the condition that the second target identification information is 10, the output mode obtained by query is RS485.
In the case where the second target identification information is 11, the output pattern obtained by the query is RS422.
Under the condition of determining the switching channel, the serial ports can be flexibly switched among different output modes of the RS232 LOOP BACK, the RS232, the RS422 and the RS485 through the transceiver chip.
Step S106: the transceiver chip switches the output mode executed by the serial port to a target output mode.
In an alternative embodiment, the transceiver chip uses the queried output pattern as the target output pattern.
The serial port switching method can flexibly switch the output channel and the output mode of the serial port, can switch the output channel and the output mode of the serial port through software under the conditions of not changing external connection and not opening a case, and simultaneously uses FPGA programming, has the advantages of modularized operation, high portability, more flexible switching process and more selection, and is not easy to make mistakes.
In a second aspect, the present application further provides a serial port switching method, referring to fig. 2, fig. 2 shows a schematic flowchart of the serial port switching method according to an embodiment of the present application, where the serial port switching method includes the following steps:
Step S201: the FPGA acquires a chip selection instruction of the serial port which is changed by the user through the BIOS from the BIOS ROM.
Step S202: and the FPGA queries the output channel corresponding to the first target identification information according to the first target identification information and a corresponding table of the target identification information of the output channel and the output channel.
Step S203: the FPGA takes the output channel obtained by inquiry as a target output channel.
Step S204: the FPGA converts the second target identification information into new second target identification information and sends the new second target identification information to a transceiver chip.
Step S205: and the transceiver chip inquires the output mode corresponding to the new second target identification information according to the new second target identification information and the corresponding table of the target identification information of the output mode and the output mode.
Step S206: the transceiver chip takes the output mode obtained by query as a target output mode.
According to the serial port switching method, the output channels and the output modes of the serial port can be flexibly switched according to the first target identification information and the second target identification information, the output channels and the output modes of the serial port can be switched through software under the conditions that external connection is not changed and a case is not required to be opened, and meanwhile, FPGA programming is used, so that the serial port switching method is modularized in operation, high in portability, more in switching process, more in selection and less prone to error.
In a third aspect, referring to fig. 3, fig. 3 shows a schematic connection diagram of a serial port switching system according to an embodiment of the present application, including: the FPGA is configured to acquire a chip selection instruction of the serial port, and the chip selection instruction comprises: first target identification information of the target output channel and second target identification information of the target output mode. And determining a target output channel according to the first target identification information. And switching the output channel executed by the serial port to a target output channel. And sending the second target identification information to a transceiver chip.
And the transceiver chip is configured to determine a target output mode according to the second target identification information. And switching the output mode executed by the serial port to a target output mode.
The transceiver chip is SP339.
Super io configured to output serial signals to the FPGA.
And the BIOS is configured to send the chip selection instruction to the FPGA.
The serial port switching system can flexibly switch the output channel and the output mode of the serial port, can switch the output channel and the output mode of the serial port through software under the conditions of not changing external connection and not opening a case, and simultaneously uses FPGA programming, so that the serial port switching system is modularized in operation, high in portability, more flexible in switching process and more in selection, and is not easy to make mistakes.
In an alternative embodiment, referring to fig. 4, fig. 4 shows a connection relationship diagram of a serial port switching system according to an embodiment of the present application, in the serial port switching system, the BIOS ROM is connected to a Super io by connecting to a CPU, the Super io is connected to an FPGA, the FPGA is connected to at least one SP339, and the SP339 is externally connected to a DB9P interface conforming to an industry standard, so as to provide a composite serial port expansion hardware connection structure of cpu+super io & BIOS rom+fpga+sp339, so as to improve flexibility of serial port switching. Taking COM1 as an example in this embodiment, referring to table 3, table 3 shows a definition table of pins of a compound serial port under COM1 according to an embodiment of the present application. Wherein "x" indicates that the PIN is not functionally defined in the corresponding output mode.
TABLE 3 Table 3
The PC directly utilizes Super io to carry out serial port definition, and the Super io sends out a conventional output mode signal. In this embodiment, taking RS232 as an example, the RS232 interface definition refers to table 4, and table 4 shows a serial port definition table according to an embodiment of the present application.
TABLE 4 Table 4
Before entering the operating system, the PC can firstly change the chip selection configuration of the FPGA by changing the chip selection instruction by the BIOS system. Specifically, after a chip selection instruction is changed by entering the BIOS system, the BIOS ROM performs data transmission with the FPGA through a data bus, so that the chip selection result of the output channel by the changed FPGA is realized.
In an alternative embodiment, referring to fig. 4 and 5, fig. 5 is a schematic diagram illustrating a connection relationship between a serial port real interface and an output channel defined in a serial port according to an embodiment of the present application. A, B, C and D are four serial port real interfaces in the serial port switching system; the COM1, the COM2, the COM3 and the COM4 are output channels defined inside four serial ports, and each serial port actual interface is connected with the output channels defined inside the four serial ports, so that when a hardware fault occurs in a serial port actual interface, serial port output channel selection can be directly performed in the BIOS, a required serial port communication mode is switched to other serial ports, normal operation of communication is guaranteed, and reliability is high.
In an alternative embodiment, the FPGA is further configured to convert the second target identification information into new second target identification information and send the new second target identification information to the transceiver chip.
The transceiver chip is further configured to determine a target output mode based on the new second target identification information.
In an alternative embodiment, the FPGA is further configured to query the output channel corresponding to the first target identification information according to the first target identification information and a table of correspondence between target identification information of output channels and output channels. And taking the output channel obtained by query as a target output channel.
In an alternative embodiment, the transceiver chip is further configured to query the output mode corresponding to the second target identification information according to the second target identification information and a corresponding table of target identification information and output modes of the output mode. And taking the output mode obtained by query as a target output mode.
In an alternative embodiment, the FPGA is further configured to obtain, from the BIOS ROM, a chip select instruction of the serial port modified by the user through the BIOS.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (2)

1. The serial port switching method is characterized by comprising the following steps of:
The system control device obtains a chip selection instruction of the serial port, wherein the chip selection instruction comprises the following steps: first target identification information of the target output channel and second target identification information of the target output mode; the step of the system control device obtaining the chip selection instruction of the serial port comprises the following steps: the system control device obtains a chip selection instruction of the serial port which is changed by a user through the BIOS from the BIOS ROM;
The system control device determines a target output channel according to the first target identification information; the step of determining a target output channel by the system control device according to the first target identification information comprises the following steps: the system control device inquires an output channel corresponding to the first target identification information according to the first target identification information and a corresponding table of the target identification information and the output channel of the output channel; the system control device takes the output channel obtained by inquiry as a target output channel;
The system control device switches the output channel executed by the serial port to a target output channel;
The system control device sends the second target identification information to a transceiver chip; the step of the system control device transmitting the second target identification information to a transceiver chip includes: the system control device converts the second target identification information into new second target identification information and then sends the new second target identification information to the transceiver chip, the transceiver chip cannot be operated by the second target identification information, and the transceiver chip can be operated by the new second target identification information;
The transceiver chip determines a target output mode according to the second target identification information; the step of determining a target output mode by the transceiver chip according to the second target identification information includes: the transceiver chip determines a target output mode according to the new second target identification information; the step of determining a target output mode by the transceiver chip according to the second target identification information, further comprises: the transceiver chip inquires an output mode corresponding to the second target identification information according to the second target identification information and a corresponding table of the target identification information and the output mode of the output mode; the transceiver chip takes the output mode obtained by query as a target output mode;
The transceiver chip switches the output mode executed by the serial port to a target output mode.
2. A serial port switching system, comprising:
The system control device is configured to acquire a chip selection instruction of the serial port, wherein the chip selection instruction comprises: first target identification information of the target output channel and second target identification information of the target output mode; determining a target output channel according to the first target identification information; switching the output channel executed by the serial port to a target output channel; transmitting the second target identification information to a transceiver chip; the system control device is further configured to obtain a chip selection instruction of the serial port modified by the user through the BIOS from the BIOS ROM; the system control device is further configured to convert the second target identification information into new second target identification information and then send the new second target identification information to the transceiver chip, wherein the transceiver chip cannot be operated by the second target identification information, and the transceiver chip can be operated by the new second target identification information; the system control device is further configured to query an output channel corresponding to the first target identification information according to the first target identification information and a corresponding table of the target identification information of the output channel and the output channel; taking the output channel obtained by inquiry as a target output channel;
A transceiver chip configured to determine a target output mode based on the second target identification information; switching the output mode executed by the serial port to a target output mode; the transceiver chip is further configured to determine a target output mode from the new second target identification information; the transceiver chip is further configured to query an output mode corresponding to the second target identification information according to the second target identification information and a corresponding table of target identification information and output mode of the output mode; and taking the output mode obtained by query as a target output mode.
CN201910496342.XA 2019-06-10 2019-06-10 Serial port switching method and system thereof Active CN110895501B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910496342.XA CN110895501B (en) 2019-06-10 2019-06-10 Serial port switching method and system thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910496342.XA CN110895501B (en) 2019-06-10 2019-06-10 Serial port switching method and system thereof

Publications (2)

Publication Number Publication Date
CN110895501A CN110895501A (en) 2020-03-20
CN110895501B true CN110895501B (en) 2024-05-14

Family

ID=69785794

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910496342.XA Active CN110895501B (en) 2019-06-10 2019-06-10 Serial port switching method and system thereof

Country Status (1)

Country Link
CN (1) CN110895501B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112181743B (en) * 2020-09-24 2023-04-11 中车青岛四方车辆研究所有限公司 Accompanying and measuring device of serial port equipment

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101520763A (en) * 2009-04-16 2009-09-02 成都市华为赛门铁克科技有限公司 Method for switching serial ports and sharing device of serial ports
CN102033833A (en) * 2009-09-25 2011-04-27 研祥智能科技股份有限公司 Serial port communication switching method and serial port communication system
CN102035532A (en) * 2009-09-28 2011-04-27 上海爱瑞科技发展有限公司 Software switching circuit for communication serial port
CN203966118U (en) * 2014-06-19 2014-11-26 甘肃交通职业技术学院 The VME bus multi-serial-port card of a kind of FPGA
CN104320594A (en) * 2014-11-21 2015-01-28 连明昌 Serial port matrix switcher based on FPGA
CN104811359A (en) * 2015-04-10 2015-07-29 深圳市元征科技股份有限公司 Serial port communication method and terminal
CN105718410A (en) * 2016-01-19 2016-06-29 山东超越数控电子有限公司 Adaptor for converting LPC (Low Pin Count) into SPI (Serial Peripheral Interface) and I2C based on FPGA (Field-Programmable Gate Array) and realizing method of adaptor
CN205375458U (en) * 2016-01-20 2016-07-06 北京航宇天创科技发展有限公司 Four -channel's multi -protocols communication interface card
CN107451087A (en) * 2017-07-31 2017-12-08 郑州云海信息技术有限公司 A kind of similarities and differences based on FPGA walk changeable serial ports and application method
CN108600017A (en) * 2018-04-27 2018-09-28 中国科学院长春光学精密机械与物理研究所 Multi-protocols serial ports expansion method
CN109672574A (en) * 2019-01-29 2019-04-23 四川九洲电器集团有限责任公司 A kind of adaptive switching module of multilink for unmanned platform telemetry communication

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8959397B2 (en) * 2013-03-15 2015-02-17 Portwell Inc. Computer-on-module debug card assembly and a control system thereof

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101520763A (en) * 2009-04-16 2009-09-02 成都市华为赛门铁克科技有限公司 Method for switching serial ports and sharing device of serial ports
CN102033833A (en) * 2009-09-25 2011-04-27 研祥智能科技股份有限公司 Serial port communication switching method and serial port communication system
CN102035532A (en) * 2009-09-28 2011-04-27 上海爱瑞科技发展有限公司 Software switching circuit for communication serial port
CN203966118U (en) * 2014-06-19 2014-11-26 甘肃交通职业技术学院 The VME bus multi-serial-port card of a kind of FPGA
CN104320594A (en) * 2014-11-21 2015-01-28 连明昌 Serial port matrix switcher based on FPGA
CN104811359A (en) * 2015-04-10 2015-07-29 深圳市元征科技股份有限公司 Serial port communication method and terminal
CN105718410A (en) * 2016-01-19 2016-06-29 山东超越数控电子有限公司 Adaptor for converting LPC (Low Pin Count) into SPI (Serial Peripheral Interface) and I2C based on FPGA (Field-Programmable Gate Array) and realizing method of adaptor
CN205375458U (en) * 2016-01-20 2016-07-06 北京航宇天创科技发展有限公司 Four -channel's multi -protocols communication interface card
CN107451087A (en) * 2017-07-31 2017-12-08 郑州云海信息技术有限公司 A kind of similarities and differences based on FPGA walk changeable serial ports and application method
CN108600017A (en) * 2018-04-27 2018-09-28 中国科学院长春光学精密机械与物理研究所 Multi-protocols serial ports expansion method
CN109672574A (en) * 2019-01-29 2019-04-23 四川九洲电器集团有限责任公司 A kind of adaptive switching module of multilink for unmanned platform telemetry communication

Also Published As

Publication number Publication date
CN110895501A (en) 2020-03-20

Similar Documents

Publication Publication Date Title
US7721028B2 (en) Keyboard video mouse (KVM) switch between plurality of internal USB hubs each associated with plurality of audio codecs connected to the downstream port of associated USB hub
KR101496672B1 (en) Mobile Industry Processor Interface
CN102981989B (en) The apparatus and method of general-purpose serial bus USB communication
CN212391573U (en) Chip testing device and equipment
CN102932489A (en) Multi-channel ARINC429 bus interface
US8798930B2 (en) Method for servicing a field device of process automation technology having at least two measurement channels and field device of process automation technology having at least two measurement channels and being suitable for performing the method
US9984024B2 (en) USB control circuit with built-in bypass function
KR20210002515A (en) Receiving circuit, reconstruction method of receiving circuit, and electronic device
CN110895501B (en) Serial port switching method and system thereof
US8467751B2 (en) Serial interface communication test apparatus and test method using the same
US10146728B2 (en) USB control circuit with built-in signal repeater circuit
US7694053B2 (en) Slave assembly for determining source of data received over a two-wire master-slave communications bus
CN106207685A (en) A kind of plug interconnecting device
CN110247265B (en) Multifunctional data line, switching circuit and switching method
JPH0227443A (en) Diagnosis control device
CN101471970B (en) Portable electronic device
US9996492B2 (en) Coupling device and method for dynamically allocating USB endpoints of a USB interface, and exchange trading system terminal with coupling device
CN114040370B (en) Debugging system of many bluetooth equipment
CN110471881B (en) Method for realizing rapid communication between multiple slave devices and SPI (Serial peripheral interface) master device
CN210129113U (en) EtherCAT control structure with main line control and independent control
CN114124146A (en) External port expansion device for network analyzer and radio frequency switch control method
CN114461554A (en) Redundant communication control system, redundant communication control method, and integrated device
CN104426566A (en) Data transceiving system and data transceiving method
CN114896185B (en) MIPI interface data receiving and transmitting device and mobile terminal
US9288296B2 (en) Mobile phone and method for outputting kernel message

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20230707

Address after: 518057 1701, Yanxiang science and technology building, 31 Gaoxin middle Fourth Road, Maling community, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province

Applicant after: Yanxiang smart IOT Technology Co.,Ltd.

Address before: No.1, Yanxiang Zhigu chuangxiangdi, No.11, Gaoxin Road, Guangming New District, Shenzhen, Guangdong 518107

Applicant before: EVOC INTELLIGENT TECHNOLOGY Co.,Ltd.

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant