CN110888048A - Integrated circuit chip and fuse testing method - Google Patents

Abstract

The present disclosure relates to a method for testing an integrated circuit chip and a fuse, comprising: a substrate, a plurality of conductive layers, a dielectric layer, a fuse, and a latch circuit; a dielectric layer is arranged between the adjacent conducting layers, a dielectric layer is arranged between the substrate and the conducting layer adjacent to the substrate, and a contact hole is formed in the dielectric layer; the fuse is positioned on a first conducting layer, the first conducting layer is the conducting layer positioned on the uppermost layer in the multiple conducting layers, the conducting layer is the bottom layer close to the substrate, and the conducting layer is the upper layer far away from the substrate; a latch circuit is disposed on the substrate and connected to the fuse. When the integrated circuit chip is tested, the latch effect is triggered, so that the current in the latch circuit is continuously increased until the fuse is blown, and the fuse is blown during the test of the fuse. And when testing a plurality of fuses, only need the latch circuit of order triggering every fuse can, promoted efficiency of software testing, practiced thrift test time.

Description

Integrated circuit chip and fuse testing method

Technical Field

The disclosure relates to the technical field of integrated circuits, in particular to an integrated circuit chip and a fuse testing method.

Background

As technology develops and advances, integrated circuits are becoming more widely used, and a large number of fuses are often included in the integrated circuits.

Currently, fuses used in integrated circuits are typically gate oxide fuses, which are open before they are blown, and require a large voltage difference to be applied between the conductive gate and the heavily doped layer to blow the fuse.

When the integrated circuit is tested, the fuse is required to be tested, and the fusing efficiency of the grid oxide fuse is low, so that the testing time is long and the testing efficiency is low.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to an integrated circuit chip and a method for testing a fuse, which overcome at least some of the problems of long testing time and low testing efficiency of an integrated circuit due to limitations and disadvantages of the related art.

According to an aspect of the present disclosure, there is provided an integrated circuit chip including:

a substrate;

the multilayer conducting layer is provided with a dielectric layer between the adjacent conducting layers, a dielectric layer is arranged between the substrate and the conducting layer adjacent to the substrate, and a contact hole is formed in the dielectric layer;

the fuse is positioned on a first conducting layer, the first conducting layer is the conducting layer positioned on the uppermost layer in the multiple conducting layers, the conducting layer is the bottom layer close to the substrate, and the conducting layer is the upper layer far away from the substrate;

and a latch circuit disposed in the substrate and connected to the fuse.

According to an embodiment of the present disclosure, a first through hole is disposed on the first conductive layer, and the fuse is located in the through hole.

According to an embodiment of the present disclosure, the integrated circuit chip further includes:

and the connector is positioned in the contact hole of the dielectric layer and is used for connecting the conducting layers on two sides of the dielectric layer.

According to an embodiment of the present disclosure, the first conductive layer is used for connecting a power supply and receiving a power supply signal.

According to an embodiment of the present disclosure, a disconnection detecting device for detecting whether the fuse is blown is connected to the second conductive layer, which is a conductive layer located between the first conductive layer and the substrate.

According to an embodiment of the present disclosure, the fuse is a metal fuse.

According to an embodiment of the present disclosure, the plurality of conductive layers and the substrate are disposed parallel to each other.

According to an embodiment of the present disclosure, the fuse is a fuse, and a resistance of the fuse is greater than a resistance of the first conductive layer and a resistance of the connector.

According to an embodiment of the present disclosure, a width of the fuse is smaller than a width of the first conductive layer.

According to an embodiment of the present disclosure, a thickness of the fuse is smaller than a thickness of the first conductive layer.

According to an embodiment of the present disclosure, the integrated circuit chip further includes:

and the passivation layer is positioned on one side of the first conductive layer, which is far away from the substrate.

According to another aspect of the present disclosure, there is provided a method of testing an integrated circuit chip fuse, comprising:

triggering the latch effect of the latch circuit and outputting fusing current;

the fusing current flows through the connector, the conductive layer and the fuse, fusing the fuse.

According to an embodiment of the present disclosure, the testing method further includes:

detecting whether the fuse is blown;

if the fuse is fused, outputting a first signal;

and if the fuse is not fused, outputting a second signal.

The utility model provides an integrated circuit chip sets up the fuse on first to the electric layer to connect fuse and latch circuit, when integrated circuit chip test, trigger latch effect, make the electric current in the latch circuit constantly increase, until blowing the fuse, realized the fusing when testing the fuse. And when testing a plurality of fuses, only need the latch circuit of order triggering every fuse can, promoted efficiency of software testing, practiced thrift test time.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic structural diagram of an integrated circuit chip according to an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a fuse connection provided in an exemplary embodiment of the present disclosure.

Fig. 3 is a top view of a fuse and conductive layers provided by an exemplary embodiment of the present disclosure.

Fig. 4 is a schematic cross-sectional view of a fuse according to an exemplary embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of a CMOS device according to an exemplary embodiment of the present disclosure.

Fig. 6 is an equivalent circuit of the parasitic latch circuit of the CMOS device shown in fig. 5.

Fig. 7 is a schematic structural diagram of another CMOS device according to an exemplary embodiment of the present disclosure.

Fig. 8 is an equivalent circuit of the parasitic latch circuit of the CMOS device shown in fig. 6.

Fig. 9 is a diagram of a latch circuit trigger signal according to an exemplary embodiment of the present disclosure.

FIG. 10 is a flowchart of a method for detecting fuses of an integrated circuit chip according to an exemplary embodiment of the present disclosure.

FIG. 11 is a flow chart of another method for detecting integrated circuit chip fuses provided in an exemplary embodiment of the present disclosure.

In the figure:

100. a substrate; 200. a conductive layer; 210. a first conductive layer; 220. a second conductive layer; 300. a dielectric layer; 400. a fuse; 500. a latch circuit; 600. a connector; 700. and a passivation layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.

In the related art, a gate oxide fuse is generally used in an integrated circuit, and the gate oxide fuse is in an open state before being blown, and a large voltage difference needs to be applied between a conductive gate and a heavily doped layer when being blown so as to blow the fuse. When carrying out the fuse test, to a plurality of fuses, often need to carry out the fusing test to one of them fuse at first, blow another again after a fuse is fused, lead to test time long, the efficiency of software testing is low.

First, in the present exemplary embodiment, there is provided an integrated circuit chip, as shown in fig. 1, including: substrate 100, multilayer conductive layer 200, fuse 400, and latch circuit 500;

a dielectric layer 300 is arranged between the adjacent conductive layers 200, a dielectric layer 300 is arranged between the substrate 100 and the adjacent conductive layers 200, and a contact hole is arranged on the dielectric layer 300;

a fuse 400 disposed on the first conductive layer 210, wherein the first conductive layer 210 is a conductive layer 200 disposed at the uppermost layer among the plurality of conductive layers 200, a bottom layer is disposed near the substrate 100, and an upper layer is disposed far from the substrate 100;

the latch circuit 500 is provided in the substrate 100 and connected to the fuse 400, and when the latch effect is triggered, the current in the latch circuit 500 increases to blow the fuse 400.

According to the integrated circuit chip provided by the embodiment of the disclosure, the fuse 400 is arranged on the first conductive layer, the fuse 400 is connected with the latch circuit 500, and when the integrated circuit chip is tested, the latch effect is triggered, so that the current in the latch circuit 500 is continuously increased until the fuse 400 is blown, and the fuse 400 is blown during testing. And when testing a plurality of fuses 400, only need the latch circuit 500 of each fuse 400 of sequential trigger can, promoted test efficiency, practiced thrift test time.

Further, since the dielectric layer 300 is an insulating layer, in order to realize electrical connection between the multiple conductive layers 200, the integrated circuit chip provided by the embodiment of the present disclosure may further include a connector 600, and the connector 600 is located in the contact hole in the dielectric layer 300. The connector 600 is used to connect the conductive layers 200 on both sides of the dielectric layer 300. The dielectric layer 300, which is positioned at the lowermost layer, has a lower side in contact with the substrate 100 and an upper side in contact with the second conductive layer 220. The latch circuit 500 is provided in the substrate 100, and a contact hole on the dielectric layer 300 contacting the substrate 100 is provided corresponding to the latch circuit 500, and the conductive layer 200 and the latch circuit 500 are connected by a connector 600 in the contact hole.

The connector 600 may be a connection wire, a conductive connection block, or the like, which is not particularly limited in this disclosure.

The integrated circuit chip provided by the embodiment of the present disclosure further includes a passivation layer 700, where the passivation layer 700 is located on a surface of the first conductive layer 210 away from the substrate 100, and the first conductive layer 210 is located on an uppermost layer of the plurality of conductive layers 200. The passivation layer 700 serves to prevent contamination of the surface of the integrated circuit chip and to protect the conductive layer 200.

The first conductive layer 210 is provided with a first through hole, the fuse 400 is located in the through hole, and the first conductive layer 210 is connected with a power supply for receiving a power supply signal. The power supply signal may be high or low. The power supply, fuse 400 and latch circuit 500 form a fuse 400 detection circuit. When the fuse 400 is tested, the latch-up effect is triggered by the trigger signal, the current in the latch circuit 500 increases, and the current flowing through the fuse 400 increases until the fuse 400 is blown.

In practical applications, the fuse 400 and the first conductive layer 210 may also be a unitary structure, and the fuse 400 is formed by etching the first conductive layer 210 so that the thickness of the fuse 400 in the first conductive layer 210 is reduced.

The second conductive layer 220 is connected with a disconnection detecting means for detecting whether the fuse 400 is blown or not, and the second conductive layer 220 is a conductive layer 200 between the first conductive layer 210 and the substrate 100. The disconnection detecting device may be a latch circuit or other disconnection detecting circuit.

For example, as shown in FIG. 1, an integrated circuit chip includes a three-layer conductive layer 200 with a fuse 400 disposed in the uppermost first conductive layer 210. A connector 600 is disposed in the contact hole of the dielectric layer 300, a latch circuit 500 is disposed in the substrate 100, and the latch circuit 500 is connected to the connector 600 in the dielectric layer 300 which is in contact with the substrate 100. The connection to the fuse 400 is finally achieved through the conductive layer 200 and the connector 600 thereon.

Further, to ensure that the current in the circuit increases when the latch-up is triggered, fuse 400 is blown without damaging other devices. In the disclosed embodiment, the fuse 400 and the connector 600 may be made of the same conductive material. The resistance of the fuse 400 is required to be greater than the resistance of the connector 600 and the resistance of the first conductive layer 210 to ensure that the fuse 400 is blown first without damaging other devices when blown.

Illustratively, as shown in fig. 3 and 4, the width D of the fuse 400 may be designed to be smaller than the width D of the first conductive layer 210, the width of the fuse 400 may be 50nm to 300nm, the length L of the fuse 400 is 50nm to 300nm, the height Z of the fuse 400 is 100nm to 350nm, and the width 2D <3D of the first conductive layer 210.

The conductive layers 200 are disposed in parallel with each other, and the conductive layers 200 are disposed in parallel with the substrate 100, wherein the conductive layers 200 are metal conductive layers, the material of which may be copper or aluminum, and the connector 600 is a metal connector. The fuse 400 may be a fuse or other fuse, and the fuse may be made of the same material as the connector 600 or may be made of a different material. The thickness of the fuse is less than the thickness of the first conductive layer 210.

The latch-up circuit described in the embodiments of the present disclosure may be a parasitic circuit generated by latch-up of a CMOS device. For example, in one possible embodiment of the present disclosure, parasitic circuits may be created by the CMOS device shown in fig. 5. The CMOS comprises a substrate Su, wherein an NMOS and a PMOS are arranged on the substrate Su, the NMOS comprises a P-type silicon substrate Su with lower doping concentration, namely a P well PW shown in the figure, and two heavily doped N + regions and a heavily doped P + region are manufactured on the P well PW. The PMOS includes an N-type silicon substrate Su with a low doping concentration, i.e., an N-well NW as shown in the figure, and two heavily doped P + regions and one heavily doped N + region are formed on the N-well NW.

In the CMOS, a first parasitic transistor Q1 and a second parasitic transistor Q2 are formed due to latch-up effect, a first emitter and a second emitter of the first parasitic transistor Q1 are connected with high level, a collector is connected with low level, and a base receives a first trigger signal; the collector of the second parasitic transistor Q2 is connected with the base of the first transistor, the collector is connected with high level, the base is connected with the collector of the first parasitic transistor Q1, the base receives the second trigger signal, and the first emitter and the second emitter are connected with low level to form a latch circuit.

As shown in fig. 6, the fuse may be connected to the first emitter of the first parasitic transistor Q1, one end of the fuse Fu is connected to the first emitter of the first parasitic transistor Q1, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the source of the PMOS. When the latch-up effect of the CMOS is triggered, the current in the latch circuit is continuously increased, and the current flowing through the fuse Fu is also continuously increased, so that the fuse Fu is finally blown. Of course, the fuse may be disposed at the second emitter of the first parasitic transistor Q1, the first emitter of the second parasitic transistor Q2, or the second emitter of the second parasitic transistor Q2.

In practical applications, a CMOS as shown in fig. 5 may be disposed on the substrate, and when detecting, the latch-up effect of the CMOS is triggered by the trigger signal, so that the current flowing through the fuse is increased continuously to blow the fuse. The trigger signal may be an up-shoot signal or an down-shoot signal at the trigger end of the latch circuit. For example, in the circuit shown in fig. 6, the first receiving terminal G1 is disposed at the base of the second parasitic transistor Q2, the second receiving terminal G2 is disposed at the base of the first parasitic transistor Q1, the third receiving terminal G3 is disposed at the high-level terminal, and the fourth receiving terminal G4 is disposed at the low-level terminal. The latch circuit may be triggered by a trigger signal as shown in fig. 10.

In another possible embodiment of the present disclosure, the latch circuit may be generated by a structure as shown in fig. 7, which includes a substrate Su having an N-type region and a P-type region, i.e., an N-well NW and a P-well PW, wherein the N-well NW is formed with heavily doped P + and N +, and the P-well PW is formed with heavily doped P + and N +. A third parasitic transistor Q3 and a fourth parasitic transistor Q4 are formed on the structure, wherein the emitter of the third parasitic transistor Q3 is connected with high level, the collector is connected with low level, and the base receives the first trigger signal; the fourth parasitic transistor Q4 has a collector connected to the base of the third transistor, a collector connected to a high level, a base connected to the collector of the first parasitic transistor Q1, a base receiving the second trigger signal, and an emitter connected to a low level, forming a latch circuit. In the latch circuit, the current in the latch circuit gradually increases after receiving the trigger signal.

Fig. 8 is an equivalent circuit diagram of the parasitic circuit and the fuse Fu in fig. 7, and the fuse Fu may be connected to the emitter of the third parasitic transistor Q3, as shown in fig. 8. One end of the fuse Fu is connected to the emitter of the third parasitic transistor Q3, and the other end is connected to the power supply. Correspondingly, a P + terminal on the N-type region. When the latch-up is triggered, the current in the latch circuit increases continuously, and the current flowing through the fuse Fu also increases continuously, so that the fuse Fu is blown out finally. Of course, the fuse may be provided at the emitter of the fourth parasitic transistor Q4.

In practical applications, the structure shown in fig. 7 may be disposed on a substrate, and when detecting, the latch-up effect of the CMOS is triggered by a trigger signal, so that the current flowing through the fuse is increased continuously to blow the fuse. The trigger signal may be an up-shoot signal or an down-shoot signal at the trigger end of the latch circuit.

There is also provided in this example embodiment a method of testing an integrated circuit chip fuse, as shown in fig. 10, the method including the steps of:

step S1, triggering the latch effect of the latch circuit and outputting fusing current;

in step S2, the fusing current flows through the connector, the conductive layer, and the fuse is fused.

By triggering the latch effect of the latch circuit, the fusing current output by the latch circuit is continuously increased, so that the fuse is rapidly fused, and the detection time is saved. When a plurality of fuses are detected, the fuses can be guaranteed only by sequentially triggering the latch circuits, the condition that the fuses of another fuse are blown after the current fuse is blown in the related technology is avoided, the detection time is saved, and the detection efficiency is improved.

Optionally, as shown in fig. 11, after step S2, the method for detecting a fuse of an integrated circuit chip according to the embodiment of the present disclosure may further include:

step S3, detecting whether the fuse is blown;

step S4, if the fuse is fused, outputting a first signal;

and step S5, if the fuse is not fused, outputting a second signal.

In step S3, whether the fuse is blown or not may be detected by a disconnection detecting means, such as a latch circuit or the like; in step S4, if the fuse is blown, the entire circuit is opened, and the disconnection detecting means outputs a first signal indicating that the fuse has been blown; in step S5, if the fuse is blown, a second signal is output, and the second signal indicates that the fuse is defective or that the circuit is faulty.

Whether the fuse is fused or not is detected, the first signal is output when the fuse is fused, and the second signal is output when the fuse is not fused, so that the fuse test result is convenient to obtain, and the problem that the test result of the fuse cannot be directly obtained because the fuse is located inside an integrated circuit chip is avoided.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (13)

1. An integrated circuit chip, comprising:

a substrate;

the multilayer conducting layer is provided with a dielectric layer between the adjacent conducting layers, a dielectric layer is arranged between the substrate and the conducting layer adjacent to the substrate, and a contact hole is formed in the dielectric layer;

the fuse is positioned on a first conducting layer, the first conducting layer is the conducting layer positioned on the uppermost layer in the multiple conducting layers, the conducting layer is the bottom layer close to the substrate, and the conducting layer is the upper layer far away from the substrate;

and a latch circuit disposed in the substrate and connected to the fuse.

2. The integrated circuit chip of claim 1, wherein the first conductive layer has a first via disposed thereon, the fuse being located in the via.

3. The integrated circuit chip of claim 2, wherein the integrated circuit chip further comprises:

and the connector is positioned in the contact hole of the dielectric layer and is used for connecting the conducting layers on two sides of the dielectric layer.

4. The integrated circuit chip of claim 1, wherein the first conductive layer is for connection to a power supply for receiving a power supply signal.

5. The integrated circuit chip of claim 1, wherein a disconnection detection device is coupled to the second conductive layer, the disconnection detection device being configured to detect whether the fuse is blown, the second conductive layer being a conductive layer located between the first conductive layer and the substrate.

6. The integrated circuit chip of claim 1, wherein the fuse is a metal fuse.

7. The integrated circuit chip of claim 1, wherein a plurality of said conductive layers and said substrate are disposed parallel to each other.

8. The integrated circuit chip of claim 1, wherein the fuse is a fuse having a resistance greater than a resistance of the first conductive layer and a resistance of the connector.

9. The integrated circuit chip of claim 8, wherein a width of the fuse is less than a width of the first conductive layer.

10. The integrated circuit chip of claim 8, wherein a thickness of the fuse is less than a thickness of the first conductive layer.

11. The integrated circuit chip of any of claims 1-10, wherein the integrated circuit chip further comprises:

and the passivation layer is positioned on one side of the first conducting layer far away from the substrate.

12. A method of testing an integrated circuit chip fuse, comprising:

triggering the latch effect of the latch circuit and outputting fusing current;

the fusing current flows through the connector, the conductive layer and the fuse, fusing the fuse.

13. The test method of claim 12, further comprising:

detecting whether the fuse is blown;

if the fuse is fused, outputting a first signal;

and if the fuse is not fused, outputting a second signal.

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