CN110875685A - Synchronous Buck switching power supply circuit - Google Patents

Synchronous Buck switching power supply circuit Download PDF

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Publication number
CN110875685A
CN110875685A CN201811002259.4A CN201811002259A CN110875685A CN 110875685 A CN110875685 A CN 110875685A CN 201811002259 A CN201811002259 A CN 201811002259A CN 110875685 A CN110875685 A CN 110875685A
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China
Prior art keywords
circuit
coupled
output end
dead time
output
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CN201811002259.4A
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Chinese (zh)
Inventor
龚宏国
王俊
苏振江
郭振业
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201811002259.4A priority Critical patent/CN110875685A/en
Publication of CN110875685A publication Critical patent/CN110875685A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

A synchronous Buck switching power supply circuit comprising: the PWM wave generating circuit comprises a PWM wave generating circuit, a dead time control circuit, a driving circuit and a filter shaping circuit, wherein the output end of the PWM wave generating circuit is coupled with the PWM wave input end of the dead time control circuit; the driving circuit comprises an upper MOS tube and a lower MOS tube, wherein the grid electrode of the upper MOS tube is coupled with a first signal output end of the dead time control circuit, and the grid electrode of the lower NMOS tube is coupled with a second signal output end of the dead time control circuit; the driving circuit comprises an upper MOS tube and a lower MOS tube, wherein the grid electrode of the upper MOS tube is coupled with a first signal output end of the dead time control circuit, and the grid electrode of the lower NMOS tube is coupled with a second signal output end of the dead time control circuit; the filter shaping circuit is coupled with the output end of the driving circuit. According to the scheme, the dead time of the synchronous Buck switching power supply circuit can be automatically adjusted, and the power consumption of the synchronous Buck switching power supply circuit is reduced.

Description

Synchronous Buck switching power supply circuit
Technical Field
The invention relates to the field of circuits, in particular to a synchronous Buck switching power supply circuit.
Background
In a synchronous Buck (power supply conversion) switch power supply circuit, dead time is set for avoiding the simultaneous conduction of a PMOS (P-channel metal oxide semiconductor) tube and an NMOS (N-channel metal oxide semiconductor) tube of an output power tube, namely the dead time is the time difference between the conduction of the PMOS tube and the conduction of the NMOS tube.
The length of the dead time is an important parameter influencing the synchronous Buck switching power supply circuit. The dead time of a classical synchronous Buck switching power supply circuit is usually predetermined, for example, with a fixed time delay as the dead time. In addition, when the PMOS tube of the output power tube works in a dead zone, the body diode of the NMOS tube is conducted, and the conduction voltage of the body diode is larger, so that the loss of the synchronous Buck switching power supply circuit is increased along with the increase of the dead zone time.
Disclosure of Invention
The embodiment of the invention solves the technical problem of how to automatically adjust the dead time of the synchronous Buck switching power supply circuit and reduce the power consumption of the synchronous Buck switching power supply circuit.
To solve the above technical problem, an embodiment of the present invention provides a synchronous Buck switching power supply circuit, including: PWM ripples generating circuit, dead time control circuit, drive circuit and filter shaping circuit, wherein: the output end of the PWM wave generating circuit is coupled with the PWM wave input end of the dead time control circuit; the driving circuit comprises an upper MOS tube and a lower MOS tube, wherein the grid electrode of the upper MOS tube is coupled with a first signal output end of the dead time control circuit, and the grid electrode of the lower MOS tube is coupled with a second signal output end of the dead time control circuit; the driving circuit is suitable for outputting a dead zone identification signal when the upper MOS tube and the lower MOS tube are both cut off; the dead time control circuit is coupled with the output end of the drive circuit at the feedback signal input end and is suitable for controlling the conduction of the upper MOS tube and the lower MOS tube in the first-in cut-off state when receiving a dead time identification signal output by the output end of the drive circuit; and the input end of the filter shaping circuit is coupled with the output end of the drive circuit and is suitable for carrying out filter shaping processing on the output signal of the output end of the drive circuit.
Optionally, the dead time control circuit includes: inverting circuit, dead zone detection circuit, flip-flop circuit, NOR gate and NAND gate, wherein: the input end of the inverter circuit is coupled with the output end of the PWM wave generating circuit, and the output end of the inverter circuit is coupled with the data signal input end of the trigger circuit; the input end of the dead zone detection circuit is coupled with the output end of the driving circuit, the output end of the dead zone detection circuit is coupled with the clock signal input end of the trigger circuit, and the dead zone detection circuit is suitable for generating a trigger signal and outputting the trigger signal to the clock signal input end of the trigger circuit when the dead zone time of the driving circuit is detected; the output end of the trigger circuit is coupled with the second input end of the nor gate and the first input end of the nand gate, and the trigger circuit is suitable for outputting the input signal of the data signal input end when the trigger signal input by the clock signal input end is detected; the first input end of the NOR gate is coupled with the output end of the inverter circuit, and the output end of the NOR gate is coupled with the grid electrode of the upper MOS tube of the driving circuit; and the second input end of the NAND gate is coupled with the output end of the inverter circuit, and the output end of the NAND gate is coupled with the grid electrode of the lower MOS tube of the driving circuit.
Optionally, the dead zone detection circuit is a body diode detection circuit; the input end of the body diode detection circuit is coupled with the output end of the driving circuit, and the output end of the body diode detection circuit is coupled with the clock signal input end of the trigger circuit.
Optionally, the trigger circuit is a D flip-flop.
Optionally, in the D flip-flop, a data signal input end is coupled to the input end of the inverter circuit, a clock signal input end is coupled to the output end of the dead zone detection circuit, and an output end is coupled to the second input end of the nor gate and the first input end of the nand gate.
Optionally, the inverting circuit is an inverter.
Optionally, the upper MOS transistor is a PMOS transistor, and the lower MOS transistor is an NMOS transistor, wherein: the source electrode of the PMOS tube inputs a high-level signal, the drain electrode of the PMOS tube is coupled with the drain electrode of the NMOS tube, and the grid electrode of the PMOS tube is coupled with the first signal output end of the dead time control circuit; and the source electrode of the NMOS tube is coupled with the ground, and the grid electrode of the NMOS tube is coupled with the second signal output end of the dead time control circuit.
Optionally, the filter shaping circuit includes: inductance, first resistance, electric capacity and second resistance, wherein: the first end of the inductor is coupled with the output end of the dead time control circuit, and the second end of the inductor is coupled with the first end of the first resistor; the second end of the first resistor is coupled with the first end of the capacitor; the second end of the capacitor is coupled with the ground; and the first end of the second resistor is coupled with the first end of the capacitor, and the second end of the second resistor is coupled with the second end of the capacitor.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
when the dead time control circuit detects the dead time identification signal output by the output end of the drive circuit, the dead time control circuit controls the conduction of the upper MOS tube and the lower MOS tube in the drive circuit which are in the cut-off state firstly, so that the drive circuit is separated from the dead time rapidly, and the dead time of the synchronous Buck switching power supply circuit can be automatically adjusted. Since the dead time of the synchronous Buck switching power supply circuit is reduced, the power consumption of the synchronous Buck switching power supply circuit is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a synchronous Buck switching power supply circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a dead time control circuit according to an embodiment of the present invention;
fig. 3 is a timing diagram of an operation of a synchronous Buck switching power supply circuit according to an embodiment of the present invention.
Detailed Description
In the prior art, the dead time of the synchronous Buck switching power supply circuit is usually preset, for example, a fixed time delay is set as the dead time. However, for the synchronous Buck switching power supply circuit, the dead time required for different loads and switching frequencies may be different, resulting in the dead time set with a fixed time delay not being the optimal dead time in most operating situations, resulting in a larger power consumption of the synchronous Buck switching power supply circuit.
In the embodiment of the invention, when the dead time control circuit detects the dead time identification signal output by the output end of the drive circuit, the dead time control circuit controls the conduction of the upper MOS tube and the lower MOS tube in the drive circuit which are in the cut-off state firstly, so that the drive circuit is quickly separated from the dead time, and the dead time of the synchronous Buck switch power supply circuit can be automatically adjusted. Since the dead time of the synchronous Buck switching power supply circuit is reduced, the power consumption of the synchronous Buck switching power supply circuit is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a synchronous Buck switch power supply circuit, which comprises: a PWM wave generating circuit 11, a dead time control circuit 12, a drive circuit 13, and a filter shaping circuit 14.
And a PWM wave generating circuit 11, an output terminal of which is coupled to a PWM wave input terminal of the dead time control circuit 12, and adapted to generate a PWM wave and output it to the dead time control circuit 12.
In practical applications, the duty ratio and the frequency of the PWM wave can be set according to specific application scenarios and application requirements. The PWM wave generating circuit 11 may be a PWM wave generating circuit existing in the prior art, and the specific structure and the working principle thereof are not described in detail in the embodiment of the present invention.
The driving circuit 13 may include an upper MOS transistor and a lower MOS transistor. In the embodiment of the present invention, the gate of the upper MOS transistor may be coupled to the first signal output terminal CLK _1 of the dead time control circuit 12, and the gate of the lower MOS transistor may be coupled to the second signal output terminal CLK _2 of the dead time control circuit 12. In practical applications, it can be known that when both the upper MOS transistor and the lower MOS transistor of the driving circuit 13 are in the off state, the driving circuit 13 enters the dead-zone state. Therefore, when the drive circuit 13 enters the dead zone state, the drive circuit 13 can output the dead zone flag signal.
In the embodiment of the present invention, when both the upper MOS transistor and the lower MOS transistor of the driving circuit 13 are in the off state, the level of the output signal of the output terminal of the driving circuit 13 is a negative level; when any one of the upper MOS transistor and the lower MOS transistor of the driving circuit 13 is in a conducting state, the level of the output signal of the output terminal of the driving circuit 13 is a high level or a low level. In other words, the dead zone identification signal output by the output terminal of the drive circuit 13 is: the level of the signal having the negative level, that is, the level of the dead zone identifying signal, is the negative level.
Dead time control circuit 12, a feedback signal input may be coupled to an output of drive circuit 13. Therefore, the output terminal output signal of the driving circuit 13 can be input to the feedback signal input terminal of the dead time control circuit 12. When the dead time control circuit 12 receives the dead time identification signal output by the driving circuit 13, it may control the conduction of the upper MOS transistor and the lower MOS transistor which are first turned into the off state, so that the driving circuit 13 is separated from the dead time state.
A filter-shaping circuit 14, an input of which may be coupled to the output of the driving circuit 13, is adapted to perform a filter-shaping circuit 14 processing on the output signal at the output of the driving circuit 13.
In the embodiment of the present invention, the dead time control circuit 12 may control the levels of the output signals of the first signal output terminal CLK _1 and the second signal output terminal CLK _2 to control the first-to-off state of the upper MOS transistor and the lower MOS transistor.
Specifically, when the upper MOS transistor and the lower MOS transistor are both in the off state and the upper MOS transistor enters the off state later than the lower MOS transistor, the dead time control circuit 12 may control the level of the output signal of the second signal output terminal CLK _2 to be inverted, so that the lower MOS transistor is switched from the off state to the on state. After the lower MOS transistor is switched from the off state to the on state, the driving circuit 13 is out of the dead zone state.
Accordingly, when the upper MOS transistor and the lower MOS transistor are both in the off state, and the lower MOS transistor enters the off state later than the upper MOS transistor, the dead time control circuit 12 may control the level of the output signal of the first signal output terminal CLK _1 to be inverted, so that the upper MOS transistor is switched from the off state to the on state. When the upper MOS transistor is switched from the off state to the on state, the driving circuit 13 is out of the dead zone state.
In practical applications, the two MOS transistors in the driving circuit 13 may be a PMOS transistor and an NMOS transistor, respectively, where: the upper tube is a PMOS tube, and the lower tube is an NMOS tube. The two MOS transistors in the driving circuit 13 may also be both NMOS transistors.
In an embodiment of the present invention, the upper tube of the driving circuit 13 is a PMOS tube, and the lower tube is an NMOS tube. At this time, a high level signal is input to the source of the PMOS transistor, the drain of the PMOS transistor is coupled to the drain of the NMOS transistor, and the gate of the PMOS transistor is coupled to the first signal output terminal CLK _1 of the dead time control circuit 12. The source of the NMOS transistor is coupled to ground, the drain of the NMOS transistor is coupled to the drain of the PMOS transistor, and the gate of the NMOS transistor is coupled to the second signal output terminal CLK _2 of the dead time control circuit 12.
The dead time control circuit provided in the embodiment of the present invention is explained in detail below.
Referring to fig. 2, a schematic diagram of a dead time control circuit according to an embodiment of the present invention is shown, and is described below with reference to fig. 1.
In a specific implementation, the dead-time control circuit 12 may include an inverter circuit 21, a dead-time detection circuit 22, a flip-flop circuit 23, a nor gate 24, and a nand gate 25, wherein:
the input end of the inverter circuit 21 is a PWM wave input end of the dead time control circuit, and may be coupled to the output end of the PWM wave generating circuit; an output of inverting circuit 21 may be coupled to a signal input of triggering circuit 23;
an input terminal of the dead time detection circuit 22 is a feedback signal input terminal of the dead time control circuit, and may be coupled to an output terminal of the driving circuit; an output of the dead band detection circuit 22 may be coupled to a clock signal input of the trigger circuit 23. In the embodiment of the present invention, the dead time detection circuit 22 may generate a trigger signal when it is detected that the driving circuit enters the dead time, and output the trigger signal to the clock signal input terminal of the trigger circuit 23 via the output terminal.
A data signal input of the flip-flop 23 may be coupled to an output of the inverter circuit 21; a clock signal input of the trigger circuit 23 may be coupled to an output of the dead band detection circuit 22; the output of the flip-flop 23 may be coupled to a second input of the nor gate 24 and a first input of the nand gate 25, respectively. In the embodiment of the present invention, the trigger circuit 23 may output the current input signal of the data signal input terminal when detecting the trigger signal input by the clock signal input terminal.
A first input of nor gate 24 may be coupled to an output of inverting circuit 21; a second input of nor gate 24 may be coupled to an output of flip-flop circuit 23; the output terminal of the nor gate 24 is a first signal output terminal CLK _1 of the dead time control circuit, and may be coupled to the gate of the upper MOS transistor of the driving circuit.
In practical applications, the nor gate 24 is a logic operation device, and is adapted to perform nor operation on the input signal of the first input terminal and the input signal of the second input terminal and output the nor operation. Therefore, in the embodiment of the present invention, the nor gate 24 is adapted to perform nor operation on the output signal of the inverter circuit 21 and the output signal of the flip-flop circuit 23.
A first input terminal of the nand-gate 25 may be coupled to the output terminal of the flip-flop circuit 23, a second input terminal of the nand-gate 25 may be coupled to the output terminal of the inverter circuit 21, and an output terminal of the nand-gate 25 is a second signal output terminal CLK _2 of the dead time control circuit, and may be coupled to a gate of the lower MOS transistor of the driving circuit.
In practical applications, the nand gate 25 is a logic operation device, and is adapted to perform a nand operation on the input signal of the first input terminal and the input signal of the second input terminal and output the nand operation. Therefore, in the embodiment of the present invention, the nand gate 25 is adapted to perform a nand operation on the output signal of the inverter circuit 21 and the output signal of the flip-flop circuit 23.
In practical applications, when the lower tube of the driving circuit is an NMOS tube, a body diode exists between the source and the drain of the NMOS tube. Therefore, the dead zone detection circuit 22 can determine whether the drive circuit enters the dead zone by detecting whether the body diode is on.
In a specific implementation, the dead zone detection circuit 22 may be a body diode detection circuit. An input of the body diode detection circuit may be coupled to an output of the driver circuit and an output of the body diode detection circuit may be coupled to a clock signal input of the trigger circuit 23.
It should be understood that the dead zone detection circuit 22 is not limited to the body diode detection circuit provided in the above embodiment of the present invention, and may also be other types of circuits or electronic devices capable of detecting whether the driving circuit enters the dead zone, which is not described herein.
In a specific implementation, the trigger circuit 23 may be a D flip-flop. When the flip-flop 23 is a D flip-flop, a data signal input terminal of the D flip-flop may be coupled to the output terminal of the inverter circuit 21, a clock signal input terminal of the D flip-flop is coupled to the output terminal of the dead zone detection circuit 22, and an output terminal of the D flip-flop is coupled to the second input terminal of the nor gate 24 and the first input terminal of the nand gate 25.
In the embodiment of the present invention, when the dead-band detection circuit 22 outputs a rising edge, the D flip-flop outputs the input signal of the data signal input terminal, that is, the output signal of the output terminal of the inverter circuit 21 to the second input terminal of the nor gate 24 and the first input terminal of the nand gate 25.
In a specific implementation, the inverter circuit 21 may be an inverter, or may be another circuit or component capable of inverting the input signal.
In a specific implementation, the filter shaping circuit 14 may include: inductor L1, first resistor R1, capacitor C1 and second resistor R2.
In an embodiment of the present invention, a first terminal of the inductor L1 may be coupled to the output terminal of the dead-time control circuit, and a second terminal of the inductor L1 may be coupled to a first terminal of the first resistor R1; a first terminal of the first resistor R1 may be coupled to the second terminal of the inductor L1, and a second terminal of the first resistor R1 may be coupled to the first terminal of the capacitor C1; a first terminal of the capacitor C1 may be coupled to a second terminal of the first resistor R1, and a second terminal of the capacitor C1 may be coupled to ground; a first terminal of the second resistor R2 may be coupled to a first terminal of the capacitor C1, and a second terminal of the second resistor R2 may be coupled to a second terminal of the capacitor C1.
In practical applications, the inductor L1 and the first resistor R1 may shape an output signal at an output terminal of the driving circuit, and the capacitor C1 and the second resistor R2 may filter the shaped signal. It is understood that other filter shaping circuits may be used to replace the filter shaping circuit provided in the embodiment of the present invention, as long as the output signal of the output terminal of the driving circuit can be shaped, which is not described in detail herein.
Referring to fig. 3, an operation timing diagram of the synchronous Buck switching power supply circuit provided in the above embodiment of the present invention is shown. The working principle and flow of the synchronous Buck switching power supply circuit provided in the above embodiment of the present invention are described below with reference to fig. 1 to 3.
At time t0, when the voltage amplitude of the PWM wave output by the PWM wave generating circuit is ground, the first signal output terminal CLK _1 of the dead time control circuit outputs the low level signal CLK _1, and the second signal output terminal CLK _2 of the dead time control circuit outputs the low level signal CLK _2, at this time, the PMOS transistor is in the on state, and the NMOS transistor is in the off state. The output end of the driving circuit outputs a signal SW with high level.
At time t1, the voltage amplitude of the PWM wave output by the PWM generating circuit jumps from ground to high level, at this time, the level of the signal CLK _1 output by the first signal output terminal CLK _1 of the dead time control circuit gradually switches from low level to high level, and the low level signal CLK _2 is still output by the second signal output terminal CLK _2 of the dead time control circuit. The output signal SW of the output terminal of the driving circuit is high level.
After the level of a signal CLK _1 output by a first signal output end CLK _1 of the dead time control circuit is switched to a high level, at the moment, the PMOS tube is in a cut-off state, the NMOS tube is still in a cut-off state, and the driving circuit enters a dead time state. When the drive circuit enters the dead zone state, the level of the output signal SW of the output terminal of the drive circuit is switched from a high level to a negative level. The negative level output by the driving circuit is the dead zone identification signal.
The dead time control circuit controls the level of the output signal CLK _2 of the second signal output terminal CLK _2 to be switched from a low level to a high level after receiving the dead time identification signal.
At time t2, the level of the signal CLK _1 output by the first signal output terminal CLK _1 of the dead time control circuit is high, and the level of the signal CLK _2 output by the second signal output terminal CLK _2 is switched to high, at this time, the PMOS transistor is in an off state, and the NMOS transistor is in a conducting state, so that the driving circuit is separated from the dead time state.
At time t3, the level of the signal CLK _1 output by the first signal output terminal CLK _1 of the dead time control circuit is high, the level of the signal CLK _2 output by the second signal output terminal CLK _2 is also high, at this time, the NMOS transistor is in a conducting state, the PMOS transistor is in a blocking state, and the output signal SW of the output terminal of the driving circuit is switched from a negative level to ground.
At time t1 to time t2, the drive circuit is in the dead zone state.
With continued reference to fig. 3, accordingly, when the voltage amplitude of the PWM wave output from the PWM wave generating circuit jumps from the high level to the ground, the level of the second signal output terminal CLK _2 of the dead time control circuit output signal CLK _2 gradually switches from the high level to the low level, and the level of the first signal output terminal CLK _1 of the dead time control circuit output signal CLK _1 is the high level.
When the level of the signal CLK _2 output by the second signal output end CLK _2 of the dead time control circuit is switched to a low level, both the PMOS transistor and the NMOS transistor are in a cut-off state, and at the moment, the driving circuit enters a dead time state. The output of the drive circuit outputs a signal SW switched from ground to a negative level.
The dead time control circuit controls the level of the first signal output end CLK _1 and the output signal CLK _1 to be switched from high level to low level, so that the PMOS tube is conducted. After the PMOS tube is conducted, the output end output signal SW of the driving circuit is switched from a negative level to a high level, so that the dead zone state is separated.
Therefore, when the dead zone time control circuit detects the dead zone identification signal output by the output end of the driving circuit, the dead zone time control circuit controls the conduction of the upper MOS tube and the lower MOS tube in the driving circuit which are in the cut-off state firstly, so that the driving circuit is separated from the dead zone quickly, and the dead zone time of the synchronous Buck switching power supply circuit can be automatically adjusted. Since the dead time of the synchronous Buck switching power supply circuit is reduced, the power consumption of the synchronous Buck switching power supply circuit is reduced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (8)

1. A synchronous Buck switching power supply circuit, comprising: PWM ripples generating circuit, dead time control circuit, drive circuit and filter shaping circuit, wherein:
the output end of the PWM wave generating circuit is coupled with the PWM wave input end of the dead time control circuit;
the driving circuit comprises an upper MOS tube and a lower MOS tube, wherein the grid electrode of the upper MOS tube is coupled with a first signal output end of the dead time control circuit, and the grid electrode of the lower MOS tube is coupled with a second signal output end of the dead time control circuit; the driving circuit is suitable for outputting a dead zone identification signal when the upper MOS tube and the lower MOS tube are both cut off;
the dead time control circuit is coupled with the output end of the drive circuit at the feedback signal input end and is suitable for controlling the conduction of the upper MOS tube and the lower MOS tube in the first-in cut-off state when receiving a dead time identification signal output by the output end of the drive circuit;
and the input end of the filter shaping circuit is coupled with the output end of the drive circuit and is suitable for carrying out filter shaping processing on the output signal of the output end of the drive circuit.
2. The synchronous Buck switching power supply circuit of claim 1, wherein the dead-time control circuit comprises: inverting circuit, dead zone detection circuit, flip-flop circuit, NOR gate and NAND gate, wherein:
the input end of the inverter circuit is coupled with the output end of the PWM wave generating circuit, and the output end of the inverter circuit is coupled with the data signal input end of the trigger circuit;
the input end of the dead zone detection circuit is coupled with the output end of the driving circuit, the output end of the dead zone detection circuit is coupled with the clock signal input end of the trigger circuit, and the dead zone detection circuit is suitable for generating a trigger signal and outputting the trigger signal to the clock signal input end of the trigger circuit when the dead zone time of the driving circuit is detected;
the output end of the trigger circuit is coupled with the second input end of the nor gate and the first input end of the nand gate, and the trigger circuit is suitable for outputting the input signal of the data signal input end when the trigger signal input by the clock signal input end is detected;
the first input end of the NOR gate is coupled with the output end of the inverter circuit, and the output end of the NOR gate is coupled with the grid electrode of the upper MOS tube of the driving circuit;
and the second input end of the NAND gate is coupled with the output end of the inverter circuit, and the output end of the NAND gate is coupled with the grid electrode of the lower MOS tube of the driving circuit.
3. The synchronous Buck switching power supply circuit of claim 2, wherein the dead-time detection circuit is a body diode detection circuit; the input end of the body diode detection circuit is coupled with the output end of the driving circuit, and the output end of the body diode detection circuit is coupled with the clock signal input end of the trigger circuit.
4. The synchronous Buck switching power supply circuit of claim 2, wherein the trigger circuit is a D-flip-flop.
5. The synchronous Buck switching power supply circuit of claim 4, wherein said D flip-flop has a data signal input coupled to an input of said inverter circuit, a clock signal input coupled to an output of said dead-time detection circuit, and an output coupled to a second input of said NOR gate and a first input of said NAND gate.
6. The synchronous Buck switching power supply circuit of claim 5, wherein the inverting circuit is an inverter.
7. The synchronous Buck switching power supply circuit of claim 1, wherein the upper MOS transistor is a PMOS transistor, and the lower MOS transistor is an NMOS transistor, wherein:
the source electrode of the PMOS tube inputs a high-level signal, the drain electrode of the PMOS tube is coupled with the drain electrode of the NMOS tube, and the grid electrode of the PMOS tube is coupled with the first signal output end of the dead time control circuit;
and the source electrode of the NMOS tube is coupled with the ground, and the grid electrode of the NMOS tube is coupled with the second signal output end of the dead time control circuit.
8. The synchronous Buck switching power supply circuit of claim 1, wherein the filter shaping circuit comprises: inductance, first resistance, electric capacity and second resistance, wherein:
the first end of the inductor is coupled with the output end of the dead time control circuit, and the second end of the inductor is coupled with the first end of the first resistor;
the second end of the first resistor is coupled with the first end of the capacitor;
the second end of the capacitor is coupled with the ground;
and the first end of the second resistor is coupled with the first end of the capacitor, and the second end of the second resistor is coupled with the second end of the capacitor.
CN201811002259.4A 2018-08-30 2018-08-30 Synchronous Buck switching power supply circuit Pending CN110875685A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102170228A (en) * 2011-04-29 2011-08-31 电子科技大学 A dead time control circuit used in a DC-DC converter
CN104170229A (en) * 2012-08-27 2014-11-26 富士电机株式会社 Switching power supply apparatus
CN104270008A (en) * 2014-09-19 2015-01-07 成都芯源***有限公司 Resonant switching converter, control circuit and control method for automatic dead time adjustment of resonant switching converter
CN104410300A (en) * 2014-11-24 2015-03-11 深圳创维－Rgb电子有限公司 Synchronous rectification drive circuit and television set
WO2017112322A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Digitally controlled zero voltage switching
CN107707121A (en) * 2017-11-20 2018-02-16 电子科技大学 Switch converters adaptive dead zone generation circuit based on body diode conduction detection

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102170228A (en) * 2011-04-29 2011-08-31 电子科技大学 A dead time control circuit used in a DC-DC converter
CN104170229A (en) * 2012-08-27 2014-11-26 富士电机株式会社 Switching power supply apparatus
CN104270008A (en) * 2014-09-19 2015-01-07 成都芯源***有限公司 Resonant switching converter, control circuit and control method for automatic dead time adjustment of resonant switching converter
CN104410300A (en) * 2014-11-24 2015-03-11 深圳创维－Rgb电子有限公司 Synchronous rectification drive circuit and television set
WO2017112322A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Digitally controlled zero voltage switching
CN107707121A (en) * 2017-11-20 2018-02-16 电子科技大学 Switch converters adaptive dead zone generation circuit based on body diode conduction detection

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