CN110875232A

CN110875232A - Wafer level packaging method and packaging structure

Info

Publication number: CN110875232A
Application number: CN201811028258.7A
Authority: CN
Inventors: 罗海龙; 克里夫·德劳利
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2018-09-04
Filing date: 2018-09-04
Publication date: 2020-03-10

Abstract

A wafer level packaging method and a packaging structure are provided, the method comprises the following steps: providing a device wafer; providing a bearing substrate, temporarily bonding a plurality of chips on the bearing substrate, wherein the chips are provided with bonding surfaces facing the bearing substrate, the chips to be shielded in the plurality of chips are first chips, and the number of the first chips is one or more; forming a packaging layer covering the chip on the bearing substrate; after the packaging layer is formed, removing the bearing substrate; the bonding surface and the device wafer are oppositely arranged, and the bonding of the device wafer and the chip is realized by adopting a low-temperature fusion bonding process; forming a trench in the encapsulation layer surrounding the first chip; forming a conductive material in the groove and on the surface of the packaging layer; the conductive material in the groove is a conductive side wall; the conductive material on the surface of the packaging layer above the first chip is a conductive layer and is used for forming a shielding shell with the conductive side wall. The invention can reduce the volume and the thickness of the packaging structure, and the bonding strength between the chip and the device wafer is higher.

Description

Wafer level packaging method and packaging structure

Technical Field

The present invention relates to the field of semiconductor manufacturing, and in particular, to a wafer level package method and a package structure.

Background

With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional Package (3D), System In Package (SiP), and the like.

At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts Wafer Level Package System In Package (WLPSiP), and compared with the conventional System packaging, the Wafer Level System packaging completes a packaging integration process on a Wafer, so that the Wafer Level System packaging has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.

Because the bare chip is easily affected by an external magnetic field in the use process of the integrated circuit packaging structure, and the performance is not stable enough, in the packaging process, the shielding structure is usually arranged in the packaging structure to reduce the interference of the external magnetic field, however, the integrated circuit with the shielding function has the problems of large volume and thickness, and the packaging yield of the current integrated circuit is also low.

Disclosure of Invention

The invention provides a wafer level packaging method and a packaging structure, which can reduce the volume and thickness of the formed packaging structure and improve the packaging yield.

To solve the above problems, the present invention provides a packaging method, comprising: providing a device wafer; providing a bearing substrate, temporarily bonding a plurality of chips on the bearing substrate, wherein the chips are provided with bonding surfaces facing the bearing substrate, the chips to be shielded in the plurality of chips are first chips, and the number of the first chips is one or more; forming an encapsulation layer covering the plurality of chips on the bearing substrate; after the packaging layer is formed, removing the bearing substrate; after the bearing substrate is removed, the bonding surface and the device wafer are oppositely arranged, and the bonding of the device wafer and the chip is realized by adopting a low-temperature fusion bonding process; forming a trench in the encapsulation layer surrounding each of the first chips after the low temperature fusion bonding process; forming a conductive material in the groove and on the surface of the packaging layer above the first chip; the conductive material in the groove is a conductive side wall; the conductive material on the surface of the packaging layer above the first chip is a conductive layer and is used for forming a shielding shell with the conductive side wall.

Correspondingly, the invention also provides a packaging structure, which comprises: a device wafer; the device wafer is bonded with a plurality of chips, wherein the chips to be shielded in the plurality of chips are first chips, the number of the first chips is one or more, and the plurality of chips are bonded with the device wafer through a low-temperature fusion bonding process; a packaging layer located on the device wafer and covering the plurality of chips; conductive sidewalls in the encapsulation layer and surrounding each of the first chips; and the conducting layer is positioned on the surface of the packaging layer above the first chip and is used for being connected with the conducting side wall to form a shielding shell.

Compared with the prior art, the technical scheme of the invention has the following advantages:

the device wafer and the plurality of chips are bonded in a fusion bonding mode, and the device wafer and the chips are bonded in a covalent bond bonding mode through a fusion bonding process, so that the bonding strength of the device wafer and the chips is remarkably improved, and the packaging yield is further improved; in addition, the chips to be shielded in the plurality of chips are first chips, after grooves surrounding each first chip are formed in the packaging layer, the grooves are filled with conductive materials to form conductive side walls, the conductive side walls are arranged around the side faces of the first chips, a conductive layer connected with the conductive side walls is formed on the surface of the packaging layer above the first chips, the conductive layer and the conductive side walls form a shielding shell, and the shielding shell is used for protecting the first chips so as to reduce the influence of an external magnetic field on the first chips. The anti-interference effect of the first chip is favorably ensured by the shielding shell.

Drawings

Fig. 1 to 13 are schematic structural diagrams corresponding to steps of a first embodiment of a wafer level packaging method according to the present invention;

fig. 14 to 15 are schematic structural diagrams corresponding to the steps of the second embodiment of the wafer level packaging method of the present invention.

Detailed Description

As known from the background art, the integrated circuit with the shielding function has the problems of large volume and thickness, and the packaging yield of the integrated circuit is low at present. The reason for this analysis is:

in order to reduce the external magnetic field interference, in the prior art, a metal shell is assembled on a die in a package structure to shield the external magnetic field, however, part of the die in the package structure is usually easily interfered by the external magnetic field, and the metal shell shields all the dies by the magnetic field and does not protect the dies to be shielded in a targeted manner, so that the size of the metal shell is usually large, which results in the increase of the volume and thickness of the package structure; moreover, the device wafer and the bare chip in the package structure are usually physically connected through an adhesive layer (such as an adhesive film or a dry film), but the adhesive layer has poor temperature resistance, and when the process temperature in the subsequent process is too high, the adhesive layer is easily failed, so that the adhesiveness of the adhesive layer is reduced, and even the device wafer and the bare chip are peeled off, thereby seriously affecting the package yield.

In order to solve the technical problem, after a groove surrounding each first chip to be shielded is formed in a packaging layer, a conductive material is filled in the groove to form a conductive side wall, the conductive side wall is arranged around the side face of the first chip, a conductive layer connected with the conductive side wall is formed on the surface of the packaging layer above the first chip, the conductive layer and the conductive side wall form a shielding shell, and the shielding shell is used for protecting the first chip so as to reduce the influence of an external magnetic field on the first chip; moreover, the device wafer and the plurality of chips are bonded in a fusion bonding mode, the bonding strength between the device wafer and the chips is high, and correspondingly, the formed packaging structure can keep good reliability on the whole, so that the anti-interference effect of the shielding shell on the first chip is guaranteed.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 to 13 are schematic structural diagrams corresponding to steps of the first embodiment of the wafer level packaging method of the present invention.

Referring to fig. 1, a device Wafer (CMOS Wafer)100 is provided.

In this embodiment, the packaging method is used to implement wafer level system packaging, and the device wafer 100 is used to bond with a chip to be integrated in a subsequent process.

The device wafer 100 is a wafer on which device fabrication is completed. In this embodiment, the substrate of the device wafer 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

A plurality of second chips 110 are formed in the device wafer 100. It should be noted that the device wafer 100 may be manufactured by using an integrated circuit manufacturing technology, for example, devices such as an NMOS device and a PMOS device are formed on a substrate through deposition, etching, and the like, and structures such as a dielectric layer, a metal interconnection structure, and a Pad (Pad) electrically connected to the metal interconnection structure are formed on the devices, so that the plurality of second chips 110 are formed in the device wafer 100.

It should be noted that, for convenience of illustration, the device wafer 100 of the present embodiment is described by taking three second chips 110 as an example. The number of the second chips 110 is not limited to three.

In this embodiment, the surface of the device wafer 100 on which the second chips 110 are formed is a wafer front side 101, and a surface facing away from the wafer front side 101 is a wafer back side 102. Wherein the wafer backside 102 refers to the bottom surface of the substrate away from the device wafer 100 pads.

Referring to fig. 2, a carrier substrate 10 is provided, a plurality of chips 200 are temporarily bonded on the carrier substrate 10, the chips 200 have bonding surfaces (not labeled) facing the carrier substrate 10, a chip to be shielded in the plurality of chips 200 is a first chip 205, and the number of the first chips 205 is one or more.

The carrier substrate 10 is used for supporting the plurality of chips 200, so that the subsequent process is facilitated, and the operability of the subsequent process is improved; and also facilitates the subsequent separation of the chip 200 and the carrier substrate 10 by means of Temporary Bonding (Temporary Bonding).

In this embodiment, the Carrier substrate 10 is a Carrier Wafer (Carrier Wafer). Specifically, the carrier substrate 10 may be a semiconductor substrate (e.g., a silicon substrate), an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, a metal wafer, an organic plastic wafer, an inorganic oxide wafer, or a ceramic material wafer.

In this embodiment, the chip front surface 201 is attached to the carrier substrate 10 by an adhesive layer 15.

The adhesive layer 15 is used to temporarily bond the chip 200 and the carrier substrate 10, so as to facilitate the subsequent separation of the chip 200 and the carrier substrate 10. Specifically, the adhesive layer 15 is one or both of a Die Attach Film (DAF) and a Dry Film (Dry Film).

The dry film is a sticky photoresist film used for semiconductor chip packaging or printed circuit board manufacturing, and the dry film photoresist is manufactured by coating solvent-free photoresist on a polyester film base and then coating a polyethylene film; when the dry film photoresist is used, the polyethylene film is uncovered, the solvent-free photoresist is pressed on the base plate, and a pattern can be formed in the dry film photoresist through exposure and development treatment.

The adhesive film is an ultra-thin film adhesive used for connecting a semiconductor chip and a packaging substrate and connecting the chip and the chip in a semiconductor packaging process, has high reliability and convenient process performance, and is beneficial to realizing the lamination and thinning of the semiconductor packaging.

It should be noted that, in other embodiments, the bonding surface of the chip may also be temporarily bonded to the carrier substrate through electrostatic bonding. The electrostatic bonding technology is a method for realizing bonding without any adhesive, in the bonding process, a chip to be bonded and a bearing substrate are respectively connected with different electrodes, electric charges are formed on the surfaces of the chip and the bearing substrate under the action of voltage, and the electric charges on the surfaces of the chip and the bearing substrate are different, so that a larger electrostatic attraction is generated in the bonding process of the chip and the bearing substrate, and the physical connection of the chip and the bearing substrate is realized.

The chips 200 are used as chips to be integrated in a wafer level system package, and the chips 200 may be manufactured by using an integrated circuit manufacturing technology. The wafer level packaging method of the present embodiment is used to realize heterogeneous integration, and thus the plurality of chips 200 are chips made of silicon wafers. In other embodiments, the second chip may also be a chip formed by other materials.

The chip 200 may be one or more of an active element, a passive element, a micro electro mechanical system, an optical element, and the like. Specifically, the chip 200 may be a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip. In other embodiments, the chip may also be other functional chips.

For convenience of illustration, the present embodiment takes the number of the chips 200 as three as an example for description. The number of the chips 200 is not limited to three.

It should be further noted that, in the plurality of chips 200, the first chip 205 is relatively susceptible to the influence of an external magnetic field, and the first chip 205 is a chip to be shielded. In this embodiment, the number of the first chips 205 is taken as an example. In other embodiments, the number of the first chips may also be multiple.

In this embodiment, a bonding pad 210 is formed in the chip 200, a surface of the chip 200 close to the bonding pad 210 is a chip front surface 201, and a surface opposite to the chip front surface 201 is a chip back surface 202. Specifically, the bonding Pad 210 may be a wire bonding Pad (Bond Pad), and the bonding Pad 210 is used for electrically connecting the chip 200 to other semiconductor devices.

In this embodiment, in a subsequent process, the chip front surface 201 of the chip 200 is bonded to the wafer front surface 101 (shown in fig. 1) of the device wafer 100 (shown in fig. 1), so that the bonding surface of the chip 200 is the chip front surface 201, and the chip front surface 201 is temporarily bonded to the carrier substrate 10. In other embodiments, the bonding surface of the chip may also be the back surface of the chip according to actual process requirements.

Referring to fig. 3, an encapsulation layer 400 covering the plurality of chips 200 is formed on the carrier substrate 10.

The packaging layer 400 is used for protecting the plurality of chips 200, and can play a role in sealing and moisture protection, and can also play a role in protecting the device wafer 100 after the chips 200 and the device wafer 100 (shown in fig. 1) are bonded in the following, so that the probability that the second chip 110 (shown in fig. 1) and the chips 200 are damaged, polluted or oxidized is reduced, and further, the performance of the obtained packaging structure is favorably optimized; moreover, the encapsulation layer 400 covers the plurality of chips 200, and can also support the plurality of chips 200, thereby improving the operability of the subsequent process.

In this embodiment, the material of the package layer 400 is a polymer or a dielectric, and the package layer 400 also serves to insulate the shield case formed later from the first chip 205.

Specifically, the encapsulation layer 400 is formed by an injection molding process using a liquid molding compound or a solid molding compound. The filling performance of the injection molding process is good, so that the molding compound can be filled among the plurality of chips 200 well, thereby improving the packaging effect of the packaging layer 400 on the chips 200. In other embodiments, other processes may be used to form the encapsulation layer.

In this embodiment, the material of the encapsulation layer 400 is Epoxy resin (Epoxy). Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, low cost and the like, and is widely used as a packaging material for electronic devices and integrated circuits. In other embodiments, the material of the encapsulation layer may also be a thermosetting material such as polyimide or silica gel, or the encapsulation layer may also be a dielectric material such as aluminum oxide or aluminum nitride.

Accordingly, referring to fig. 4, after the package layer 400 is formed, a De-bonding process is performed on the plurality of chips 200 and the carrier wafer 10 (shown in fig. 3), and the carrier wafer 10 and the adhesive layer 15 (shown in fig. 3) are removed to expose the chip front surface 201.

Through the bonding-releasing treatment, the packaging layer 400 is exposed out of the front surface 201 of the chip, so that a process foundation is provided for a subsequent fusion bonding process

Specifically, during the debonding process, the carrier wafer 10 may be separated from the chips 200 by chemical or mechanical peeling. In other embodiments, the carrier wafer may be separated from the chips in other ways.

With continuing reference to fig. 1 and with combined reference to fig. 5 to 9, after the debonding process, the bonding surface (not labeled) and the device wafer 100 are disposed opposite to each other, and a low-temperature fusion bonding process is used to bond the device wafer 100 and the chip 200.

The fusion bonding is a process for completing bonding by mainly utilizing interface chemical force, so that the reliability of the bonding process is improved, the bonding strength of the device wafer 100 and the chip 200 is further improved, the subsequent process has small influence on the bonding strength, and the packaging yield is correspondingly improved.

Moreover, since the encapsulation layer 400 is also exposed to the process environment of the fusion bonding process, the process temperature of the annealing treatment in the fusion bonding process is reasonably reduced by adopting the low-temperature fusion bonding process, so that the influence of the fusion bonding process on the encapsulation layer 400 is reduced.

Correspondingly, for the low-temperature fusion bonding process, the packaging method further comprises the following steps:

referring to fig. 1 and 5 in combination, a first oxide layer 150 (shown in fig. 1) is formed on the surface of the device wafer 100 (shown in fig. 1); a second oxide layer 250 is formed on the bonding surface (not labeled) (as shown in fig. 5).

The first oxide layer 150, the second oxide layer 250 and a Bonding layer used as a subsequent Fusion Bonding (Fusion Bonding) process are used to realize the physical connection between the device wafer 100 and the chip 200. In the process of the fusion bonding, unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 150 and the second oxide layer 250, and covalent bonding can be achieved, so that through the fusion bonding process, the contact surfaces of the first oxide layer 150 and the second oxide layer 250 are bonded in a covalent bonding manner, and the first oxide layer 150 and the second oxide layer 250 have high bonding strength, so that the reliability of the bonding process is improved, and the bonding strength of the device wafer 100 and the chip 200 is further improved.

In this embodiment, the first oxide layer 150 is made of silicon oxide. By selecting the silicon oxide material, in the subsequent fusion bonding process, the device wafer 100 and the chip to be integrated can be bonded by a Si-O-Si covalent bond, and the bonding energy of the Si-O bond is larger, so that the bonding strength of the device wafer 100 and the chip to be integrated is further improved; in addition, the silicon oxide material has higher process compatibility, and the silicon oxide is a material which is commonly used in the process and has lower cost, so that the process difficulty and the process cost are favorably reduced by selecting the silicon oxide material, and the performance influence on the formed packaging structure is favorably reduced. In other embodiments, the first oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide.

Specifically, the process of forming the first oxide layer 150 may be an Atomic Layer Deposition (ALD) process. The atomic layer deposition process refers to a deposition process in which a vapor phase precursor is alternately pulsed into a reaction chamber to chemisorb and cause a surface reaction on a substrate to be deposited. By adopting an atomic layer deposition process, the first oxide layer 150 is formed on the surface of the device wafer 100 in an atomic layer manner, so that the uniformity of the deposition rate, the thickness uniformity of the first oxide layer 150, and the structural uniformity in the first oxide layer 150 are improved, and the first oxide layer 150 has good coverage capability; in addition, the process temperature of the ald process is usually lower, so that the Thermal Budget (Thermal Budget) is also reduced, and the probability of Wafer deformation (Wafer deformation) and device performance deviation is reduced.

In other embodiments, the process of forming the first oxide layer may also be a Low Pressure Chemical Vapor Deposition (LPCVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a Physical Vapor Deposition (PVD) process, or a Laser pulse Deposition (PLD) process according to the material of the first oxide layer.

In this embodiment, the chip 200 is bonded to the wafer front side 101 of the device wafer 100, so the first oxide layer 150 is formed on the wafer front side 101, and the first oxide layer 150 covers the wafer front side 101 entirely.

By means of enabling the first oxidation layer 150 to completely cover the front surface 101 of the wafer, after the device wafer 100 and the chip 200 are bonded, the probability of generating a gap between the device wafer 100 and the chip 200 can be effectively reduced, and the packaging layer can better isolate air and moisture, so that the packaging effect is improved, and the performance of the obtained packaging structure is further facilitated to be optimized; moreover, the chip to be shielded in the chip to be integrated is the first chip, and then the conductive sidewall surrounding each first chip is formed in the packaging layer, so that the first oxide layer 150 covers the front surface 101 of the wafer completely, so that the first oxide layer 150 plays an insulating role on the second chip 110 and the conductive sidewall, and the conductive sidewall is prevented from affecting the normal operation of the second chip 110.

In this embodiment, the material of the second oxide layer 250 is the same as the material of the first oxide layer 150 (shown in fig. 1), so that covalent bonding can be better achieved in a subsequent fusion bonding process, which is beneficial to further improving the bonding strength between the second oxide layer 250 and the first oxide layer 150. Specifically, the second oxide layer 250 is formed by an atomic layer deposition process, and the material of the second oxide layer 250 is silicon oxide.

In other embodiments, the second oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide, and the process for forming the second oxide layer may also be a low pressure chemical vapor deposition process, a metal organic chemical vapor deposition process, a physical vapor deposition process, or a laser pulse deposition process.

For a detailed description of the second oxide layer 250, reference may be made to the foregoing description of the first oxide layer 150, and this embodiment is not repeated herein.

In this embodiment, the bonding surface of the chip 200 is the chip front surface 201, and thus the second oxide layer 250 covers the chip front surface 201.

In this embodiment, the second oxide layer 250 further covers the encapsulation layer 400. By covering the second oxide layer 250 with the encapsulation layer 400, the difficulty of the process for forming the second oxide layer 250 can be reduced, which is beneficial to simplifying the process steps and reducing the process cost; moreover, the package layer 400 may contact with the second oxide layer 250 to achieve sealing, and after the device wafer 100 and the chip 200 are bonded, the probability of generating a gap between the device wafer 100 and the chip 200 may be effectively reduced, and air and moisture may be better isolated, so as to improve the package effect, and further facilitate optimizing the performance of the obtained package structure; in addition, a conductive sidewall surrounding the first chip 205 is subsequently formed in the package layer 400, and the second oxide layer 250 covers a surface of the package layer 400 close to the chip front surface 201, so that the second oxide layer 250 insulates the second chip 110 and the conductive sidewall, thereby preventing the conductive sidewall from affecting the normal operation of the second chip 110.

In other embodiments, the second oxide layer may be formed on the bonding surface before the plurality of chips are temporarily bonded on the carrier substrate; correspondingly, in the step of temporarily bonding the plurality of chips on the bearing substrate, the second oxide layer is temporarily bonded on the bearing substrate.

Therefore, referring to fig. 6 to 9 in combination, the bonding between the device wafer 100 and the chip 200 is achieved through the first oxide layer 150 and the second oxide layer 250 by using a low-temperature fusion bonding process.

Specifically, referring to fig. 6 and 7 in combination, the steps of the low temperature fusion bonding process include: and performing plasma activation treatment 130 on the surface of the first oxide layer 150 (shown in fig. 6) and the surface of the second oxide layer 250 (shown in fig. 7).

On one hand, the contaminants, impurities, and the like on the surfaces of the first oxide layer 150 and the second oxide layer 250 are made into a gaseous state by the plasma activation treatment 130, and are exhausted by a vacuum pump of a plasma system, thereby performing a function of removing the contaminants and impurities, for example, metal contaminants and organic contaminants can be removed well. On the other hand, the plasma of the plasma activation treatment 130 collides with the surfaces of the first oxide layer 150 and the second oxide layer 250, and energizes unstable non-bridging oxygen atoms to move the oxygen atoms away from the original bonded atoms, thereby providing a good basis for the subsequent formation of covalent bonds at the contact surfaces of the first oxide layer 150 and the second oxide layer 250.

The reactive gas used in the plasma activation treatment 130 may include Ar, N₂、O₂And SF₆One or more of (a). In this embodiment, the reaction gas used for the plasma activation treatment 130 is O₂That is, the plasma activation treatment 130 is an oxygen plasma activation treatment.

The rf power of the plasma activation treatment 130 is not too low or too high. In the plasma activation process 130, electrons are accelerated by the radio frequency electric field generated by the radio frequency power source, and each electron collides with a reaction gas molecule to transfer kinetic energy, so that each reaction gas molecule is ionized to generate plasma.

If the rf power is too low, the reaction gas is difficult to be converted into plasma, which is likely to cause insufficient plasma and poor plasma stability, thereby reducing the effect of the plasma activation treatment 130, and further reducing the bonding strength between the first oxide layer 150 and the second oxide layer 250; if the rf power is too high, the kinetic energy obtained after the reaction gas is turned into plasma is too high, the bombardment effect on the first oxide layer 150 and the second oxide layer 250 is correspondingly too strong, so that the surfaces of the first oxide layer 150 and the second oxide layer 250 are easily damaged, Micro-defects (Micro-defects) are formed on the surfaces of the first oxide layer 150 and the second oxide layer 250, an annealing cavity is easily generated after subsequent annealing treatment, the bonding strength between the subsequent first oxide layer 150 and the subsequent second oxide layer 250 is easily reduced, and the rf power also consumes too much energy, thereby increasing the process cost. For this reason, in this embodiment, the rf power of the plasma activation process 130 is 20W to 200W.

The process pressure of the plasma activation treatment 130 should not be too low or too high. The process pressure affects the radio frequency power, the greater the process pressure, the shorter the mean free path of the plasma, and the greater the probability of collision between the plasmas, thereby causing the effect of the plasma activation processing 130 to be poor, and correspondingly, the higher the radio frequency power required for ensuring the effect of the plasma activation processing 130; in addition, when the process pressure is too small, the stability of the plasma is easily lowered, and accordingly, the higher the rf power required to suppress the plasma from being unstable. To this end, in this embodiment, the process pressure is adjusted to a matching value range according to the rf power of the plasma activation process 130. Specifically, the process pressure of the plasma activation treatment 130 is 0.1mBar to 10 mBar.

The processing time of the plasma activation processing 130 is not preferably too short, nor too long. If the processing time is too short, the effect of the plasma activation processing 130 is correspondingly deteriorated under the condition of certain radio frequency power and the flow rate of the reaction gas, thereby causing the bonding strength between the first oxide layer 150 and the second oxide layer 250 to be reduced; if the treatment time is too long, the surface of the first oxide layer 150 and the second oxide layer 250 is easily damaged, so that micro defects are formed on the surface of the first oxide layer 150 and the second oxide layer 250, and the treatment time is too long, so that an excessive amount of hydroxyl groups is generated, and an excessive amount of by-products (H) is easily generated after the subsequent annealing treatment₂O and H₂Etc.), thereby causing the generation of annealing voids, which in turn tends to decrease the bonding strength between the first oxide layer 150 and the second oxide layer 250, and further, the process cost increases due to the long process time. For this reason, in the present embodiment, the treatment time of the plasma activation treatment 130 is 0.1 minute to 10 minutes.

In this embodiment, the rf power, the process pressure, and the processing time of the plasma activation processing 130 are set within a reasonable range and cooperate with each other, so that the activation effect on the first oxide layer 150 and the second oxide layer 250 is improved while the processing efficiency and stability are improved and the process cost is reduced.

In this embodiment, the step of the fusion bonding process further includes: after the plasma activation treatment 130, performing deionized water cleaning treatment on the surfaces of the first oxide layer 150 and the second oxide layer 250; after the deionized water pre-cleaning treatment, the surfaces of the first oxide layer 150 and the second oxide layer 250 are dried.

Through the deionized water cleaning treatment and the drying treatment, the surface quality of the first oxide layer 150 and the second oxide layer 250 is improved, and thus the bonding strength of the first oxide layer 150 and the second oxide layer 250 is improved.

Specifically, the surfaces of the first oxide layer 150 and the second oxide layer 250 are rinsed with deionized water, thereby completing the deionized water cleaning process; after the deionized water cleaning treatment, N is adopted₂The first and second oxide layers 150 and 250 are blow-dried, thereby completing the drying process.

Referring to fig. 8, in this embodiment, the step of the fusion bonding process further includes: after the drying process, the second oxide layer 250 and the first oxide layer 150 are oppositely disposed and attached, and a bonding pressure is applied to the device wafer 100 and the plurality of chips 200 to perform a pre-bonding process 140.

After the plasma activation treatment 130, unsaturated bonded Si atoms are formed on the surfaces of the first oxide layer 150 and the second oxide layer 250, and thus the first oxide layer 150 and the second oxide layer 250 are bonded by interfacial chemical bonding through the pre-bonding treatment 140.

Specifically, bonding pressure is applied to the wafer back side 102 of the device wafer 100 and the surface of the encapsulation layer 400 facing away from the chip front side 201 to perform the pre-bonding process 140. In the process of the pre-bonding treatment 140, the encapsulation layer 400 is used to effectively support the plurality of chips 200, so as to improve the operability of the pre-bonding treatment 140, and by applying a bonding pressure to the encapsulation layer 400, it is beneficial to improve the stress uniformity of the plurality of chips 200, and in addition, compared with a scheme of directly applying a bonding pressure to the chips 200, it is beneficial to reduce the damage of the pre-bonding treatment 140 to the chips 200.

It should be noted that, although increasing the bonding pressure of the pre-bonding treatment 140 is beneficial to improving the chemical bond effect and strength at the interface between the first oxide layer 150 and the second oxide layer 250, if the bonding pressure is too high, the device wafer 100, the first oxide layer 150, the second oxide layer 250, the chip 200, and the package layer 400 are easily adversely affected, for example, a problem of deformation occurs. For this reason, in this embodiment, in order to effectively realize the interfacial chemical bond connection between the first oxide layer 150 and the second oxide layer 250 and reduce the process risk, the bonding pressure of the pre-bonding treatment 140 is 1 newton to 20 newton.

It should be noted that the processing time of the pre-bonding process 140 is not short, nor long. The increase of the processing time of the pre-bonding treatment 140 is also beneficial to improving the chemical bond connection effect and strength of the contact surface between the first oxide layer 150 and the second oxide layer 250, so that under the condition of a certain bonding pressure, if the processing time is too short, the problem of poor chemical bond connection effect of the interface between the first oxide layer 150 and the second oxide layer 250 is easily caused; the excessive processing time will cause waste of process time and decrease of efficiency. For this reason, in the present embodiment, in order to improve the process efficiency while the first oxide layer 150 and the second oxide layer 250 effectively achieve the interfacial chemical bond connection, the processing time of the pre-bonding treatment 140 is 1 second to 60 seconds.

In this embodiment, after the second oxide layer 250 and the first oxide layer 150 are oppositely disposed and bonded, the plurality of chips 200 and the plurality of second chips 110 in the device wafer 100 are staggered, that is, the projection of the chips 200 on the device wafer 100 is not overlapped with the second chips 110.

In order to shield the first chip 205, the subsequent steps further include forming a trench surrounding the first chip 205 in the package layer 400, and by staggering the chip 200 and the second chip 110 in the device wafer 100, the difficulty of the process for forming the trench is reduced, and the influence of the process for forming the trench on the second chip 110 corresponding to the first chip 205 is reduced.

In other embodiments, after the second oxide layer and the first oxide layer are oppositely disposed and bonded, the chip and the second chip in the device wafer may be aligned with each other, that is, a projection of the chip on the device wafer coincides with the second chip. Therefore, the subsequently formed shielding shell can also have a shielding effect on the second chip corresponding to the first chip.

Referring to fig. 9 in combination, in this embodiment, the step of the fusion bonding process further includes: after the pre-bonding process 140 (shown in fig. 8), the device wafer 100 and the plurality of chips 200 are annealed.

By the annealing treatment, dehydration condensation reaction occurs between hydroxyl groups on the contact surface of the first oxide layer 150 and the second oxide layer 250, and Si-O-Si covalent bond is formed between the first oxide layer 150 and the second oxide layer 250; since the silicon-oxygen bond has a large bond energy, the bonding strength between the first oxide layer 150 and the second oxide layer 250 is improved.

Wherein, the process temperature of the annealing treatment is not suitable to be too low or too high. If the process temperature is too low, the effect of dehydration condensation reaction is easily reduced, which is not favorable for improving the bonding strength of the first oxide layer 150 and the second oxide layer 250; if the process temperature is too high, the performance of the devices formed in the device wafer 100 and the chips 200 is easily adversely affected, and the high temperature resistance of the encapsulation layer 400 is generally poor, so that the encapsulation layer 400 is also easily adversely affected. For this reason, in this embodiment, the process temperature of the annealing treatment is 200 ℃ to 500 ℃.

The process time of the annealing treatment is not too short or too high. If the process time is too short, it is difficult to sufficiently complete the dehydration condensation reaction, thereby being disadvantageous to improve the bonding strength of the first and second oxide layers 150 and 250; if the process time is too long, the process time is wasted and the efficiency is reduced, and the risk of the process increases when the device wafer 100 and the chips 200 are placed in the annealing environment for a long time. For this reason, in this embodiment, the process time of the annealing treatment is 20 minutes to 200 minutes.

In this embodiment, the process temperature and the process time of the annealing treatment are set within a reasonable range and are matched with each other, so that the bonding strength is improved and the probability of side effects is reduced.

Referring to fig. 10 and 11 in combination, fig. 11 is a top view of fig. 10, after the low temperature fusion bonding process, a trench 410 is formed in the encapsulation layer 400 around each of the first chips 205.

The trench 410 is used for filling a conductive material in a subsequent step to form a conductive sidewall, and the conductive sidewall is used for protecting the first chip 205 and reducing interference of an external magnetic field on the first chip 205.

Specifically, the trench 410 is formed around each first chip 205, so that the trench 410 is filled with a shielding material to form a shielding layer around each first chip 205.

The width d (shown in fig. 11) of the trench 410 is used to define the thickness of the subsequent conductive sidewall. If the width d of the trench 410 is too large, the thickness of the conductive sidewall is too large, which easily increases the thickness and volume of the whole package structure; if the width d of the trench 410 is too small, the thickness of the conductive sidewall is too small, which may easily affect the shielding effect of the conductive sidewall. Therefore, in the present embodiment, the width d of the trench 410 is in the range of 10 to 50 μm.

Typically, the projection of the first chip 205 on the device wafer 100 is rectangular. In this embodiment, a projection of the trench 410 in the package layer 400 on the device wafer 100 is rectangular, that is, a shape of the trench 410 is matched with a shape of the first chip 205, so that the formed shielding structure occupies a smaller volume and has a good shielding effect on the first chip 205.

The sidewall of the trench 410 near the first chip 205 is an inner sidewall (not labeled), and a distance D (as shown in fig. 11) between the inner sidewall and the opposite sidewall of the first chip 205 is used to define a distance between the first chip 205 and the conductive sidewall, that is, the distance D is used to define a thickness of the encapsulation layer 400 between the first chip 205 and the conductive sidewall.

If the distance D is too large, the distance between the trench 410 and the other chips 200 adjacent to the first chip 205 is short, which easily affects the performance of the other chips 200, and when the distance between the conductive sidewall and the first chip 205 is large, the shielding effect of the conductive sidewall on the first chip 205 is also weakened; if the distance D is too small, the thickness of the encapsulation layer 400 between the conductive sidewall and the first chip 205 is small, thereby easily affecting the insulation between the conductive sidewall and the first chip 205. For this reason, in the present embodiment, the distance D between the inner sidewall and the opposite sidewall of the first chip 205 is in the range of 5 to 100 micrometers.

Specifically, the trench 410 may be formed by etching the encapsulation layer 400 through a laser etching process. The laser etching process has high precision, and the forming position of the trench 410 and the size of the trench 410 can be determined more precisely.

As shown in fig. 10, in the step of forming the trench 410, after the encapsulation layer 400 is etched, the second oxide layer 250 and the first oxide layer 150 are also sequentially etched, and the device wafer 100 is used as an etching stop layer, and the etching is stopped when the front surface 101 of the wafer is exposed at the bottom of the trench 410. By exposing the bottom of the trench 410 to the device wafer 100, the conductive sidewall subsequently formed in the trench 410 can contact the device wafer 100, and thus the conductive sidewall can widely shield the first chip 205.

In another embodiment, after the encapsulation layer is etched, the bottom of the trench may be located in the encapsulation layer, that is, the trench does not penetrate through the encapsulation layer, and a thickness of encapsulation layer material is also present between the bottom of the trench and the second oxide layer. When the trench is filled with a conductive material, the formed conductive sidewall does not contact the device wafer, but extends to a certain thickness in a direction perpendicular to the surface of the device wafer, and the conductive sidewall can still shield the first chip. Therefore, in other embodiments, the bottom of the trench may also be exposed from the second oxide layer, or the bottom of the trench may be located in the first oxide layer.

Referring to fig. 12 and 13 in combination, a conductive material is formed in the trench 410 (shown in fig. 10) and on the surface of the encapsulation layer 400 above the first chip 205; the conductive material in the trenches 410 is conductive sidewalls 451 (shown in fig. 12 and 13); the conductive material on the surface of the packaging layer 400 above the first chip 205 is a conductive layer 452 (as shown in fig. 13), and the conductive layer 452 and the conductive sidewall 451 form a shielding shell 450 (as shown in fig. 13).

By locally shielding the first chip 205, the influence of an external magnetic field on the first chip 205 is reduced; since the shielding shell 450 selectively shields the first chip 205, that is, the shielding shell 450 is selectively formed on a portion of the chips 200, the volume and thickness of the entire package structure are not excessively increased, so that the package structure is lighter and thinner, and since the chips 200 and the device wafer 100 have higher bonding strength, the overall package structure can maintain better reliability, thereby also being beneficial to ensuring the anti-interference effect of the shielding shell 450 on the first chip 205.

In this embodiment, the shielding case 450 is an electrostatic shielding structure, and is used to terminate an external electric field on the surface of the shielding case 450 and transmit charges to the ground. Accordingly, the package structure formed in this embodiment connects the shielding shell 450 to the ground terminal during the use process.

It should be noted that, in other embodiments, the shielding shell may also be an electromagnetic shielding structure, and is configured to reduce the influence of the high-frequency electromagnetic field, so that the interference field forms an eddy current in the shielding shell, thereby weakening the field strength of the interference field at the integrated circuit position, and achieving the shielding effect.

As shown in fig. 12, the step of forming the shield case 450 includes: conductive material is filled into the trench 410 to form conductive sidewalls 451.

The conductive sidewall 451 is used to reduce the interference of the external magnetic field to the first chip 205, thereby improving the performance stability and reliability of the integrated circuit in the package structure.

Specifically, the conductive sidewall 451 is used for shielding from the side of the first chip 205, and forms a shielding shell 450 with a conductive layer 452 formed later.

In this embodiment, in order to achieve the shielding effect, the conductive material may be metal, for example: the conductive material is one or more of metals such as silver, copper, tin, aluminum, zinc, tungsten and the like. In other embodiments, the conductive material may be an alloy, such as: the conductive material is an alloy such as stainless steel.

In practice, the conductive sidewalls 451 are formed by an electroplating process. The conductive sidewall 151 formed by the electroplating method can achieve a good filling effect in the trench 410, thereby improving the shielding effect of the subsequently formed shielding shell 450. In other embodiments, the conductive sidewalls may also be formed by physical vapor deposition or sputtering methods.

In this embodiment, the conductive sidewall 451 is formed by a conductive material filled in the trench 410, so the thickness H (as shown in fig. 13) of the conductive sidewall 451 is the same as the width D (as shown in fig. 11) of the trench 410, and the distance H (as shown in fig. 13) between the inner sidewall of the conductive sidewall 451 and the opposite sidewall of the first chip 205 is the same as the distance D (as shown in fig. 11) between the inner sidewall of the trench 410 and the first chip 205. Correspondingly, the thickness H of the conductive side wall 451 is 10-50 micrometers, and the distance H between the inner side wall of the conductive side wall 451 and the opposite side wall of the first chip 205 is in the range of 5-100 micrometers. The inner sidewall of the conductive sidewall 451 refers to a sidewall of the conductive sidewall 451 close to the first chip 205.

As shown in fig. 13, the conductive material is formed continuously, and a conductive material is formed on the surface of the package layer 400, wherein the conductive material on the surface of the package layer 400 above the first chip 205 is a conductive layer 452, which is used to form a shielding shell 450 with the conductive sidewall 451.

The conductive layer 452 is connected to the conductive sidewall 451 to form a closed shielding can 450 over the first chip 205. The encapsulation layer 400 located between the first chip 205 and the conductive layer 452 serves as an insulation layer, so as to prevent the shielding shell 450 from affecting the normal operation of the first chip 205.

It should be noted that if the thickness P (shown in fig. 13) of the conductive material on the surface of the encapsulation layer 400 is too large, the volume and thickness of the shielding shell 450 are easily increased; if the thickness P of the conductive material on the surface of the encapsulation layer 400 is too small, the shielding effect of the shielding shell 450 is easily affected. Therefore, in the present embodiment, the thickness P of the conductive material on the surface of the encapsulation layer 400 is 5 to 50 μm.

It should be further noted that, in this embodiment, the shielding shell 450 is an electrostatic shielding structure, and the conductive layer 452 on the package layer 400 also serves as a ground terminal of the shielding shell 450, and is connected to the ground terminal in a use process of a subsequent formed package structure.

In addition, the packaging method of the embodiment further includes: after the shielding shell 450 is formed, the device wafer 100 is thinned through the wafer back side 102 of the device wafer 100, and a through-silicon via interconnection structure is formed in the thinned device wafer 100, which is not described in detail herein.

The same parts of this embodiment as those of the first embodiment will not be described herein again. The present embodiment is different from the first embodiment in that: after the packaging layer 600 is covered with the conductive material 610 (as shown in fig. 14), a portion of the conductive material 610 is removed, and the conductive material 610 on the surface of the packaging layer 600 above each of the first chips 605 remains, and the remaining conductive material 610 is a conductive layer 652 (as shown in fig. 15).

In this embodiment, the conductive material 610 on the surface of the package layer 600 that is not used for forming the shielding shell 650 (as shown in fig. 15) is removed, so as to reduce the problem of coupling capacitance caused by the excess conductive material 610, and optimize the performance of the package structure.

Specifically, as shown in fig. 14, the surface of the conductive sidewall 651 facing away from the first chip 605 is an outer side surface 653; removing a portion of the conductive material 610, and the step of retaining the conductive material 610 on the surface of the encapsulation layer 600 above the first chip 605 includes: a masking layer 660 is formed over the conductive material 610 over the first chip 605, the masking layer 660 masking the conductive material 610 over the first chip 605, and sidewalls of the masking layer 660 aligned with the outer side 653.

The sidewalls of the mask layer 660 are aligned with the outer sidewalls 653, so that in the subsequent step of removing a portion of the conductive material 610, as much of the conductive material 610 on the first chip 605 and in contact with the conductive sidewalls 651 remains as possible while removing the excess conductive material 610, thereby improving the shielding effect of the formed shielding shell 650.

In this embodiment, the mask layer 660 is a photoresist.

As shown in fig. 15, the mask layer 660 (shown in fig. 14) is used as a mask, the conductive material 610 exposed by the mask layer 660 (shown in fig. 14) is removed, the conductive material 610 on the surface of the package layer 600 above each first chip 605 is remained, and the remained conductive material 610 is a conductive layer 652 and is used for forming the shielding shell 650 with the conductive sidewall 651.

Specifically, the conductive material 610 is a metal, and a dry etching process may be used to remove the excess conductive material 610. For example: the conductive material 610 is aluminum, and a portion of the conductive material 610 may be removed by a dry etching process using chlorine gas as an etching gas.

In this embodiment, by removing the excess conductive material 610, the problem of coupling capacitance is reduced while ensuring that a local shielding is achieved for the first chip 605.

Correspondingly, the invention also provides a wafer level packaging structure.

Referring to fig. 13, a schematic structural diagram of a wafer level package structure according to an embodiment of the invention is shown.

The package structure includes: a device wafer 100; a plurality of chips 200 bonded to the device wafer 100, wherein a chip to be shielded in the plurality of chips 200 is a first chip 205, the number of the first chips 205 is one or more, and the plurality of chips 200 and the device wafer 100 are bonded by a low-temperature fusion bonding process; a packaging layer 400 on the device wafer 100 and covering the plurality of chips 200; conductive sidewalls 451 in the encapsulation layer 400 and surrounding each of the first chips 205; a conductive layer 452 on the surface of the package layer 400 above the first chip 205 for forming a shielding shell 450 with the conductive sidewall 451.

In this embodiment, the package structure is a wafer level system package structure.

Wherein the device wafer 100 is a wafer on which device fabrication is completed. The device wafer 100 may be fabricated using integrated circuit fabrication techniques, and thus the device wafer 100 generally includes devices such as NMOS devices and PMOS devices formed on a substrate, a dielectric layer formed on the devices, a metal interconnect structure, and a pad electrically connected to the metal interconnect structure.

In this embodiment, the substrate of the device wafer 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, the device wafer 100 includes a wafer front side 101 formed with the second chips 110 and a wafer back side 102 opposite to the wafer front side 101. Wherein the wafer backside 102 refers to a substrate bottom surface away from the bonding pads of the device wafer 100.

The chips 200 are used as chips to be integrated in a wafer level system package, and the chips 200 may be manufactured by using an integrated circuit manufacturing technology. In this embodiment, the chips 200 are chips made of silicon wafers. In other embodiments, the chip may be formed of other materials.

The plurality of chips 200 may be chips with the same function or different functions, and the number of the chips 200 is the same as that of the second chips 110 (shown in fig. 1).

It should be further noted that, in the plurality of chips 200, the first chip 205 is relatively susceptible to the influence of an external magnetic field, and the first chip 205 is a chip to be shielded.

In addition, in this embodiment, the number of the first chips 205 is taken as an example. In other embodiments, the number of the first chips may also be multiple.

In this embodiment, a bonding pad 210 is formed in the chip 200, a surface of the chip 200 close to the bonding pad 210 is a chip front surface 201, and a surface opposite to the chip front surface 201 is a chip back surface 202. Specifically, the bonding pad 210 may be a wire bonding pad, and the bonding pad 210 is used for electrically connecting the chip 200 with other semiconductor devices.

In this embodiment, the chip front surface 201 of the chip 200 is bonded to the wafer front surface 101 of the device wafer 100, so that the bonding surface of the chip 200 is the chip front surface 201. In other embodiments, the bonding surface of the chip may also be the back surface of the chip according to actual process requirements.

The chip 200 and the second chip 110 have a predetermined relative position relationship. The meaning that the chip 200 and the second chip 110 have the predetermined relative position relationship means that, after the chip 200 and the device wafer 100 are bonded, the chip 200 and the second chip 110 are disposed opposite to each other and aligned with each other, or a projection of the chip 200 on the front surface 101 (as shown in fig. 1) of the wafer partially overlaps with the second chip 110, or a projection of the chip 200 on the front surface 101 of the wafer is located on one side of the second chip 110.

In this embodiment, the plurality of chips 200 and the plurality of second chips 110 in the device wafer 100 are staggered, that is, the projection of the chips 200 on the device wafer 100 is not overlapped with the second chips 110.

By staggering the chips 200 and the second chips 110 in the device wafer 100, the difficulty of the process for forming the conductive side wall 451 is reduced, and the influence of the process for forming the conductive side wall 451 on the second chips 110 corresponding to the first chips 205 is reduced.

In other embodiments, the chip and a second chip in the device wafer may be aligned with each other, that is, a projection of the chip on the device wafer coincides with the second chip. Therefore, the shielding shell can also play a shielding effect on the second chip corresponding to the first chip.

The plurality of chips 200 and the device wafer 100 are bonded through a low-temperature fusion bonding process, and fusion bonding is a process for completing bonding mainly by using interfacial chemical force, so that the chips 200 and the device wafer 100 have higher bonding strength, and the yield and the reliability of the packaging structure are improved.

For this reason, in this embodiment, a first oxide layer 150 is formed on the surface of the device wafer 100, a surface of the chip 200 facing the device wafer 100 is a bonding surface (not labeled), and a second oxide layer 250 is formed on the bonding surface; the second oxide layer 250 is disposed opposite to the first oxide layer 150 and bonded by a low-temperature fusion bonding process, and the second oxide layer 250 and the first oxide layer 150 are used for realizing a physical connection between the device wafer 100 and the chip 200.

The contact surfaces of the first oxide layer 150 and the second oxide layer 250 are connected in a covalent bond manner, so that the first oxide layer 150 and the second oxide layer 250 have higher bonding strength, thereby being beneficial to improving the yield and reliability of the packaging structure.

The material of the second oxide layer 250 is the same as the material of the first oxide layer 150, so that covalent bonding can be achieved well, which is beneficial to further improving the bonding strength between the second oxide layer 250 and the first oxide layer 150.

In this embodiment, the material of the first oxide layer 150 and the second oxide layer 250 is silicon oxide. The silicon oxide material has higher process compatibility, and the silicon oxide is a material which is commonly used in the process and has lower cost, so that the process difficulty and the process cost are favorably reduced and the performance influence on the packaging structure is favorably reduced by selecting the silicon oxide material; moreover, the contact surfaces of the first oxide layer 150 and the second oxide layer 250 are bonded by covalent bonds of Si-O-Si, and the bonding energy of the Si-O bonds is large, so that the bonding strength between the chip 200 and the device wafer 100 can be effectively improved.

In other embodiments, the first oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide, and the second oxide layer may also be hafnium oxide, aluminum oxide, or lanthanum oxide.

In this embodiment, in order to reduce the process difficulty, the thicknesses of the first oxide layer 150 and the second oxide layer 250 are equal. However, the thicknesses of the first oxide layer 150 and the second oxide layer 250 are not necessarily too small, and are not necessarily too large. If the thickness is too small, the uniformity and quality of the thickness of the first oxide layer 150 and the second oxide layer 250 are easily reduced, and the bonding strength between the first oxide layer 150 and the second oxide layer 250 is also easily adversely affected; if the thickness is too large, the overall thickness of the packaging structure is correspondingly over-thickLarge, which is not favorable for improving the process integration level. For this reason, in this embodiment, the first oxide layer 150 and the second oxide layer 250 have both thicknesses

To

The encapsulation layer 400 covers the plurality of chips 200 (including the first chip 205) and the device wafer 100, and can play a role in sealing and moisture-proof, so as to reduce the probability that the second chip 110 and the chips 200 are damaged, contaminated or oxidized, thereby facilitating optimization of the performance of the obtained package structure; moreover, the encapsulation layer 400 encapsulates the plurality of chips 200, and can support the chips 200, thereby improving process operability during the manufacturing process of the package structure.

In this embodiment, the material of the package layer 400 is a polymer or a dielectric, and the package layer 400 also serves to insulate the shielding shell 450 from the first chip 205.

In this embodiment, the package layer 400 is an injection molding layer, and the package layer 400 is formed by an injection molding process. The filling performance of the injection molding layer is good, so that the packaging layer 400 can be well filled among the chips 200, thereby achieving good insulation and sealing effects.

Specifically, the material of the encapsulation layer 400 is epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, low cost and the like, and is widely used as a packaging material for electronic devices and integrated circuits. In other embodiments, the material of the encapsulation layer may also be a thermosetting material such as polyimide or silica gel, or the encapsulation layer may also be a dielectric material such as aluminum oxide or aluminum nitride.

In this embodiment, the second oxide layer 250 is further located between the package layer 400 and the first oxide layer 150.

By positioning the second oxide layer 250 between the package layer 400 and the first oxide layer 150, the difficulty of forming the second oxide layer 250 can be reduced, which is beneficial to simplifying process steps and reducing process cost, and the first oxide layer 150 is in contact with the second oxide layer 250, which is beneficial to further improving the bonding strength between the chip 200 and the device wafer 100, and the package layer 400 is in contact with the second oxide layer 250 to realize sealing, which can effectively reduce the probability of generating a gap between the device wafer 100 and the chip 200, and can better isolate air and moisture, thereby improving the package effect, and further being beneficial to optimizing the performance of the obtained package structure; in addition, the first oxide layer 150 and the second oxide layer 250 can also insulate the second chip 110 and the conductive sidewall 451, so as to prevent the conductive sidewall 451 from affecting the normal operation of the second chip 110.

The conductive sidewalls 451 are located in the package layer 400 and surround each of the first chips 205, and are used for shielding from the side of the first chips 205, and form a shielding shell 450 with the conductive layer 452 located on the package layer 400, so as to protect the first chips 205 and reduce the influence of the external magnetic field on the first chips 205.

Since the shielding shell 450 selectively shields the first chip 205, that is, the shielding shell 450 is selectively formed on a portion of the chips 200, the volume and thickness of the entire package structure are not excessively increased, so that the package structure is lighter and thinner, and since the chips 200 and the device wafer 100 have higher bonding strength, the overall package structure can maintain better reliability, thereby also being beneficial to ensuring the anti-interference effect of the shielding shell 450 on the first chip 205.

In this embodiment, the shielding case 450 is an electrostatic shielding structure, and is used for terminating an external electric field on the surface of the shielding case 450 and transmitting charges to the ground. Accordingly, the package structure of the present embodiment connects the shielding shell 450 to the ground terminal during the use process.

To achieve the shielding effect, the material of the shielding shell 450 may be metal, for example: the shielding shell 450 is made of one or more metals such as silver, copper, tin, aluminum, zinc, tungsten, and the like. In other embodiments, the material of the shielding shell may be an alloy, such as: the shielding shell is made of stainless steel and other alloys.

It should be noted that if the thickness h of the conductive sidewall 451 is too large, the thickness and volume of the whole package structure are easily increased; if the thickness h of the conductive sidewall 451 is too small, the shielding effect of the conductive sidewall 451 is easily affected. Therefore, in the present embodiment, the thickness h of the conductive sidewall 451 is in the range of 10 to 50 μm.

Typically, the projection of the first chip 205 on the device wafer 100 is rectangular. Accordingly, the projection of the conductive sidewall 451 surrounding the first chip 205 on the device wafer 100 is a rectangular ring, that is, the shape of the conductive sidewall 451 matches the shape of the first chip 205.

The sidewall of the conductive sidewall 451 close to the first chip 205 is an inner sidewall (not labeled), the distance between the inner sidewall and the opposite sidewall of the first chip 205 is H, if the distance H is too large, the conductive sidewall 451 is closer to other chips 200 adjacent to the first chip 205, which may easily affect the performance of other chips 200 and may also weaken the shielding effect of the conductive sidewall 451 on the first chip 205; if the distance H is too small, the insulation between the conductive sidewall 451 and the first chip 205 is easily affected. For this reason, in the present embodiment, the distance H between the inner sidewall and the opposite sidewall of the first chip 205 is in the range of 5 to 100 micrometers.

In this embodiment, the bottom of the conductive sidewall 451 is in contact with the device wafer 100, i.e., the conductive sidewall 451 extends through the package layer 400, the second oxide layer 250, and the first oxide layer 150. By contacting the bottom of the conductive sidewall 451 with the device wafer 100, the conductive sidewall 451 can be shielded to a greater extent from the first chip 205.

In another embodiment, the bottom of the conductive sidewall may also be located in the encapsulation layer, that is, the conductive sidewall does not penetrate through the encapsulation layer, and a thickness of encapsulation layer material is further present between the bottom of the conductive sidewall and the second oxide layer. In this case, although the bottom of the conductive sidewall is not in contact with the device wafer, but still extends with a certain thickness in a direction perpendicular to the surface of the device wafer, the conductive sidewall can still act as a shield for the first chip. Therefore, in other embodiments, the bottom of the conductive sidewall may also be in contact with the second oxide layer, or the bottom of the conductive sidewall is in the first oxide layer.

In this embodiment, the entire surface of the package layer 400 above the first chip 205 is covered with a conductive material, wherein the conductive material on the surface of the package layer 400 and in contact with the conductive sidewall 451 is the conductive layer 452, and is used to form an enclosed shielding case 450 with the conductive sidewall 451. The encapsulation layer 400 located between the first chip 205 and the conductive layer 452 can serve as an insulation layer, so as to prevent the shielding shell 450 from affecting the normal operation of the first chip 205.

It should be noted that if the thickness P of the conductive material on the surface of the encapsulation layer 400 is too large, the volume and thickness of the shielding shell 450 are easily increased; if the thickness P of the conductive material on the surface of the encapsulation layer 400 is too small, the shielding effect of the shielding shell 450 is easily affected. Therefore, in the present embodiment, the thickness P of the conductive material on the surface of the encapsulation layer 400 is in the range of 5 to 50 μm.

It should be further noted that, in the present embodiment, the shielding shell 450 is an electrostatic shielding structure, and the conductive layer 452 on the package layer 400 also serves as a ground terminal of the shielding shell 450, and is connected to the ground terminal in a use process of a subsequent formed package structure.

In addition, in this embodiment, the device wafer 100 is a wafer after wafer thinning processing, and a through silicon via interconnection structure (not shown) is further formed in the device wafer 100, which is not described in detail herein.

The package structure of this embodiment may be formed by using the package method of the first embodiment, or may be formed by using other package methods. In this embodiment, for the specific description of the package structure, reference may be made to the corresponding description in the first embodiment, and details of this embodiment are not repeated herein.

With continued reference to fig. 15, a schematic diagram of another embodiment of the wafer level package structure of the present invention is shown.

This embodiment is the same as the previous embodiment and is not as cumbersome herein. The same points of the package structure of this embodiment as those of the previous embodiment are not described again, and the difference between the package structure of this embodiment and the previous embodiment is: the conductive layer 652 partially covers the packaging layer 600 above each of the first chips 605.

In this embodiment, the conductive layer 652 only covers the surface of the packaging layer 600 above the first chip 605, but does not cover the surface of the packaging layer 600 in other areas, thereby reducing the problem of coupling capacitance and optimizing the performance of the packaging structure. Specifically, the side of the conductive sidewall 651 facing away from the first chip 605 is a lateral side 653, and the sidewall of the conductive layer 652 is aligned with the lateral side 653.

In this embodiment, the conductive layer 652 is obtained by removing the excess conductive material on the surface of the package layer 600, and the sidewall of the conductive layer 652 is aligned with the outer sidewall 653, so that the conductive material on each first chip 605 and in contact with the conductive sidewall 651 can be retained as much as possible while removing the excess conductive material, thereby improving the shielding effect of the shielding housing 650.

The package structure of this embodiment may be formed by using the package method of the second embodiment, or may be formed by using other package methods. In this embodiment, for the specific description of the package structure, reference may be made to the corresponding description in the foregoing second embodiment, and this embodiment is not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A wafer level packaging method, comprising:

providing a device wafer;

providing a bearing substrate, temporarily bonding a plurality of chips on the bearing substrate, wherein the chips are provided with bonding surfaces facing the bearing substrate, the chips to be shielded in the plurality of chips are first chips, and the number of the first chips is one or more;

forming an encapsulation layer covering the plurality of chips on the bearing substrate;

after the packaging layer is formed, removing the bearing substrate;

after the bearing substrate is removed, the bonding surface and the device wafer are oppositely arranged, and the bonding of the device wafer and the chip is realized by adopting a low-temperature fusion bonding process;

forming a trench in the encapsulation layer surrounding each of the first chips after the low temperature fusion bonding process;

forming a conductive material in the groove and on the surface of the packaging layer above the first chip; the conductive material in the groove is a conductive side wall; the conductive material on the surface of the packaging layer above the first chip is a conductive layer and is used for forming a shielding shell with the conductive side wall.

2. The packaging method of claim 1, further comprising: forming a first oxide layer on the surface of the device wafer; forming a second oxide layer on the bonding surface;

and carrying out the low-temperature melting bonding process through the first oxide layer and the second oxide layer.

3. The packaging method according to claim 2, wherein the second oxide layer is formed on the bonding face before temporarily bonding a plurality of chips on the carrier substrate;

or after removing the bearing substrate, forming a second oxide layer covering the packaging layer and the bonding surface.

4. The packaging method of claim 2, wherein the step of the low temperature fusion bonding process comprises: sequentially carrying out plasma activation treatment, deionized water cleaning treatment and drying treatment on the surface of the first oxidation layer and the surface of the second oxidation layer;

after the drying treatment, oppositely arranging and attaching the second oxidation layer and the first oxidation layer, and applying bonding pressure to the device wafer and the chips to carry out pre-bonding treatment;

and after the pre-bonding treatment, annealing the device wafer and the plurality of chips.

5. The packaging method of claim 1, wherein forming a conductive material in the trench and on a surface of the package layer above the first chip comprises: covering the packaging layer with a conductive material; and removing part of the conductive material, and reserving the conductive material on the surface of the packaging layer above each first chip, wherein the reserved conductive material is the conductive layer.

6. The packaging method according to claim 5, wherein a surface of the conductive sidewall facing away from the first chip is an outer side surface;

removing part of the conductive material, and reserving the conductive material on the surface of the encapsulation layer above each first chip, wherein the step of removing the part of the conductive material comprises the following steps: forming a mask layer on the conductive material above the first chip, wherein the mask layer shields the conductive material above the first chip, and the side wall of the mask layer is aligned with the outer side face; and removing the conductive material exposed by the mask layer.

7. The packaging method of claim 1, wherein the trench is formed by an etching process.

8. The packaging method of claim 7, wherein the etching process is a laser etching process.

9. The packaging method according to claim 4, wherein the reactive gas used in the plasma activation process comprises Ar, N₂、O₂And SF₆One or more of (a).

10. The packaging method of claim 1, wherein the conductive material is a metal, the conductive material being formed by an electroplating process.

11. The packaging method of claim 1, wherein the trench exposes the device wafer; alternatively, the bottom of the trench is located in the encapsulation layer.

12. A wafer level package structure, comprising:

a device wafer;

the device wafer is bonded with a plurality of chips, wherein the chips to be shielded in the plurality of chips are first chips, the number of the first chips is one or more, and the plurality of chips are bonded with the device wafer through a low-temperature fusion bonding process;

a packaging layer located on the device wafer and covering the plurality of chips;

conductive sidewalls in the encapsulation layer and surrounding each of the first chips;

and the conducting layer is positioned on the surface of the packaging layer above the first chip and is used for being connected with the conducting side wall to form a shielding shell.

13. The package structure of claim 12, wherein the conductive layer partially covers the encapsulation layer over each of the first chips.

14. The package structure of claim 12, wherein the encapsulation layer is covered with a conductive material, the conductive material is located above the first chip, and a portion connected to the conductive sidewall is the conductive layer.

15. The package structure of claim 12, wherein a bottom of the conductive sidewall is in contact with the device wafer; alternatively, the bottom of the conductive sidewall is located in the encapsulation layer.

16. The package structure of claim 12, wherein the material of the shielding shell is a metal.

17. The package structure of claim 12, wherein the conductive sidewall has a thickness in a range of 10-50 microns.

18. The package structure of claim 12, wherein the conductive sidewall adjacent to the first chip is an inner sidewall, and a distance between the inner sidewall and an opposite sidewall of the first chip is in a range from 5 to 100 μm.

19. The package structure of claim 12, wherein a first oxide layer is formed on a surface of the device wafer; the surface of the chip facing the device wafer is a bonding surface, and a second oxidation layer is formed on the bonding surface;

the second oxide layer is arranged opposite to the first oxide layer and bonded through a low-temperature melting bonding process.

20. The package structure of claim 12, wherein the second oxide layer is further located between the encapsulation layer and the first oxide layer.