CN110868209A - High-phase-precision voltage-controlled delay line structure for multi-phase delay phase-locked loop and implementation method thereof - Google Patents
High-phase-precision voltage-controlled delay line structure for multi-phase delay phase-locked loop and implementation method thereof Download PDFInfo
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Abstract
The invention discloses a high-phase precision voltage-controlled delay line structure for a multiphase delay phase-locked loop and an implementation method thereof, wherein the high-phase precision voltage-controlled delay line structure comprises an n-level phase output circuit; the single-ended-differential circuit of the phase output circuit of the first stage is used for accessing a reference clock REF, and the single-ended-differential circuit of the phase output circuit of the other stage is connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage; the input of the delay unit of each stage of phase output circuit is connected with the output of the single-end-differential circuit of the stage of phase output circuit, and the output of the delay unit of each stage of phase output circuit is connected with the input of the differential-single-end circuit of the stage of phase output circuit. The invention can reduce the matching error from the circuit level and can also save the chip area and the power consumption.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a high-phase-precision voltage-controlled delay line structure for a multiphase delay phase-locked loop and an implementation method thereof.
Background
With the progress of IC design technology and the reduction of process size, the scale of system on chip is larger and higher, the operating frequency is also higher and the on-chip clock becomes the mainstream choice.
A Delay Locked Loop (DLL) is an important module of a Time-to-digital converter (TDC). To digitize the time intervals recorded in the TDC, a plurality of high phase precision clocks are typically required. Analog DLLs are commonly used in TDCs because of their higher accuracy and lower jitter at lower power consumption compared to digital DLLs. However, for the conventional multi-phase DLL, a Voltage-Controlled delay line (VCDL) outputs a multi-phase clock by adopting a delay cell phase cascade connection manner, and the conventional structure is shown in fig. 1, where there is a mismatch condition between any two stages of phase output circuits; in particular, the first and last stages are completely different from the other intermediate stages, so that the phase error between any two output phases is relatively large.
In summary, a high-phase-accuracy voltage-controlled delay line structure for a multiphase delay-locked loop is needed.
Disclosure of Invention
The present invention is directed to a high-phase-accuracy voltage-controlled delay line structure for a multi-phase delay-locked loop and a method for implementing the same, so as to solve one or more of the above technical problems. Aiming at the phase error caused by interstage mismatching, the invention provides a high-phase precision VCDL structure with better matching performance, which can reduce the matching error on the circuit level on one hand and can save the chip area and the power consumption on the other hand because the circuit structure is simple by matching the same module for each stage of phase output circuit and outputting a multi-phase clock by adopting an end-to-end interstage connection mode.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention relates to a high-phase-precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop, which comprises an n-level phase output circuit;
each stage of phase output circuit comprises:
a single-ended-differential circuit for outputting a differential signal;
the delay unit is used for delaying the differential signal output by the single-ended-differential circuit;
the differential-single-ended circuit is used for converting the differential output signals of the delay unit into single-ended signals which are used as output clock signals of each phase output circuit;
the single-ended-differential circuit of the phase output circuit of the first stage is used for accessing a reference clock REF, and the single-ended-differential circuits of the phase output circuits of other stages are connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage;
the input of the delay unit of each stage of phase output circuit is connected with the output of the single-end-differential circuit of the stage of phase output circuit, and the output of the delay unit of each stage of phase output circuit is connected with the input of the differential-single-end circuit of the stage of phase output circuit.
The invention has the further improvement that the input signal period of the voltage-controlled delay line structure is T, and n paths of clock signals with each stage of time delay of T/n are obtained after the time delay processing of the time delay unit.
The invention is further improved in that the delay unit of each stage of phase output circuit adopts a differential pair type circuit structure.
The invention is further improved in that the output of the differential-to-single-ended circuit of the last stage is connected with a single-ended-to-differential conversion circuit for ensuring the structural consistency of each stage of circuit.
The invention relates to a method for realizing a high-phase-precision voltage-controlled delay line structure for a multiphase delay phase-locked loop, which is based on the existing voltage-controlled delay line structure and comprises an n-level phase output circuit and also comprises the following steps:
in the existing voltage-controlled delay line structure, the connection between differential delay circuits of each stage of phase output circuit is disconnected;
the second-stage phase output circuit to the nth-stage phase output circuit, wherein each stage of phase output circuit is additionally provided with a single-ended-differential circuit; the output of the single-ended-differential circuit of each stage of phase output circuit is connected with the input of the differential delay circuit of the phase output circuit of the stage, and the input of the single-ended-differential circuit of each stage of phase output circuit is connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage.
A further improvement of the present invention is that the existing voltage controlled delay line structure comprises: a single-ended-differential circuit and a multi-stage phase output circuit;
in the multi-stage phase output circuit, each stage of phase output circuit is formed by connecting a differential delay circuit and a differential-single-ended circuit; the output of the differential delay circuit is used as the input of the differential-single-ended circuit, and the output of the differential single-ended circuit is used as the output clock signal of each stage of phase output circuit;
the single-ended-differential circuit is used for outputting differential signals; the single-ended-differential circuit is used for accessing a reference clock REF;
the output of the single-ended-differential circuit is connected to the input of the differential delay circuit in the first-stage phase output circuit; in the second-stage to nth-stage phase output circuits, the input of the differential delay circuit in the phase output circuit is connected with the differential delay circuit in the previous-stage phase output circuit.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a high-phase-precision VCDL structure with better matching for phase errors caused by interstage mismatching. According to the voltage-controlled delay line structure, the same module is matched for each phase output circuit, and the multi-phase clock is output in an end-to-end connection mode, so that on one hand, the matching error can be reduced on the circuit level, and on the other hand, the chip area and the power consumption can be saved due to the simple circuit structure.
In the VCDL structure, each stage of phase output circuit comprises a single-ended-differential circuit (module I), a delay unit (module II) and a differential-single-ended circuit (module III). In the circuit module I, the input of the single-ended-differential circuit is connected to the reference clock REF of the system or the output of the previous stage, and after conversion by the internal circuit, differential signals INa and INb are output. In the circuit module II, the delay unit adopts a differential pair type circuit structure, the differential input of which is connected to the outputs INa and INb of the single-ended-differential circuit and outputs the differential signals OUTa and OUTb, and this structure can reduce the influence of noise on the circuit while realizing the delay function. In the circuit module III, the input of the differential-single-ended circuit is connected with the outputs OUTb and OUTA of the delay unit and outputs a single-ended clock signal OUTn; considering the load effect, an STD is added to the last stage of differential-single-ended circuit, so that the n phase output circuits are better matched. The circuit provided by the invention has a simple structure, is easy to realize, and can better meet the development requirement of a low-power-consumption miniaturized integrated circuit.
The method can realize the high-phase-precision voltage-controlled delay line structure for the multiphase delay phase-locked loop. The circuit structure realized by the invention is simple, and can better meet the development requirement of the low-power-consumption miniaturized integrated circuit.
The VCDL structure of the invention does not need to add any calibration circuit, but ensures the consistency of the circuit structure of each stage through the optimization of the circuit structure of the VCDL structure, and has the characteristic of low power consumption, and the average current of each stage of circuit is about 540 muA under the condition of realizing the phase precision equivalent to the result.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art are briefly introduced below; it is obvious that the drawings in the following description are some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic circuit diagram of a conventional VCDL architecture implementation;
FIG. 2 is a schematic diagram of a high phase accuracy voltage-controlled delay line structure for a multiphase delay locked loop according to an embodiment of the present invention;
fig. 3 is a diagram illustrating a simulation result of the output phase of the conventional VCDL structure and the VCDL structure according to the embodiment of the present invention; fig. 3 (a) is a diagram illustrating a simulation result of an output phase of a conventional VCDL structure, and fig. 3 (b) is a diagram illustrating a simulation result of an output phase of a VCDL structure according to an embodiment of the present invention.
Detailed Description
In order to make the purpose, technical effect and technical solution of the embodiments of the present invention clearer, the following describes the technical solution of the embodiments of the present invention clearly and completely with reference to the attached drawings in the embodiments of the present invention; it is to be understood that the described embodiments are only some of the embodiments of the present invention. Other embodiments, which can be derived by one of ordinary skill in the art from the disclosed embodiments without inventive faculty, are intended to be within the scope of the invention.
Referring to fig. 2, a voltage-controlled delay line structure with high phase precision for a multi-phase delay-locked loop according to an embodiment of the present invention is a high phase precision VCDL structure for a multi-phase DLL, in which the circuit is simple to implement; all transistors for realizing the circuit adopt the same manufacturing process. In the invention, each stage of phase output circuit comprises a single-ended-differential circuit (module I), a delay unit (module II) and a differential-single-ended circuit (module III).
Specifically, the high-phase-precision Voltage-Controlled-Delay Line (VCDL) structure of the present invention includes an n (greater than or equal to 2) stage phase output circuit; each stage of phase output circuit comprises: a Single-to-Differential circuit STD (Single-to-Differential) for outputting a Differential signal; the delay unit is used for delaying the differential signal output by the single-ended-differential circuit; a Differential-to-Single-ended circuit DTS (Differential-to-Single) for converting a Differential output signal of the delay unit into a Single-ended signal as an output clock signal of each phase output circuit; the single-ended-differential circuit of the phase output circuit of the first stage is used for accessing a reference clock REF, and the single-ended-differential circuits of the phase output circuits of other stages are connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage; the input of the delay unit of each stage of phase output circuit is connected with the output of the single-end-differential circuit of the stage of phase output circuit, and the output of the delay unit of each stage of phase output circuit is connected with the input of the differential-single-end circuit of the stage of phase output circuit.
The input of the single-ended-differential circuit shown in the module I is connected to the reference clock REF of the system or the output of the previous stage, and after conversion by the internal circuit, differential signals INa and INb are output to provide a pair of differential signals for the delay unit.
The delay unit shown in the module II adopts a differential pair type circuit structure, the differential input of the delay unit is connected with the outputs INa and INb of the single-ended-differential circuit, and differential signals OUTA and OUTb are output, and the structure can reduce the influence of noise on the circuit while realizing the delay function; assuming that the period of the input signal is T, the VCDL has n stages of phase output circuits, and after the processing of the delay unit, n paths of clock signals with each stage of delay being T/n are obtained.
The input of the differential-single-ended circuit shown in the module III is connected with the outputs OUTb and OUTA of the delay unit, and outputs a clock signal OUTn which is used for outputting the delayed differential signal in the form of a single-ended clock signal; considering the load effect, an STD is added to the last stage of the differential-single-ended circuit, so that the n phase output circuits are better matched.
Explanation in the examples of the present invention:
DLL: delay Locked Loop; TDC: Time-to-Digital Converter, Time-to-Digital Converter; VCDL: Voltage-Controlled Delay Line.
Table 1 phase accuracy comparison of conventional VCDL structure and VCDL structure of the present invention
The data is based on the simulation result under the condition that T is 10ns and n is 4
In the embodiment of the present invention, each stage of phase output circuit includes a single-ended-differential circuit, a delay unit, and a differential-single-ended circuit, which have multiple implementation manners, and the present invention does not limit the specific implementation manner of a certain module circuit.
In order to verify the effect of the VCDL structure of the embodiment of the present invention, under the conditions that the power voltage is 1.8V, the period is 10ns, and n is 4, simulation comparison is performed on the DLLs including the conventional VCDL structure and the VCDL structure of the present embodiment, respectively, wherein the STD circuit adopts a structure shown in the literature (set-jump Bae, hang-join Chi, hang-jump Kim and Hong-jump Park, "A3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with differentiation of equalization and offset coefficients," isscc.2005, pp.520-521 "), and is implemented by an inverter circuit; the delay circuit adopts a differential circuit structure shown in the literature (J.Wu, Y.Zhang, R.Zhao, K.Zhang, L.ZHEN and W.Sun, "Low-jitter DLL applied for two-segment TDC," IETCircuts, Devices & Systems, vol.12, No.1, pp.17-24, Jan.2018.); the DTS circuit has a structure shown in the literature (Joonsuk Lee, and Beomp Kim, A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control, IEEE Journal of Solid-StateCruits, vol.35, No.8, pp.1137-1145. Aug.2000.).
Referring to fig. 3, the phase accuracy simulation results are shown in fig. 3, and the data are collated in table 1. The expected phase difference between every two adjacent output signals is pi/2, namely 2.5ns, and the simulation result shows that the maximum phase error rate of the traditional VCDL structure is-6.8%, namely, the delay is 2.33ns, and the error is 0.17ns, while the maximum phase error rate of the embodiment of the invention is only 0.8%, namely, the delay is 2.52ns, and the error is 0.02ns, so that the phase precision of the VCDL structure of the embodiment of the invention is greatly improved compared with that of the traditional VCDL structure.
In addition, some calibration schemes currently exist to improve phase accuracy. H. The digital self-calibration technique proposed by-h.chang, j. -y.chang and c. -y.kuo et al in a paper entitled "a 0.7-2-GHz self-calibrated multiphase delay-locked loop" uses a digital calibration circuit to adjust the output of each stage of the VCDL, which includes the digital calibration circuit, to achieve an improvement in phase accuracy, with the average current of each stage of the VCDL being 5 mA. An analog calibration technique is proposed in a paper entitled "a Self-Calibrated DLL-Based Clock Generator for an Energy-aware eisc Processor" by s.hwang, k.kim and j.kim et al, adding an analog calibration circuit, including an analog calibration circuit, to the output of each stage of VCDL, the average current of each stage of VCDL being 930 μ a; the VCDL structure of the embodiment of the invention does not need to add any calibration circuit, but ensures the consistency of the circuit structure of each stage through the optimization of the circuit structure of the VCDL structure, and has the characteristic of low power consumption, wherein the average current of each stage of circuit is 540 muA under the condition of realizing the phase precision equivalent to the result.
To sum up, the embodiment of the present invention provides a high-phase precision VCDL structure applied to a multi-phase DLL, which has a simple circuit, and except for the 1 st stage, each stage of phase output circuit can be realized by adding 1 STD on the basis of the conventional VCDL structure circuit. Compared with the traditional VCDL structure circuit, the implementation circuit of the VCDL structure disclosed by the invention reduces the phase error caused by the mismatching among stages by carrying out structure matching on each stage of phase output circuit, thereby improving the output phase precision and simultaneously realizing the low power consumption and the miniaturization of a chip.
The implementation method of the high-phase-precision voltage-controlled delay line structure for the multiphase delay phase-locked loop in the embodiment of the invention is based on the existing voltage-controlled delay line structure, comprises an n-level phase output circuit, and comprises the following steps:
in the existing voltage-controlled delay line structure, the connection between differential delay circuits of each stage of phase output circuit is disconnected;
the second-stage phase output circuit to the nth-stage phase output circuit, wherein each stage of phase output circuit is additionally provided with a single-ended-differential circuit; the output of the single-ended-differential circuit of each stage of phase output circuit is connected with the input of the differential delay circuit of the phase output circuit of the stage, and the input of the single-ended-differential circuit of each stage of phase output circuit is connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage.
The existing voltage controlled delay line structure comprises: a single-ended-differential circuit and a multi-stage phase output circuit;
in the multi-stage phase output circuit, each stage of phase output circuit is formed by connecting a differential delay circuit and a differential-single-ended circuit; the output of the differential delay circuit is used as the input of the differential-single-ended circuit, and the output of the differential single-ended circuit is used as the output clock signal of each stage of phase output circuit;
the single-ended-differential circuit is used for outputting differential signals; the single-ended-differential circuit is used for accessing a reference clock REF;
the output of the single-ended-differential circuit is connected to the input of the differential delay circuit in the first-stage phase output circuit; in the second-stage to nth-stage phase output circuits, the input of the differential delay circuit in the phase output circuit is connected with the differential delay circuit in the previous-stage phase output circuit.
In summary, the present invention discloses a high phase-precision Voltage-Controlled Delay Line (VCDL) structure for a multi-phase Delay Locked Loop (DLL), which mainly solves the problem of large output phase error caused by inter-stage mismatch of VCDL. The invention discloses a phase output circuit of each stage of a VCDL structure, which comprises a single-ended-differential circuit (shown as a module I in figure 1), a delay unit (shown as a module II in figure 1) and a differential-single-ended circuit (shown as a module III in figure 1), wherein the single-ended-differential circuit is used for converting a single-ended input signal into a differential signal; the delay unit is responsible for finishing the task of delaying and outputting the differential input signal; the differential-single-ended circuit is used for converting the differential signal output by the delay unit into a single-ended clock signal and outputting the single-ended clock signal. After the input clock passes through the phase output circuit formed by the three modules, clock signals with the same frequency and different phases are uniformly output. The circuit corresponding to the VCDL structure disclosed by the invention has low power consumption and small scale, and is suitable for the design of a low-power-consumption miniaturized circuit.
Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art can make modifications and equivalents to the specific embodiments of the present invention, and such modifications and equivalents do not depart from the spirit and scope of the present invention and are intended to be included within the scope of the claims of the present invention.
Claims (6)
1. A high-phase-precision voltage-controlled delay line structure for a multi-phase delay phase-locked loop is characterized by comprising n stages of phase output circuits;
each stage of phase output circuit comprises:
a single-ended-differential circuit for outputting a differential signal;
the delay unit is used for delaying the differential signal output by the single-ended-differential circuit;
the differential-single-ended circuit is used for converting the differential output signals of the delay unit into single-ended signals which are used as output clock signals of each phase output circuit;
the single-ended-differential circuit of the phase output circuit of the first stage is used for accessing a reference clock REF, and the single-ended-differential circuits of the phase output circuits of other stages are connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage;
the input of the delay unit of each stage of phase output circuit is connected with the output of the single-end-differential circuit of the stage of phase output circuit, and the output of the delay unit of each stage of phase output circuit is connected with the input of the differential-single-end circuit of the stage of phase output circuit.
2. The voltage-controlled delay line structure of claim 1, wherein the input signal period of the voltage-controlled delay line structure is T, and n clock signals with a delay of T/n per stage are obtained after the delay processing of the delay unit.
3. The high-phase-precision voltage-controlled delay line structure for the multiphase delay phase-locked loop of claim 1, wherein the delay units of each stage of the phase output circuit are in a differential pair type circuit structure.
4. The voltage-controlled delay line structure of high phase precision for multiphase delay phase-locked loop as claimed in claim 1, wherein the output of the last stage of differential-to-single-ended circuit is connected with a single-ended-to-differential conversion circuit for ensuring the structural consistency of each stage of circuit.
5. The utility model provides a high phase accuracy voltage-controlled delay line structure's implementation method for multiphase time delay phase-locked loop, is based on current voltage-controlled delay line structure, includes n grades of phase output circuit, its characterized in that still includes:
in the existing voltage-controlled delay line structure, the connection between differential delay circuits of each stage of phase output circuit is disconnected;
the second-stage phase output circuit to the nth-stage phase output circuit, wherein each stage of phase output circuit is additionally provided with a single-ended-differential circuit; the output of the single-ended-differential circuit of each stage of phase output circuit is connected with the input of the differential delay circuit of the phase output circuit of the stage, and the input of the single-ended-differential circuit of each stage of phase output circuit is connected with the output of the differential-single-ended circuit of the phase output circuit of the previous stage.
6. The method of claim 5, wherein the existing voltage-controlled delay line structure comprises: a single-ended-differential circuit and a multi-stage phase output circuit;
in the multi-stage phase output circuit, each stage of phase output circuit is formed by connecting a differential delay circuit and a differential-single-ended circuit; the output of the differential delay circuit is used as the input of the differential-single-ended circuit, and the output of the differential single-ended circuit is used as the output clock signal of each phase output circuit;
the single-ended-differential circuit is used for outputting differential signals; the single-ended-differential circuit is used for accessing a reference clock REF;
the output of the single-ended-differential circuit is connected to the input of the differential delay circuit in the first-stage phase output circuit; in the second-stage to nth-stage phase output circuits, the differential delay circuit in the phase output circuit has its input connected to the differential delay circuit in the previous-stage phase output circuit.
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