CN110855288A

CN110855288A - Clock circuit and clock signal generation method

Info

Publication number: CN110855288A
Application number: CN201911182851.1A
Authority: CN
Inventors: 贾雪绒
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2019-11-27
Filing date: 2019-11-27
Publication date: 2020-02-28
Anticipated expiration: 2039-11-27
Also published as: CN110855288B

Abstract

The invention discloses a clock circuit, comprising: a first inductance capacitance type phase-locked loop and a first annular phase-locked loop; the first inductance and capacitance type phase-locked loop is used for carrying out frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal; the first annular phase-locked loop is used for carrying out frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal. The invention solves the technical problem that the prior art can not provide a clock signal with high speed, wide frequency and low jitter.

Description

Clock circuit and clock signal generation method

Technical Field

The present invention relates to the field of clock generation circuits, and in particular, to a clock circuit and a clock signal generation method.

Background

Compared with the traditional dynamic random access memory DDR3/4/LPDDR4 physical interface PHY, the graphic dynamic random access memory GDDR6 physical interface PHY needs to provide a data transmission rate as high as 16Gbps, a system level puts more strict requirements on a clock generation circuit, a high-speed, high-performance and low-jitter clock generation circuit is needed, and the specific requirements are as follows:

1. it is necessary to provide a high speed clock signal up to 8 GHz.

2. It is necessary to provide a low-jitter clock signal to satisfy the requirement that the system as a whole is controlled within 0.2 unit time interval UI.

3. It is necessary to provide a clock signal that can cover a relatively wide frequency range, supporting a frequency range of 5GH to 8GHz (especially 5/6/6.5/7/8 GHz).

However, the clock signal provided by the clock circuit in the prior art cannot simultaneously have three performances of high speed, wide frequency and low jitter, and cannot meet the requirement of the physical interface PHY of the GDDR6 on the clock generation circuit.

Disclosure of Invention

The embodiments of the present application provide a clock circuit and a clock signal generating method, so as to solve the technical problem that a clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art.

In a first aspect, the present application provides the following technical solutions through an embodiment of the present application:

a clock circuit, comprising: a first inductance capacitance type phase-locked loop and a first annular phase-locked loop; the first inductance and capacitance type phase-locked loop is used for carrying out frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal; the first annular phase-locked loop is used for carrying out frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal.

In one embodiment, the frequency of the first target clock signal is determined according to Fout ═ Fin × (N)/M, where Fout is the frequency of the first target clock signal, Fin is the frequency of the first high-frequency clock signal, M and N are frequency allocation coefficients of the first annular phase-locked loop, N is 1 to 16, and M is 1 to 2.

In one embodiment, the bandwidth of the first ring phase locked loop is set to be one twentieth of the frequency of the first high frequency clock signal to one tenth of the frequency of the first high frequency clock signal.

In one embodiment, the first input clock signal is provided by an external crystal oscillator.

In one embodiment, the first lc pll comprises: the first frequency discrimination phase detector is used for detecting the frequency difference and the phase difference between the first input clock signal and a first internal feedback signal and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal; the first charge pump is used for amplifying the first control signal and outputting a first amplified signal; the first loop filter is used for carrying out low-pass filtering processing on the first amplified signal and outputting a first filtered signal; the first inductance-capacitance type voltage-controlled oscillator is used for outputting the first high-frequency clock signal according to the first filtering signal; and the first feedback frequency divider is used for carrying out frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal.

In one embodiment, the first ring phase locked loop comprises: a first automatic frequency calibration module, configured to detect a frequency difference between the first high-frequency clock signal and a second internal feedback signal, and generate a second control signal according to the frequency difference between the first high-frequency clock signal and the second internal feedback signal; a second phase frequency detector for detecting a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal, and generating a third control signal according to the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal; the second charge pump is used for amplifying the third control signal and outputting a second amplified signal; the first voltage control switch is used for collecting the second amplified signal and outputting a corresponding first voltage pulse signal; the second loop filter is used for carrying out low-pass filtering processing on the first voltage pulse signal to obtain a second filtered signal; a first ring voltage controlled oscillator for outputting the first target clock signal according to the second filtered signal and the second control signal; and the second feedback frequency divider is used for carrying out frequency division processing on the first target clock signal and outputting a second internal feedback signal.

In a second aspect, the present application provides the following technical solutions according to an embodiment of the present application:

a clock circuit, comprising: the second inductance and capacitance type phase-locked loop, the frequency divider and the second annular phase-locked loop; the second inductance and capacitance type phase-locked loop is used for carrying out frequency multiplication processing on a second input clock signal to generate a second high-frequency clock signal; the frequency divider is used for carrying out frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal; and the second annular phase-locked loop is used for carrying out frequency multiplication processing on the third high-frequency clock signal to generate a second target clock signal.

In one embodiment, the number of the second ring phase-locked loops is two or more, and the two or more second ring phase-locked loops have different frequency configuration coefficients, and the frequency configuration coefficients are used for configuring the frequency of the second target clock signal; the input end of each second annular phase-locked loop is connected with the output end of the frequency divider.

In one embodiment, the number of the frequency dividers is more than two, and the more than two frequency dividers have different frequency division coefficients; the input end of each frequency divider is connected with the output end of the second inductance and capacitance type phase-locked loop, and the output end of each frequency divider is connected with the input end of the second annular phase-locked loop.

In one embodiment, the number of the second ring-shaped phase-locked loops is two or more, and the two or more second ring-shaped phase-locked loops correspond to the two or more frequency dividers one to one, wherein the two or more second ring-shaped phase-locked loops have the same frequency configuration coefficient, and the frequency configuration coefficient is used for configuring the frequency of the second target clock signal.

In one embodiment, the number of the second ring-shaped phase-locked loops is two or more, and the two or more second ring-shaped phase-locked loops correspond to the two or more frequency dividers one to one, wherein the two or more second ring-shaped phase-locked loops have different frequency configuration coefficients, and the frequency configuration coefficients are used for configuring the frequency of the second target clock signal.

In one embodiment, the frequency of the second target clock signal is determined according to Fout ═ Fin × (N)/M, where Fout is the frequency of the second target clock signal, Fin is the frequency of the third high-frequency clock signal, M and N are frequency allocation coefficients of the first annular phase-locked loop, N is 1 to 16, and M is 1 to 2.

In one embodiment, the bandwidth of the second ring phase locked loop is set to be one twentieth of the frequency of the third high frequency clock signal to one tenth of the frequency of the third high frequency clock signal.

In one embodiment, the second input clock signal is provided by an external crystal oscillator.

In one embodiment, the second lc pll comprises: a third phase frequency detector for detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal; the third charge pump is used for amplifying the fourth control signal and outputting a third amplified signal; the third loop filter is used for performing low-pass filtering processing on the third amplified signal and outputting a third filtered signal; the second inductance-capacitance type voltage-controlled oscillator is used for outputting the second high-frequency clock signal according to the third filtering signal; and the third feedback frequency divider is used for carrying out frequency division processing on the second high-frequency clock signal to obtain a third internal feedback signal.

In one embodiment, the second ring phase locked loop comprises: a second automatic frequency calibration module, configured to detect a frequency difference between the third high-frequency clock signal and a fourth internal feedback signal, and generate a fifth control signal according to the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal; a fourth phase frequency detector, configured to detect a frequency difference and a phase difference between the third high-frequency clock signal and the fourth internal feedback signal, and generate a sixth control signal according to the frequency difference and the phase difference between the third high-frequency clock signal and the second internal feedback signal; the fourth charge pump is used for amplifying the sixth control signal and outputting a fourth amplified signal; the second voltage control switch is used for collecting the fourth amplified signal and outputting a corresponding second voltage pulse signal; the fourth loop filter is used for carrying out low-pass filtering processing on the second voltage pulse signal to obtain a fourth filtering signal; a second ring voltage controlled oscillator for outputting the second target clock signal in accordance with the fifth control signal and the fourth filtered signal; and the fourth feedback frequency divider is used for carrying out frequency division processing on the second target clock signal and outputting a fourth internal feedback signal.

In a third aspect, the present application provides the following technical solutions through an embodiment of the present application:

a clock signal generation method, comprising: receiving a first input clock signal by a first inductance and capacitance type phase-locked loop, and carrying out frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal; and carrying out frequency multiplication processing on the first high-frequency clock signal by using a first annular phase-locked loop to generate a first target clock signal.

In one embodiment, the receiving, by a first lc pll, a first input clock signal and performing frequency multiplication on the first input clock signal to generate a first high frequency clock signal includes: receiving and detecting a frequency difference and a phase difference between the first input clock signal and a first internal feedback signal by a first frequency discrimination phase detector, and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal; amplifying the first control signal by a first charge pump, and outputting a first amplified signal; performing low-pass filtering processing on the first amplified signal by a first loop filter to output a first filtered signal; outputting, by a first LC-VCO, the first high frequency clock signal in accordance with the first filtered signal; and carrying out frequency division processing on the first high-frequency clock signal by a first feedback frequency divider to obtain the first internal feedback signal.

In one embodiment, the frequency multiplication processing of the first high-frequency clock signal by the first circular phase-locked loop to generate a first target clock signal includes: detecting, by a first automatic frequency calibration module, a frequency difference between the first high-frequency clock signal and a second internal feedback signal, and generating a second control signal according to the frequency difference between the first high-frequency clock signal and the second internal feedback signal; detecting a frequency difference and a phase difference between the first high-frequency clock signal and the second internal feedback signal by a second phase frequency detector, and generating a third control signal according to the frequency difference and the phase difference between the first high-frequency clock signal and the second internal feedback signal; amplifying the third control signal by a second charge pump, and outputting a second amplified signal; collecting the second amplified signal by a first voltage control switch, and outputting a corresponding first voltage pulse signal; carrying out low-pass filtering processing on the first voltage pulse signal by a second loop filter to obtain a second filtered signal; outputting, by a first ring-shaped voltage controlled oscillator, the first target clock signal according to the second filtered signal and the second control signal; and performing frequency division processing on the first target clock signal by a second feedback frequency divider, and outputting a second internal feedback signal.

In a fourth aspect, the present application provides the following technical solutions according to an embodiment of the present application:

a method of generating a clock signal, comprising: receiving a second input clock signal by a second inductance capacitance type phase-locked loop, and carrying out frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal; performing frequency division processing on the second high-frequency clock signal by a frequency divider to generate a third high-frequency clock signal; and performing frequency multiplication processing on the third high-frequency clock signal by using a second annular phase-locked loop to generate a second target clock signal.

In one embodiment, the receiving, by the second lc-pll, a second input clock signal and performing frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal includes: receiving and detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal by a third phase frequency detector, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal; amplifying the fourth control signal by a third charge pump, and outputting a third amplified signal; performing low-pass filtering processing on the third amplified signal by a third loop filter, and outputting a third filtered signal; outputting, by a second LC-based voltage controlled oscillator, the second high frequency clock signal based on the third filtered signal; and carrying out frequency division processing on the second high-frequency clock signal by a third feedback frequency divider to obtain a third internal feedback signal.

In one embodiment, the frequency multiplication processing of the third high-frequency clock signal by the second circular phase-locked loop to generate a second target clock signal includes: detecting a frequency difference between the third high-frequency clock signal and a fourth internal feedback signal by a second automatic frequency calibration module, and generating a fifth control signal according to the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal; detecting a frequency difference and a phase difference between the third high-frequency clock signal and the fourth internal feedback signal by a fourth phase frequency detector, and generating a sixth control signal according to the frequency difference and the phase difference between the third high-frequency clock signal and the second internal feedback signal; amplifying the sixth control signal by a fourth charge pump, and outputting a fourth amplified signal; collecting the fourth amplified signal by a second voltage control switch, and outputting a corresponding second voltage pulse signal; performing low-pass filtering processing on the second voltage pulse signal by using a fourth loop filter to obtain a fourth filtered signal; outputting, by a second ring voltage controlled oscillator, the second target clock signal according to the fifth control signal and the fourth filtered signal; and performing frequency division processing on the second target clock signal by a fourth feedback frequency divider, and outputting a fourth internal feedback signal.

One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

in the scheme, the low-jitter and high-frequency clock signal is generated by using the inductance capacitance type phase-locked loop, the high-frequency signal is used as an input signal of the annular phase-locked loop, and the output of the high-speed, wide-frequency and low-jitter clock signal is completed by configuring the frequency configuration coefficient of the annular phase-locked loop. Due to the fact that the frequency of the input signal is high, the whole bandwidth of the annular phase-locked loop is greatly improved, and therefore phase noise generated by the loop is restrained. While the phase noise generated by the loop is suppressed, the input clock signal of the annular phase-locked loop has good phase noise, so that the whole clock circuit optimizes the jitter performance of the finally output target clock signal on the whole. In addition, the annular phase-locked loop supports the configuration of frequency configuration coefficients to support clock signals with wider frequency. Compared with the technical problem that a clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art, the whole clock circuit can ensure that the jitter of the output clock signal is greatly reduced while the high frequency and the wide frequency are ensured.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a block diagram of a clock circuit according to a preferred embodiment of the present invention;

fig. 2 is a circuit configuration diagram of a first inductance-capacitance type phase-locked loop in fig. 1;

FIG. 3 is a circuit block diagram of the first annular phase locked loop of FIG. 1;

FIG. 4 is a block diagram of another clock circuit according to the preferred embodiment of the present application;

FIG. 5 is a block diagram of another clock circuit according to the preferred embodiment of the present application;

FIG. 6 is a block diagram of another clock circuit according to the preferred embodiment of the present application;

FIG. 7 is a block diagram of another clock circuit according to the preferred embodiment of the present application;

fig. 8 is a circuit configuration diagram of a second inductance-capacitance type phase-locked loop in fig. 4;

FIG. 9 is a circuit block diagram of the second ring phase locked loop of FIG. 4;

FIG. 10 is a graph illustrating phase noise characteristics of a single circular PLL according to a preferred embodiment of the present application;

FIG. 11 is a diagram illustrating phase noise characteristics of a clock circuit according to a preferred embodiment of the present invention;

FIG. 12 is a flowchart of a clock signal generation method according to a preferred embodiment of the present application;

fig. 13 is a flowchart of another clock signal generating method according to the preferred embodiment of the present application.

Detailed Description

The embodiments of the present application provide a clock circuit and a method for generating a clock signal, so as to solve the technical problem that a clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art.

In order to solve the technical problems, the general idea of the embodiment of the application is as follows:

The technical scheme in the embodiment of the application at least has the following technical effects or advantages:

according to the scheme, the first inductance and capacitance type phase-locked loop is utilized to generate a low-jitter and high-frequency clock signal, the high-frequency signal is used as an input signal of the first annular phase-locked loop, and the high-speed, wide-frequency and low-jitter clock signal is output by configuring the frequency configuration coefficient of the first annular phase-locked loop.

Due to the fact that the frequency of the input signal is high, the whole bandwidth of the first annular phase-locked loop is greatly improved, and therefore phase noise generated by the loop is restrained. While the phase noise generated by the loop itself is suppressed, since the input clock signal of the first ring phase-locked loop itself has a good phase noise, the entire clock circuit optimizes the jitter performance of the finally output first target clock signal as a whole.

In addition, the first annular phase-locked loop supports the configuration of frequency configuration coefficients to support clock signals with wider frequency. Compared with the technical problem that a clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art, the whole clock circuit can ensure that the jitter of the output clock signal is greatly reduced while the high frequency and the wide frequency are ensured.

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

Example one

As shown in fig. 1, the present embodiment provides a clock circuit including:

a first inductance-capacitance type Phase-Locked Loop 1(LC-PLL, Inductor Capacitor-Phase Locked Loop) and a first annular Phase-Locked Loop 2(Ring-PLL, Ring-Phase Locked Loop) which are sequentially cascaded;

the first inductance-capacitance type phase-locked loop 1 is used for carrying out frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal;

the first annular phase-locked loop 2 performs frequency multiplication processing on the first high-frequency clock signal based on a frequency configuration coefficient to generate a first target clock signal, wherein the frequency configuration coefficient is used for configuring the frequency of the first target clock signal.

It should be noted that the first high-frequency clock signal provided by the first lc-pll 1 is a high-frequency clock signal, which has the advantages of high frequency and low jitter (i.e. good phase noise characteristics). The bandwidth of the first annular phase-locked loop 2 is adjusted based on the frequency of the first high-frequency clock signal output by the first inductance-capacitance type phase-locked loop 1, and the higher the bandwidth of the first annular phase-locked loop 2 is, the higher the frequency of the input clock signal that can be locked is, in other words, the higher the frequency of the input clock signal is, the higher the bandwidth of the first annular phase-locked loop 2 needs to be set. As for the specific value of the frequency of the first high-frequency clock signal, it is necessary to adjust the frequency according to the performance requirement of the clock signal finally output by the clock circuit. In summary, in the whole clock circuit, the higher the frequency of the first high-frequency clock signal provided by the first inductance-capacitance type phase-locked loop 1 is, the wider the bandwidth that the first loop-locked loop 2 needs to be configured with, the wider the bandwidth of the first loop-locked loop 2 is, the stronger the phase noise suppression capability of the voltage-controlled oscillator inside the first loop-locked loop 2 is, and the lower the jitter of the clock signal output by the whole clock circuit is in the case where the input clock signal of the first loop-locked loop 2 (i.e., the first high-frequency clock signal output by the first inductance-capacitance type phase-locked loop 1) has low jitter. However, the adjustable bandwidth of the first pll 2 is limited and cannot be increased all the time, and therefore, the first high frequency clock signal provided by the first lc-pll 1 cannot be increased without an upper limit.

As an optional embodiment, the frequency of the first target clock signal is determined according to Fout ═ Fin × (N)/M, where Fout is the frequency of the first target clock signal, Fin is the frequency of the first high-frequency clock signal, M and N are frequency allocation coefficients of the first annular phase-locked loop, a value of N is 1 to 16, and a value of M is 1 to 2.

As an alternative embodiment, the bandwidth of the first ring phase locked loop is one twentieth to one tenth of the frequency of the first high frequency clock signal.

As an alternative embodiment, the first input clock signal is provided by an external crystal oscillator.

In practical implementation, the first input clock signal may be provided by an external crystal oscillator; the frequency configuration coefficient of the first annular phase-locked loop 2 may be configured by a coefficient N and a coefficient M, specifically:

Fout＝Fin*N/M(N＝1～16，M＝1～2)，

wherein Fout is the frequency of the output clock signal of the first annular phase-locked loop 2, corresponding to this embodiment, Fout is the frequency of the first target clock signal, Fin is the frequency of the input clock signal of the first annular phase-locked loop 2, corresponding to this embodiment, Fin is the frequency of the first high-frequency clock signal;

the frequency of the first high-frequency clock signal output by the first lc-pll 1 may be set to be more than 500M, and the bandwidth of the first loop-pll 2 is set to be between one tenth and one twentieth of the input frequency, and corresponding to this embodiment, the frequency of the first high-frequency clock signal output by the first lc-pll 1 is set to be between one tenth and one twentieth of the input frequency, so that the overall performance and stability of the clock circuit loop under this bandwidth are good.

Specifically, for the requirements of the GDDR6 physical interface PHY for the clock generation circuit: it is necessary to provide a high-speed (up to 8GHz), low-jitter, and relatively wide-frequency (5GHz to 8GHz) clock signal. The clock signal can provide a first high-frequency clock signal of 500MHz-1GHz to the first annular phase-locked loop 2 through the first inductance-capacitance type phase-locked loop 1, and finally, the clock signal output of 5GHz-8GHz can be realized through various configurations of the frequency configuration coefficient N/M of the first annular phase-locked loop 2, for example: fout is Fin × N/M (N is 1-16, M is 1-2), for example, Fin is 1GHz, N is 16, M is 2, Fout is 8GHz, and can meet the requirement of the GDDR6 physical interface PHY for clock signals. In the clock circuit, in order to receive a high-frequency signal of 500MHz-1GHz, the bandwidth of the first annular phase-locked loop 2 is adjusted to a high bandwidth corresponding to the frequency of 500MHz-1GHz, namely, the bandwidth of 0.05GHz-0.1GHz, under the high bandwidth, the phase noise of a voltage-controlled oscillator in the first annular phase-locked loop 2 is greatly inhibited, and the final jitter of the clock circuit is further optimized.

It should be noted that the first lc-pll 1 can achieve better jitter, however, the first lc-pll 1 can only support one frequency point, and the requirement of the GDDR6 physical interface PHY for the clock generation circuit is as follows: if multiple frequency points are supported to provide a wide frequency range, low jitter, high frequency clock signal, multiple LC-tank circuits (LC-tank) are commonly used in the prior art to support a wide range of multiple frequency points. This design would result in a large increase in area, which is not conducive to integration.

As an alternative embodiment, as shown in fig. 2, the first lc pll 1 includes:

a first frequency discrimination Phase detector 11 (PFD) for detecting a frequency difference and a Phase difference between the first input clock signal and a first internal feedback signal, and generating a first control signal according to the frequency difference and the Phase difference between the first input clock signal and the first internal feedback signal;

a first Charge Pump 12(CP, Charge Pump), connected to the first frequency discrimination phase detector 11, and configured to amplify the first control signal and output a first amplified signal;

a first loop Filter 13(LPF, Low-pass Filter), connected to the first charge pump 12, and configured to perform Low-pass filtering processing on the first amplified signal and output a first filtered signal;

a first Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO) 14, connected to the first loop filter 13, and configured to output the first high-frequency clock signal according to the first filtered signal;

and the first feedback frequency divider 15 is connected to the first lc voltage-controlled oscillator 14, and is configured to perform frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal.

In the real-time implementation process, the frequency and jitter of the output clock signal of the first lc phase-locked loop 1 can be changed by changing the inductance parameter L and the capacitance parameter C of the first lc voltage-controlled oscillator 14 (mainly changing the capacitance parameter C), so as to achieve the output of high frequency and low jitter.

As an alternative embodiment, as shown in fig. 3, the first ring-shaped phase locked loop 2 comprises:

a first Automatic Frequency Calibration module 27 (AFC) configured to detect a Frequency difference between the first high-Frequency clock signal and a second internal feedback signal, and generate a second control signal according to the Frequency difference between the first high-Frequency clock signal and the second internal feedback signal;

a second Phase Frequency Detector (PFD) 21 for detecting a frequency difference and a Phase difference between the first high frequency clock signal and the second internal feedback signal, and generating a third control signal according to the frequency difference and the Phase difference between the first high frequency clock signal and the second internal feedback signal;

a second Charge Pump 22(CP, Charge Pump), connected to the second phase frequency detector 21, for amplifying the third control signal and outputting a second amplified signal;

a first voltage control switch 23 connected to the second charge pump 22 for outputting a corresponding first voltage pulse signal;

a second loop Filter 24(LPF, Low-pass Filter), connected to the first voltage control switch 23, for performing Low-pass filtering processing on the first voltage pulse signal to obtain a second filtered signal;

a first Ring Voltage-Controlled Oscillator 25 (Ring-VCO), connected to the second loop filter 24, and the first automatic frequency calibration module 27, for outputting the first target clock signal according to the second filtered signal and the second control signal;

and a second feedback frequency divider 26, connected to the first ring-shaped voltage-controlled oscillator 25, for performing frequency division processing on the first target clock signal and outputting the second internal feedback signal.

Specifically, the first automatic frequency calibration module 27 is connected to the first ring-shaped voltage-controlled oscillator 25 through the first voltage-controlled oscillator array switch 251, and when the first ring-shaped phase-locked loop 2 is just powered on, the second control signal is utilized through the automatic calibration function to select an optimal operating frequency of the voltage-controlled oscillator by controlling the first voltage-controlled oscillator array switch 251, so as to ensure that the PLL finally outputs a high-performance and low-jitter target clock signal; the second charge pump 22 is connected with a first charge pump current adjusting switch 221, and the first charge pump current adjusting switch 221 adjusts the current of the second charge pump 22 through a first current control signal; the output end of the first ring-shaped voltage-controlled oscillator 25 is connected with the second feedback frequency divider 26 through a first voltage-controlled oscillator buffer 261 and a first CMOS buffer 263 in sequence, and the first voltage-controlled oscillator buffer 261 is further connected with a first virtual buffer 262; the output signal of the first ring-shaped voltage-controlled oscillator 25 is processed by the first clock divider 28 to output the first target clock signal.

In practical implementation, the adjustment of the bandwidth of the ring-shaped phase-locked loop 2 can be realized by changing the gain coefficient of the second phase frequency detector 21, the gain coefficient of the second charge pump 22, the resistance R/capacitance C of the second loop filter 24, the gain coefficient of the ring-shaped voltage-controlled oscillator 25, and the like.

according to the scheme, the first inductance and capacitance type phase-locked loop is utilized to generate a low-jitter and high-frequency clock signal, the first high-frequency clock signal is used as an input signal of the first annular phase-locked loop, and the output of the high-speed, wide-frequency and low-jitter clock signal is completed through the configuration of the frequency configuration coefficient of the first annular phase-locked loop. Due to the fact that the frequency of the input signal is high, the whole bandwidth of the first annular phase-locked loop is greatly improved, and therefore phase noise generated by the loop is restrained. While the phase noise generated by the loop itself is suppressed, since the input clock signal of the first ring phase-locked loop itself has a good phase noise, the entire clock circuit optimizes the jitter performance of the finally output first target clock signal as a whole. In addition, the first annular phase-locked loop supports the configuration of frequency configuration coefficients to support clock signals with wider frequency. Compared with the technical problem that a clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art, the whole clock circuit can ensure that the jitter of the output clock signal is greatly reduced while the high frequency and the wide frequency are ensured.

Example two

As shown in fig. 4, the present embodiment provides a clock circuit including:

the second inductance and capacitance type phase-locked loop 3, the frequency divider 5 and the second annular phase-locked loop 4 are sequentially cascaded;

the second inductance-capacitance type phase-locked loop 3 is used for performing frequency multiplication processing on a second input clock signal to generate a second high-frequency clock signal;

the frequency divider 5 is configured to perform frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal;

and the second annular phase-locked loop 4 performs frequency multiplication processing on the third high-frequency clock signal based on a frequency configuration coefficient to generate a second target clock signal, wherein the frequency configuration coefficient is used for configuring the frequency of the second target clock signal.

As an alternative embodiment, the frequency of the second target clock signal is determined according to Fout ═ Fin × (N)/M, where Fout is the frequency of the second target clock signal, Fin is the frequency of the third high-frequency clock signal, M and N are frequency allocation coefficients of the first annular phase-locked loop, N ═ 1 to 16, and M ═ 1 to 2.

As an alternative embodiment, the bandwidth of the second ring phase locked loop is set to be one twentieth of the frequency of the third high frequency clock signal to one tenth of the frequency of the third high frequency clock signal.

As an alternative embodiment, the second input clock signal is provided by an external crystal oscillator.

In practical implementation, the second input clock signal may be provided by an external crystal oscillator, and the output frequency of the second ring pll 4 is configured by a frequency configuration coefficient N, M, specifically, Fout is Fin × N/M (N is 1 to 16, M is 1 to 2), where Fout is the frequency of the output clock signal of the second ring pll 4, here, the frequency of the second target clock signal, and Fin is the frequency of the input clock signal of the second ring pll 4, here, the frequency of the third high frequency clock signal.

It should be noted that the third high frequency clock signal frequency-divided by the frequency divider 5 can further reduce the jitter of the clock signal compared to the second high frequency clock signal. Jitter exists at each rising edge of the clock signal, the high-frequency clock signal has more rising edges than the low-frequency clock signal, therefore, the low-frequency signal after frequency division reduces the jitter originally appearing at each rising edge, and the jitter of the clock signal is reduced.

The second high frequency clock signal provided by the second lc-pll 3 is a high frequency clock signal, which has the advantages of high frequency and low jitter (i.e., good phase noise characteristics). The third high frequency clock signal divided by the frequency divider 5 has lower jitter (i.e., good phase noise characteristics). The bandwidth of the second ring phase-locked loop 4 is adjusted based on the frequency of the third high-frequency clock signal divided by the frequency divider 5, and the higher the bandwidth of the second ring phase-locked loop 4 is, the higher the frequency of the input clock signal that can be locked is, in other words, the higher the frequency of the input clock signal is, the higher the bandwidth of the second ring phase-locked loop 4 needs to be set. As for specific values of the frequencies of the second high-frequency clock signal and the third high-frequency clock signal, it is necessary to adjust according to performance requirements of the clock signal finally output by the clock circuit, and in general, in the entire clock circuit, the higher the frequency of the third high-frequency clock signal provided by the frequency divider 5 is, the wider the bandwidth that the second ring phase-locked loop 4 needs to be configured is, the wider the bandwidth of the second ring phase-locked loop 4 is, the stronger the phase noise suppression capability of the voltage-controlled oscillator inside the second ring phase-locked loop 4 is, and in a case where the input clock signal of the second ring phase-locked loop 4 (i.e., the third high-frequency clock signal output by the frequency divider 5) has low jitter, the lower the jitter of the clock signal output by the entire clock circuit is. The lower the jitter of the clock signal output by the entire clock circuit. The adjustable bandwidth of the second ring phase locked loop 4 is limited and cannot be increased all the time, and therefore the frequency of the third high frequency clock signal provided by the frequency divider 5 cannot be increased without an upper limit.

In practical implementation, the second input clock signal can be provided by an external crystal oscillator; the output frequency of the second ring-shaped phase-locked loop 4 is configured by a frequency configuration coefficient N, M, specifically, Fout is Fin × N/M (N is 1-16, M is 1-2), where Fout is the frequency of the output clock signal of the second ring-shaped phase-locked loop 4, which corresponds to the present embodiment, Fout is the frequency of the second target clock signal, Fin is the frequency of the input clock signal of the second ring-shaped phase-locked loop 4, which corresponds to the present embodiment, Fin is the frequency of the third high-frequency clock signal; the frequency of the second high-frequency clock signal output by the second lc-pll 3 may be set to be higher than 4GHz, the frequency of the third high-frequency clock signal output by the frequency divider 5 may be set to be higher than 500MHz, the bandwidth of the second annular pll 4 is set to be between one tenth and one twentieth of the input frequency, and corresponding to the present embodiment, the bandwidth is set to be between one tenth and one twentieth of the frequency of the third high-frequency clock signal output by the frequency divider 5, and the overall performance and stability of the clock circuit loop under this bandwidth are both good.

Specifically, for the requirements of the GDDR6 physical interface PHY for the clock generation circuit: it is necessary to provide a high-speed (up to 8GHz), low-jitter, and relatively wide-frequency (5GHz to 8GHz) clock signal. The clock circuit provides a second input clock signal with low frequency and low jitter through an external crystal oscillator, the second input clock signal is input into a second inductance and capacitance type phase-locked loop 3, a second high-frequency clock signal with 8GHz is provided for a frequency divider 5 through the second inductance and capacitance type phase-locked loop 3, the frequency divider 5 divides the frequency of the second high-frequency clock signal, a third high-frequency clock signal with 500MHz-1GHz is provided for a second annular phase-locked loop 4, and finally, the clock signal output with 5GHz-8GHz can be realized through various configurations of a frequency configuration coefficient N/M of the second annular phase-locked loop 4, for example: fout is Fin × N/M (N is 1-16, M is 1-2), for example, Fin is 1GHz, N is 16, M is 2, Fout is 8GHz, and can meet the requirement of the GDDR6 physical interface PHY for clock signals. In the clock circuit, in order to receive the high frequency signal of 500MHz-1GHz, the bandwidth of the second ring phase-locked loop 4 is adjusted to a high bandwidth corresponding to the frequency of 500MHz-1GHz, that is, a bandwidth of 0.05GHz-0.1GHz (which is set to be one tenth of the frequency of the second high frequency clock signal), under which the phase noise of the voltage-controlled oscillator VCO inside the second ring phase-locked loop 4 is greatly suppressed, and the final jitter of the clock circuit is further optimized, referring to the phase noise characteristic curves of fig. 10 and 11, fig. 11 is the phase noise characteristic of the second ring phase-locked loop 4 in the clock circuit, compared with the phase noise characteristic of the second ring phase-locked loop 4 alone in fig. 10, the phase noise characteristics of LPFs, VCOs, and CPs in the loop in the clock circuit are suppressed to different degrees, especially the phase noise characteristic of the VCO of the second ring phase-locked loop 4 is suppressed, the final jitter Jrms of the clock circuit is 0.86ps, while the jitter Jrms of the second ring pll 4 alone is 1.34 ps.

As an alternative embodiment, the number of the second ring phase-locked loops 4 is two or more, and the two or more second ring phase-locked loops 4 have different frequency configuration coefficients; the frequency configuration coefficient is used for configuring the frequency of the second target clock signal.

The input of each second ring phase locked loop 4 is connected to the output of the frequency divider 5.

For a clock circuit with only one second ring-shaped phase-locked loop 4, a clock signal with only one frequency can be output at the same time, and to realize the output of a plurality of frequency points, the frequency configuration coefficient of the second ring-shaped phase-locked loop 4 needs to be adjusted at any time. The present embodiment is configured with a plurality of second ring phase-locked loops 4 having different frequency configuration coefficients so as to output clock signals of various frequencies simultaneously.

As shown in fig. 5, a block diagram of a clock circuit with two second ring-shaped phase-locked loops 4 is provided, and the connection relationship is shown in the figure and is not described herein.

As an alternative embodiment, the number of the frequency dividers 5 is two or more, and the two or more frequency dividers 5 have different division coefficients;

the input end of each frequency divider 5 is connected with the output end of the second inductance and capacitance type phase-locked loop 3, and the output end of each frequency divider 5 is connected with the input end of the second annular phase-locked loop 4.

Compared with a clock circuit with only one frequency divider 5, the present embodiment implements output of the third high-frequency clock signals of different frequency points by configuring a plurality of frequency dividers 5 with different frequency division coefficients, and implements output of the clock signals of a wider frequency range after the third high-frequency clock signals with different frequencies are multiplied by the same second annular phase-locked loop 4. It should be noted that, in this embodiment, the power supply of the frequency divider 5 is controlled to turn on or off the frequency divider 5 to determine whether to enable the frequency divider 5 to generate the third high frequency clock signal, or a selector may be provided after the frequency divider 5 to select the frequency divider 5 to be used.

As shown in fig. 6, a block diagram of a clock circuit with two frequency dividers 5 and one second ring phase-locked loop 4 is provided, and the connection relationship is shown as shown in the figure and is not described herein.

As an alternative embodiment, the number of the second ring-shaped phase-locked loops 4 is two or more, and the two or more second ring-shaped phase-locked loops 4 correspond to the two or more frequency dividers 5 one to one; wherein two or more of the second ring phase locked loops 4 have the same frequency configuration coefficient, and the frequency configuration coefficient is used for configuring the frequency of the second target clock signal.

For a clock circuit with only one second ring-shaped phase-locked loop 4, a clock signal with only one frequency can be output at the same time, and to realize the output of a plurality of frequency points, the frequency configuration coefficient of the second ring-shaped phase-locked loop 4 needs to be adjusted at any time. In the present embodiment, a plurality of frequency dividers 5 with different frequency division coefficients are configured to achieve simultaneous output of third high-frequency clock signals at different frequency points, and for the third high-frequency clock signals with different frequencies, after frequency multiplication is performed on the third high-frequency clock signals respectively by second annular phase-locked loops 4 with the same frequency configuration coefficient, clock signals with various frequencies can be output simultaneously.

As shown in fig. 7, a block diagram of a clock circuit with two frequency dividers 5 and two second ring-shaped phase-locked loops 4 is provided, and the connection relationship is as shown in the figure, which is not described herein, and the frequency configuration coefficients for the two second ring-shaped phase-locked loops 4 in this embodiment are the same.

As an alternative embodiment, the number of the second ring-shaped phase-locked loops 4 is two or more, and the two or more second ring-shaped phase-locked loops 4 correspond to the two or more frequency dividers 5 one to one; wherein two or more of the second ring phase locked loops 4 have different frequency configuration coefficients, and the frequency configuration coefficients are used for configuring the frequency of the second target clock signal.

As shown in fig. 7, a block diagram of a clock circuit with two frequency dividers 5 and two second ring-shaped phase-locked loops 4 is provided, and the connection relationship is shown in the figure, which is not described herein, and the frequency configuration coefficients for the two second ring-shaped phase-locked loops 4 in this embodiment are different.

For a clock circuit with only one second ring-shaped phase-locked loop 4, a clock signal with only one frequency can be output at the same time, and to realize the output of a plurality of frequency points, the frequency configuration coefficient of the second ring-shaped phase-locked loop 4 needs to be adjusted at any time. In the present embodiment, the frequency dividers 5 with different frequency division coefficients are configured to simultaneously output the third high-frequency clock signals at different frequency points, and for the third high-frequency clock signals with different frequencies, after frequency multiplication is performed on the third high-frequency clock signals respectively by the second annular phase-locked loops 4 with different frequency configuration coefficients, compared with the previous embodiment, simultaneous output of clock signals with a wider frequency range can be realized.

As an alternative embodiment, as shown in fig. 8, the second lc pll 3 includes:

a third phase frequency detector 31 for detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal, and generating a fourth control signal corresponding to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal;

the third charge pump 32 is connected to the third phase frequency detector 31, and configured to amplify the fourth control signal and output a third amplified signal;

a third loop filter 33, connected to the third charge pump 32, for performing low-pass filtering processing on the third amplified signal and outputting a third filtered signal;

a second lc voltage-controlled oscillator 34, connected to the third loop filter 33, for outputting the second high-frequency clock signal with a frequency corresponding to the third filtered signal according to the third filtered signal;

and a third feedback frequency divider 35, connected to the second lc voltage-controlled oscillator 34, and configured to perform frequency division processing on the second high-frequency clock signal to obtain the third internal feedback signal.

As an alternative embodiment, as shown in fig. 9, the second ring phase locked loop 4 includes:

a second automatic frequency calibration module 47, configured to detect a frequency difference between the third high-frequency clock signal and a fourth internal feedback signal, and generate a fifth control signal corresponding to the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal;

a fourth phase frequency detector 41, configured to detect a frequency difference and a phase difference between the third high-frequency clock signal and the fourth internal feedback signal, and generate a sixth control signal corresponding to the frequency difference and the phase difference between the third high-frequency clock signal and the fourth internal feedback signal;

the fourth charge pump 42 is connected to the fourth phase frequency detector 41, and is configured to amplify the sixth control signal and output a fourth amplified signal;

the second voltage control switch 43 is connected to the fourth charge pump 42, and is configured to collect the fourth amplified signal and output a corresponding second voltage pulse signal;

a fourth loop filter 44, connected to the second voltage control switch 43, for performing low-pass filtering processing on the second voltage pulse signal to obtain a fourth filtered signal;

a second ring voltage controlled oscillator 45 coupled to the fourth loop filter 44 and the second automatic frequency calibration module 47, for outputting the second target clock signal according to the fourth filtered signal and the fifth control signal;

a fourth feedback frequency divider 546, connected to the second ring-shaped voltage-controlled oscillator 45, for dividing the frequency of the second target clock signal and outputting the fourth internal feedback signal.

Specifically, the second automatic frequency calibration module 47 is connected to the second ring-shaped voltage-controlled oscillator 45 through the second voltage-controlled oscillator array switch 451, and when the second ring-shaped phase-locked loop 4 is just powered on, the optimal operating frequency of the voltage-controlled oscillator is selected through an automatic calibration function by using the fifth control signal and controlling the second voltage-controlled oscillator array switch 451, so as to ensure that the PLL finally outputs a second target clock signal with high performance and low jitter; the fourth charge pump 42 is connected to a second charge pump current adjusting switch 421, and the second charge pump current adjusting switch 421 adjusts the current of the fourth charge pump 42 according to a second current control signal; the output terminal of the second ring-shaped vco 45 is connected to the fourth feedback frequency divider 546 sequentially through the second vco buffer 461 and the second CMOS buffer 463, and the second vco buffer is further connected to the second dummy buffer 462; the output signal of the second ring voltage controlled oscillator 45 passes through the second clock divider 48 to output the second target clock signal.

in the scheme, a second inductance and capacitance type phase-locked loop is utilized to generate a low-jitter and high-frequency clock signal, the second high-frequency clock signal is input into a frequency divider for frequency division to obtain a high-frequency clock signal with relatively low jitter, the third high-frequency clock signal is used as an input signal of a second annular phase-locked loop, and the output of the high-speed, wide-frequency and low-jitter clock signal is completed by configuring the frequency configuration coefficient of the second annular phase-locked loop. The frequency divider divides the frequency of the output signal of the second inductance and capacitance type phase-locked loop, so that the jitter can be relatively reduced; in addition, the input signal frequency of the second annular phase-locked loop is high, the overall bandwidth of the second annular phase-locked loop is greatly improved, so that the phase noise generated by the loop is suppressed, and meanwhile, the input clock signal of the second annular phase-locked loop has better phase noise, so that the jitter performance of the finally output second target clock signal is optimized on the whole clock circuit. In addition, the second ring phase-locked loop supports the configuration of the frequency configuration coefficients to support clock signals of wider frequencies. Compared with the technical problem that a clock signal with high speed, wide frequency and low jitter cannot be provided in the prior art, the whole clock circuit can ensure that the jitter of the output clock signal is greatly reduced while the high frequency and the wide frequency are ensured.

EXAMPLE III

As shown in fig. 12, the present embodiment provides a clock signal generation method including:

step S101: receiving a first input clock signal by a first inductance and capacitance type phase-locked loop, and carrying out frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal;

step S102: the first annular phase-locked loop carries out frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal.

It should be noted that the first high-frequency clock signal generated by the first lc-pll is a high-frequency clock signal, which has the advantages of high frequency and low jitter (i.e., good phase noise characteristics). The bandwidth of the first annular phase-locked loop is adjusted based on the frequency of the first high-frequency clock signal output by the first inductance-capacitance type phase-locked loop, and the higher the bandwidth of the first annular phase-locked loop is, the higher the frequency of the input clock signal that can be locked is, in other words, the higher the frequency of the input clock signal is, the higher the bandwidth of the first annular phase-locked loop needs to be set. As for the specific value of the frequency of the first high-frequency clock signal, it needs to be adjusted according to the performance requirement of the finally output clock signal. In summary, in the clock signal generation process, the higher the frequency of the first high-frequency clock signal provided by the first inductance-capacitance type phase-locked loop is, the wider the bandwidth that the first loop-locked loop needs to be configured, the wider the bandwidth of the first loop-locked loop is, the stronger the phase noise suppression capability of the voltage-controlled oscillator inside the first loop-locked loop is, and the lower the jitter of the finally output first target clock signal is in the case that the input clock signal of the first loop-locked loop (i.e., the first high-frequency clock signal output by the first inductance-capacitance type phase-locked loop 1) has low jitter. However, the adjustable bandwidth of the first pll is limited and cannot be increased all the time, and therefore, the first high frequency clock signal provided by the first lc-pll cannot be increased without an upper limit.

As an optional embodiment, the frequency of the first target clock signal is determined according to Fout ═ Fin × (N)/M, where Fout is the frequency of the first target clock signal, Fin is the frequency of the first high-frequency clock signal, M and N are frequency allocation coefficients of the first annular phase-locked loop, the value of N is 1 to 16, and the value of M is 1 to 2.

As an alternative embodiment, the bandwidth of the first ring phase locked loop is set to be one twentieth to one tenth of the frequency of the first high frequency clock signal.

In practical implementation, the first input clock signal may be provided by an external crystal oscillator; the frequency configuration coefficient of the first annular phase-locked loop can be configured by a coefficient N and a coefficient M, specifically:

Fout＝Fin*N/M(N＝1～16，M＝1～2)，

fout is the frequency of the output clock signal of the first annular phase-locked loop, corresponding to this embodiment, Fout is the frequency of the first target clock signal, Fin is the frequency of the input clock signal of the first annular phase-locked loop, corresponding to this embodiment, Fin is the frequency of the first high-frequency clock signal;

the frequency of the first high-frequency clock signal output by the first lc-pll may be set to be more than 500M, and the bandwidth of the first loop-pll may be set to be between one tenth and one twentieth of the input frequency, which corresponds to this embodiment.

Specifically, for the requirement of GDDR6 physical interface PHY for clock signals: it is necessary to provide a high-speed (up to 8GHz), low-jitter, and relatively wide-frequency (5GHz to 8GHz) clock signal. The clock signal can provide a first high-frequency clock signal of 500MHz-1GHz to a first annular phase-locked loop through a first inductance-capacitance type phase-locked loop, and finally, the clock signal output of 5GHz-8GHz can be realized through various configurations of a frequency configuration coefficient N/M of the first annular phase-locked loop, for example: fout is Fin × N/M (N is 1-16, M is 1-2), for example, Fin is 1GHz, N is 16, M is 2, Fout is 8GHz, and can meet the requirement of the GDDR6 physical interface PHY for clock signals. In the scheme, in order to receive a high-frequency signal of 500MHz-1GHz, the bandwidth of the first annular phase-locked loop is adjusted to be a high bandwidth corresponding to the frequency of 500MHz-1GHz, namely, the bandwidth of 0.05GHz-0.1GHz, under the high bandwidth, the phase noise of a voltage-controlled oscillator in the first annular phase-locked loop is greatly inhibited, and the final jitter of the clock circuit is further optimized.

As an alternative embodiment, step S101 includes:

receiving and detecting a frequency difference and a phase difference between a first input clock signal and a first internal feedback signal by a first frequency discrimination phase detector, and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal;

amplifying the first control signal by a first charge pump, and outputting a first amplified signal;

performing low-pass filtering processing on the first amplified signal by a first loop filter, and outputting a first filtered signal;

outputting a first high-frequency clock signal by a first inductance-capacitance type voltage-controlled oscillator according to a first filtering signal;

and carrying out frequency division processing on the first high-frequency clock signal by the first feedback frequency divider to obtain a first internal feedback signal.

In the real-time implementation process, the frequency and jitter of the output clock signal of the first inductance-capacitance type phase-locked loop can be changed by changing the inductance parameter L and the capacitance parameter C of the first inductance-capacitance type voltage-controlled oscillator (mainly changing the capacitance parameter C), so that the output of high frequency and low jitter is realized.

As an alternative embodiment, step S102 includes:

detecting a frequency difference between the first high-frequency clock signal and the second internal feedback signal by the first automatic frequency calibration module, and generating a second control signal according to the frequency difference between the first high-frequency clock signal and the second internal feedback signal;

detecting a frequency difference and a phase difference between the first high-frequency clock signal and the second internal feedback signal by the second phase frequency detector, and generating a third control signal according to the frequency difference and the phase difference between the first high-frequency clock signal and the second internal feedback signal;

amplifying the third control signal by a second charge pump, and outputting a second amplified signal;

collecting the second amplified signal by a first voltage control switch, and outputting a corresponding first voltage pulse signal;

carrying out low-pass filtering processing on the first voltage pulse signal by a second loop filter to obtain a second filtered signal;

outputting, by the first ring-shaped voltage-controlled oscillator, a first target clock signal according to the second filtered signal and the second control signal;

and the second feedback frequency divider performs frequency division processing on the first target clock signal and outputs a second internal feedback signal.

In the practical implementation process, the adjustment of the bandwidth of the annular phase-locked loop can be realized by changing the gain coefficient of the second phase frequency detector, the gain coefficient of the second charge pump, the resistor R/capacitor C of the second loop filter, the gain coefficient of the annular voltage-controlled oscillator and the like.

Example four

As shown in fig. 13, the present embodiment provides a method for generating a clock signal, including:

step S201: receiving a second input clock signal by a second inductance capacitance type phase-locked loop, and carrying out frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal;

step S202: performing frequency division processing on the second high-frequency clock signal by a frequency divider to generate a third high-frequency clock signal;

it should be noted that, compared with the second high-frequency clock signal, the third high-frequency clock signal divided by the frequency divider can further reduce the jitter of the clock signal. Jitter exists at each rising edge of the clock signal, the high-frequency clock signal has more rising edges than the low-frequency clock signal, therefore, the low-frequency signal after frequency division reduces the jitter originally appearing at each rising edge, and the jitter of the clock signal is reduced.

Step S203: and the second annular phase-locked loop carries out frequency multiplication processing on the third high-frequency clock signal to generate a second target clock signal.

As an optional embodiment, the frequency of the second target clock signal is determined according to Fout ═ Fin × N/M, where Fout is the frequency of the second target clock signal, Fin is the frequency of the third high-frequency clock signal, M and N are frequency allocation coefficients of the first annular phase-locked loop, N is 1 to 16, and M is 1 to 2.

It should be noted that the second high-frequency clock signal provided by the second lc-pll is a high-frequency clock signal, which has the advantages of high frequency and low jitter (i.e., good phase noise characteristics). The third high frequency clock signal divided by the frequency divider has lower jitter (i.e., good phase noise characteristics). The bandwidth of the second annular phase-locked loop is adjusted based on the frequency of the third high-frequency clock signal after frequency division by the frequency divider, and the higher the bandwidth of the second annular phase-locked loop is, the higher the frequency of the input clock signal that can be locked is, in other words, the higher the frequency of the input clock signal is, the higher the bandwidth of the second annular phase-locked loop needs to be set. As for specific values of the frequencies of the second high-frequency clock signal and the third high-frequency clock signal, the specific values need to be adjusted according to performance requirements of the finally output clock signal, in general, in the clock signal generation process, the higher the frequency of the third high-frequency clock signal provided by the frequency divider is, the wider the bandwidth that the second ring-shaped phase-locked loop needs to be configured is, the wider the bandwidth of the second ring-shaped phase-locked loop is, the stronger the phase noise suppression capability of the voltage-controlled oscillator inside the second ring-shaped phase-locked loop is, and the lower the jitter of the finally output second target clock signal is in the case that the input clock signal of the second ring-shaped phase-locked loop (i.e., the third high-frequency clock signal output by the frequency divider). The adjustable bandwidth of the second ring phase locked loop is limited and cannot be increased all the time, and therefore, the frequency of the third high frequency clock signal provided by the frequency divider cannot be increased without an upper limit.

In practical implementation, the second input clock signal can be provided by an external crystal oscillator; the output frequency of the second annular phase-locked loop is configured by a frequency configuration coefficient N, M, specifically, Fout is Fin × N/M (N is 1-16, M is 1-2), where Fout is the frequency of the output clock signal of the second annular phase-locked loop, corresponding to this embodiment, Fout is the frequency of the second target clock signal, Fin is the frequency of the input clock signal of the second annular phase-locked loop, corresponding to this embodiment, Fin is the frequency of the third high-frequency clock signal; the frequency of the second high-frequency clock signal output by the second inductance-capacitance type phase-locked loop can be set to be more than 4GHz, the frequency of the third high-frequency clock signal output by the frequency divider can be set to be more than 500MHz, the bandwidth of the second annular phase-locked loop is set to be between one tenth and one twentieth of the input frequency, and corresponding to the embodiment, the frequency of the third high-frequency clock signal output by the frequency divider is set to be between one tenth and one twentieth of the input frequency, so that the overall performance and the stability of the clock circuit loop under the bandwidth are good.

Specifically, for the requirement of GDDR6 physical interface PHY for clock signals: it is necessary to provide a high-speed (up to 8GHz), low-jitter, and relatively wide-frequency (5GHz to 8GHz) clock signal. In this embodiment, a low-frequency and low-jitter second input clock signal is provided by an external crystal oscillator, the second input clock signal is input into a second lc-pll, an 8GHz second high-frequency clock signal is provided by the second lc-pll to a frequency divider, the frequency divider divides the second high-frequency clock signal, a 500MHz-1GHz third high-frequency clock signal is provided to a second pll, and a 5GHz-8GHz clock signal output can be finally realized by configuring multiple configurations of a coefficient N/M for a frequency of the second pll, for example: fout is Fin × N/M (N is 1-16, M is 1-2), for example, Fin is 1GHz, N is 16, M is 2, Fout is 8GHz, and can meet the requirement of the GDDR6 physical interface PHY for clock signals. In this embodiment, in order to receive a high-frequency signal of 500MHz-1GHz, the bandwidth of the second ring-shaped phase-locked loop is adjusted to a high bandwidth corresponding to the frequency of 500MHz-1GHz, that is, a bandwidth of 0.05GHz-0.1GHz (which is set to be one tenth of the frequency of the second high-frequency clock signal), under the high bandwidth, the phase noise of the voltage-controlled oscillator VCO inside the second ring-shaped phase-locked loop is greatly suppressed, and the final jitter is further optimized, referring to phase noise characteristic curves of fig. 10 and 11, fig. 11 is the phase noise characteristic of the second ring-shaped phase-locked loop in the present clock circuit, compared with the phase noise characteristic of the second ring-shaped phase-locked loop alone in fig. 10, the phase noise characteristics of LPFs, VCOs, and CPs in the present clock circuit are suppressed to different degrees, particularly the phase noise characteristic of the VCO of the second ring-shaped phase-locked loop is suppressed, and the final jitter of the present clock circuit is 0.86, and the jitter Jrms of the second ring phase locked loop alone is 1.34 ps.

As an alternative embodiment, step S201 includes:

receiving and detecting a frequency difference and a phase difference between the second input clock signal and the third internal feedback signal by the third phase frequency detector, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal;

amplifying the fourth control signal by a third charge pump, and outputting a third amplified signal;

performing low-pass filtering processing on the third amplified signal by a third loop filter, and outputting a third filtered signal;

outputting a second high-frequency clock signal by a second inductance-capacitance type voltage-controlled oscillator according to the third filtering signal;

and carrying out frequency division processing on the second high-frequency clock signal by a third feedback frequency divider to obtain a third internal feedback signal.

As an alternative embodiment, step S203 includes:

detecting a frequency difference between the third high-frequency clock signal and the fourth internal feedback signal by the second automatic frequency calibration module, and generating a fifth control signal according to the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal;

detecting a frequency difference and a phase difference between the third high-frequency clock signal and the fourth internal feedback signal by a fourth phase frequency detector, and generating a sixth control signal according to the frequency difference and the phase difference between the third high-frequency clock signal and the second internal feedback signal;

amplifying the sixth control signal by a fourth charge pump, and outputting a fourth amplified signal;

collecting the fourth amplified signal by a second voltage control switch, and outputting a corresponding second voltage pulse signal;

performing low-pass filtering processing on the second voltage pulse signal by using a fourth loop filter to obtain a fourth filtered signal;

outputting, by the second ring voltage controlled oscillator, a second target clock signal based on the fifth control signal and the fourth filtered signal;

the second target clock signal is frequency-divided by a fourth feedback frequency divider, and a fourth internal feedback signal is output.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A clock circuit, comprising:

a first inductance capacitance type phase-locked loop and a first annular phase-locked loop;

the first inductance and capacitance type phase-locked loop is used for carrying out frequency multiplication processing on a first input clock signal to generate a first high-frequency clock signal;

the first annular phase-locked loop is used for carrying out frequency multiplication processing on the first high-frequency clock signal to generate a first target clock signal.

2. The clock circuit of claim 1, wherein the first lc pll comprises:

the first frequency discrimination phase detector is used for detecting the frequency difference and the phase difference between the first input clock signal and a first internal feedback signal and generating a first control signal according to the frequency difference and the phase difference between the first input clock signal and the first internal feedback signal;

the first charge pump is used for amplifying the first control signal and outputting a first amplified signal;

the first loop filter is used for carrying out low-pass filtering processing on the first amplified signal and outputting a first filtered signal;

the first inductance-capacitance type voltage-controlled oscillator is used for outputting the first high-frequency clock signal according to the first filtering signal;

and the first feedback frequency divider is used for carrying out frequency division processing on the first high-frequency clock signal to obtain the first internal feedback signal.

3. The clock circuit of claim 1, wherein the first ring phase locked loop comprises:

a first automatic frequency calibration module, configured to detect a frequency difference between the first high-frequency clock signal and a second internal feedback signal, and generate a second control signal according to the frequency difference between the first high-frequency clock signal and the second internal feedback signal;

a second phase frequency detector for detecting a frequency difference and a phase difference between the first high frequency clock signal and the second internal feedback signal, and generating a third control signal according to the frequency difference and the phase difference between the first high frequency clock signal and the second internal feedback signal;

the second charge pump is used for amplifying the third control signal and outputting a second amplified signal;

the first voltage control switch is used for collecting the second amplified signal and outputting a corresponding first voltage pulse signal;

the second loop filter is used for carrying out low-pass filtering processing on the first voltage pulse signal to obtain a second filtered signal;

a first ring voltage controlled oscillator for outputting the first target clock signal according to the second filtered signal and the second control signal;

and the second feedback frequency divider is used for carrying out frequency division processing on the first target clock signal and outputting a second internal feedback signal.

4. A clock circuit, comprising:

the second inductance and capacitance type phase-locked loop, the frequency divider and the second annular phase-locked loop;

the second inductance and capacitance type phase-locked loop is used for carrying out frequency multiplication processing on a second input clock signal to generate a second high-frequency clock signal;

the frequency divider is used for carrying out frequency division processing on the second high-frequency clock signal to generate a third high-frequency clock signal;

and the second annular phase-locked loop is used for carrying out frequency multiplication processing on the third high-frequency clock signal to generate a second target clock signal.

5. The clock circuit of claim 4, wherein the number of the second ring phase locked loops is two or more, the two or more second ring phase locked loops having different frequency configuration coefficients for configuring the frequency of the second target clock signal;

the input end of each second annular phase-locked loop is connected with the output end of the frequency divider.

6. The clock circuit according to claim 4, wherein the number of the frequency dividers is two or more, the two or more frequency dividers having different division coefficients;

the input end of each frequency divider is connected with the output end of the second inductance and capacitance type phase-locked loop, and the output end of each frequency divider is connected with the input end of the second annular phase-locked loop.

7. The clock circuit of claim 4, wherein the second LC PLL comprises:

a third phase frequency detector for detecting a frequency difference and a phase difference between the second input clock signal and a third internal feedback signal, and generating a fourth control signal according to the frequency difference and the phase difference between the second input clock signal and the third internal feedback signal;

the third charge pump is used for amplifying the fourth control signal and outputting a third amplified signal;

the third loop filter is used for performing low-pass filtering processing on the third amplified signal and outputting a third filtered signal;

the second inductance-capacitance type voltage-controlled oscillator is used for outputting the second high-frequency clock signal according to the third filtering signal;

and the third feedback frequency divider is used for carrying out frequency division processing on the second high-frequency clock signal to obtain a third internal feedback signal.

8. The clock circuit of claim 4, wherein the second ring phase locked loop comprises:

a second automatic frequency calibration module, configured to detect a frequency difference between the third high-frequency clock signal and a fourth internal feedback signal, and generate a fifth control signal according to the frequency difference between the third high-frequency clock signal and the fourth internal feedback signal;

a fourth phase frequency detector, configured to detect a frequency difference and a phase difference between the third high-frequency clock signal and the fourth internal feedback signal, and generate a sixth control signal according to the frequency difference and the phase difference between the third high-frequency clock signal and the second internal feedback signal;

the fourth charge pump is used for amplifying the sixth control signal and outputting a fourth amplified signal;

the second voltage control switch is used for collecting the fourth amplified signal and outputting a corresponding second voltage pulse signal;

the fourth loop filter is used for carrying out low-pass filtering processing on the second voltage pulse signal to obtain a fourth filtering signal;

a second ring voltage controlled oscillator for outputting the second target clock signal in accordance with the fifth control signal and the fourth filtered signal;

and the fourth feedback frequency divider is used for carrying out frequency division processing on the second target clock signal and outputting a fourth internal feedback signal.

9. A clock signal generation method, comprising:

receiving a first input clock signal by a first inductance and capacitance type phase-locked loop, and carrying out frequency multiplication processing on the first input clock signal to generate a first high-frequency clock signal;

and carrying out frequency multiplication processing on the first high-frequency clock signal by using a first annular phase-locked loop to generate a first target clock signal.

10. A method for generating a clock signal, comprising:

receiving a second input clock signal by a second inductance capacitance type phase-locked loop, and carrying out frequency multiplication processing on the second input clock signal to generate a second high-frequency clock signal;

performing frequency division processing on the second high-frequency clock signal by a frequency divider to generate a third high-frequency clock signal;

and performing frequency multiplication processing on the third high-frequency clock signal by using a second annular phase-locked loop to generate a second target clock signal.