CN110855257A - Automatic correction circuit for output offset voltage of class-D power amplifier circuit - Google Patents
Automatic correction circuit for output offset voltage of class-D power amplifier circuit Download PDFInfo
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- CN110855257A CN110855257A CN201911280492.3A CN201911280492A CN110855257A CN 110855257 A CN110855257 A CN 110855257A CN 201911280492 A CN201911280492 A CN 201911280492A CN 110855257 A CN110855257 A CN 110855257A
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
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Abstract
The invention discloses an automatic correction circuit for output offset voltage of a class-D power amplifier circuit, which can automatically detect the deviation of output direct-current voltage when the class-D power amplifier circuit starts to work, and correct the deviation through a control circuit, thereby reducing the POP noise of starting.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to an automatic correction circuit for output offset voltage of a class-D power amplifier circuit.
Background
The class-D power amplifier circuit is a switch-type power amplifier circuit, and the working principle is based on a PWM mode, audio signals are compared with triangular waves, PWM waveforms with pulse widths in direct proportion to the amplitude of the audio signals are output, then the amplitude of the PWM waveforms is amplified, and the amplified PWM waveforms are restored into amplified audio signals after being filtered. Compared with a linear power amplifier circuit, the D-type power amplifier circuit has the characteristics of high efficiency and less heat generation, so that the D-type power amplifier circuit is widely applied to the fields of consumer electronics products such as smart televisions and smart phones.
Because the audio input of the D-type power amplifier circuit can be transmitted only by working on the offset point, the two differential input ends of the D-type power amplifier circuit are both connected with a capacitor, and at the initial stage of power-on starting of the consumer electronic product, the consumer electronic product can charge the capacitors of the two differential input ends of the D-type power amplifier circuit to the offset point, but because the charging speeds of the capacitors of the two differential input ends are different, the two differential input ends can form differential input and amplify and output to form POP noise. Similarly, in the initial stage of power failure of the consumer electronic product, the discharging speeds of the capacitors of the two differential input ends are different, and the two differential input ends also form differential input to form POP noise.
Therefore, various developers and workers adopt different methods to solve the POP noise problem of the class D power amplifier circuit. For example, as disclosed in a chinese patent application, a method and an apparatus for suppressing noise of a class D power amplifier and a class D power amplifier for suppressing noise (patent publication No. CN200710199380.6), a method for suppressing noise by using a delay method is mainly aimed at suppressing POP noise caused by a voltage difference generated due to mismatching of external input signals during a power-on process. As another example, a method for suppressing noise by using a delay method disclosed in chinese patent application "class D power amplifier circuit with POP noise suppression" (patent publication No. CN201510514693.0) aims to suppress POP noise caused by voltage difference due to mismatch of external input signals during power-on process.
However, researchers have further found that the above method does not effectively suppress POP noise caused by adaptation of the circuit itself, based on the method disclosed in the above document. That is, in the prior art, during the power-on and start-up process of the class-D power amplifier circuit, due to the influence of manufacturing process deviation and device mismatch, a dc voltage difference still occurs between the two output terminals under the condition of no input signal, thereby generating POP noise during power-on.
Therefore, it is desirable to provide a novel circuit capable of automatically correcting the output offset voltage of the class D power amplifier circuit.
Disclosure of Invention
The invention aims to provide an automatic output offset voltage correction circuit of a D-type power amplifier circuit, which can automatically detect the deviation of output direct-current voltage when the D-type power amplifier circuit starts to work and correct the deviation through a control circuit so as to reduce the POP noise of starting.
In order to solve the above problems, the present invention provides an automatic correction circuit for output offset voltage of a class D power amplifier circuit, comprising: the power amplifier module comprises a power amplifier circuit; the detection module is electrically connected with the power amplifier module and is used for acquiring the output voltage of the power amplifier circuit and comparing the output voltage with a reference voltage; the control logic module is electrically connected with the detection module and is used for carrying out logic processing according to the comparison result of the output voltage of the power amplification circuit and the reference voltage and outputting a plurality of different control signals; and the execution module is electrically connected with the control logic module and the power amplifier module respectively, and is used for receiving a plurality of different control signals and correspondingly adjusting the resistance value of the resistor array in the power amplifier module according to the control signals so as to enable the difference value between the output voltages of the two output geminate transistors in the power amplifier module to be zero.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the resistor array comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all fixed resistors, and the seventh resistor and the eighth resistor are all variable resistors.
Further, the power amplifier module includes: a first operational amplifier, a second operational amplifier, a first capacitor, a second capacitor, a first comparator, a second comparator, a first gate driver, a second gate driver, a first output pair transistor, a second output pair transistor and the resistor array; one end of the first resistor is electrically connected to a positive input end, and the other end of the first resistor is electrically connected to the first input end of the first operational amplifier and one end of the third resistor, respectively; one end of the second resistor is electrically connected with a negative input end, and the other end of the second resistor is respectively and electrically connected with the second input end of the first operational amplifier and one end of the fourth resistor; a first output end of the first operational amplifier is electrically connected to the other end of the third resistor and one end of the fifth resistor respectively, and a second output end of the first operational amplifier is electrically connected to the other end of the fourth resistor and one end of the sixth resistor respectively; the other end of the fifth resistor is electrically connected to one end of the seventh resistor, one end of the first capacitor and the first input end of the second operational amplifier respectively; the other end of the sixth resistor is electrically connected to one end of the eighth resistor, one end of the second capacitor and the second input end of the second operational amplifier respectively; a first output end of the second operational amplifier is electrically connected to the other end of the first capacitor and a first input end of the first comparator respectively, and a second output end of the second operational amplifier is electrically connected to the other end of the second capacitor and a first input end of the second comparator respectively; the second input end of the first comparator and the second input end of the second comparator both receive a triangular wave signal, the output end of the first comparator is electrically connected to the input end of the first grid driver, and the output end of the second comparator is electrically connected to the input end of the second grid driver; the output end of the first grid driver is electrically connected to the first output pair transistor; the output end of the second grid driver is electrically connected to the second output pair transistor; the other end of the seventh resistor is electrically connected to the first output end of the first output pair transistor, and the other end of the eighth resistor is electrically connected to the second output end of the second output pair transistor.
Further, the first output pair transistor comprises a first switch transistor and a second switch transistor electrically connected with the first switch transistor; the second output pair transistor comprises a third switch transistor and a fourth switch transistor electrically connected with the third switch transistor.
Further, the detection module comprises: the first filter, the second filter, the third comparator and the fourth comparator; the input end of the first filter is electrically connected to the first output end of the first output geminate transistor, and the output end of the first filter is electrically connected to the first input end of the third comparator; the input end of the second filter is electrically connected to the first output end of the second output geminate transistor, and the output end of the second filter is electrically connected to the first input end of the fourth comparator; the second input end of the third comparator and the second input end of the fourth comparator both receive a reference voltage, and the output end of the third comparator and the output end of the fourth comparator are both electrically connected to the control logic module.
Further, the control logic module includes a logic circuit, a first input terminal of the logic circuit is electrically connected to the output terminal of the third comparator, and a second input terminal of the logic circuit is electrically connected to the output terminal of the fourth comparator; the logic circuit is electrically connected to the power amplifier circuit.
Further, the execution module includes: a first output of the logic circuit, a second output of the logic circuit, and a third output of the logic circuit; the first output end of the logic circuit outputs a first control signal to a seventh resistor in the resistor array so as to adjust the resistance value of the seventh resistor; the second output end of the logic circuit outputs a second control signal to an eighth resistor in the resistor array so as to adjust the resistance value of the eighth resistor; and a third output end of the logic circuit outputs a third control signal to a first switch in the power amplifier module, wherein two ends of the first switch are electrically connected to one end of the first resistor and one end of the second resistor respectively.
Further, the first filter and the second filter are both low-pass filters, wherein the low-pass filters include RC-type circuits or RC active filters having operational amplifiers and RC elements.
Further, the third control signal outputs a high enable or a low enable according to a type of the first switch.
Further, the third control signal is electrically connected to the first switch through a delay circuit.
The automatic correction circuit for the output offset voltage of the class D power amplifier circuit has the advantages that when the class D power amplifier circuit starts to work, the automatic correction circuit for the output offset voltage of the class D power amplifier circuit can automatically detect the deviation of the output direct-current voltage, and corrects the deviation through the control circuit, so that the POP noise of starting is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a frame of an output offset voltage automatic correction circuit of a class D power amplifier circuit according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of the automatic output offset voltage correction circuit of the class-D power amplifier circuit according to the embodiment of the present invention.
Fig. 3 is a circuit schematic of the resistor array shown in fig. 2.
Fig. 4 is a circuit schematic of the first filter and the second filter shown in fig. 2.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In this patent document, the drawings discussed below and the embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed in any way to limit the scope of the present disclosure. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. Further, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements.
The terms used in the description of the present invention are only used to describe specific embodiments, and are not intended to show the concept of the present invention. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it is to be understood that terms such as "comprising," "having," and "containing" are intended to specify the presence of stated features, integers, steps, acts, or combinations thereof, as taught in the present specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.
The embodiment of the invention provides an automatic correction circuit for output offset voltage of a class-D power amplifier circuit. The details will be described below separately.
Referring to fig. 1, the present invention provides an output offset voltage auto-calibration circuit of a class D power amplifier circuit, which includes: a power amplifier module 110, a detection module 120, a control logic module 130 and an execution module 140.
Specifically, the power amplifier module 110 includes a power amplifier circuit. The power amplifier circuit is well known to those skilled in the art. In this embodiment, the power amplifier circuit is a class D power amplifier circuit, which is a switch-type power amplifier circuit. The class-D power amplifier circuit works based on a PWM mode, an audio signal is compared with a triangular wave, a PWM waveform with pulse width in direct proportion to the amplitude of the audio signal is output, the amplitude of the PWM waveform is amplified, and the amplified PWM waveform is restored into an amplified audio signal after being filtered.
The detection module 120 is electrically connected to the power amplifier module 110, and the detection module 120 is configured to obtain an output voltage of the power amplifier circuit and compare the output voltage with a reference voltage.
The control logic module 130 is electrically connected to the detection module 120, and the control logic module 130 is configured to perform logic processing according to a comparison result between the output voltage of the power amplifier circuit and the reference voltage, and output a plurality of different control signals. In this embodiment, the number of the control signals is three, but is not limited thereto.
The execution module 140 is electrically connected to the control logic module 130 and the power amplifier module 110, respectively. The execution module 140 is configured to receive a plurality of different control signals (for example, reference numbers CT1, CT2, and CT3 shown in fig. 2), and accordingly adjust the resistance of the resistor array in the power amplifier module 110 according to the control signals, so that the difference between the output voltages of the two pairs of output transistors in the power amplifier module 110 is zero.
Further, the resistor array may increase or decrease the resistance of the corresponding resistor in the resistor array in a stepping manner according to the control signal, so that the difference between the output voltages of the two output pair transistors in the power amplifier module 110 gradually decreases until the difference between the output voltages of the two output pair transistors is zero, that is, the two output pair transistors are equal to each other. Therefore, the problem that in the prior art, due to the influences of manufacturing process deviation and device mismatch in the power-on starting process of the class-D power amplifier circuit, and under the condition of no input signal, the output voltages of two output pair transistors (such as the reference numerals I7 and I8 in fig. 2) still have direct current voltage difference to generate POP noise during power-on can be effectively solved.
Preferably, after the difference between the output voltages of the two output pair transistors is zero, that is, the output voltages are equal to each other, the output voltages of the output pair transistors are further adjusted to be equal to the reference voltage, at this time, the control signal of the control logic module 130 makes the resistor array in a locked state, so that the resistance values of the corresponding resistors in the resistor array are no longer changed. In addition, one of the control signals causes the first switch SW1 in the power amplifier circuit to be switched to an on state, so that the power amplifier circuit can receive an external input signal and is in a normal operating state.
In the present embodiment, the resistor array includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are all fixed resistors, the seventh resistor R7 and the eighth resistor R8 are all variable resistors, and the seventh resistor R7 and the eighth resistor R8 are resistors with adjustable resistance values in the resistor array and are adjusted and controlled by the execution module 140. Of course, in other embodiments, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 may also be designed as variable resistors, and are also used as resistors with adjustable resistance values in a resistor array, and are adjusted and controlled by the executing module 140.
In addition, the seventh resistor R7 and the eighth resistor R8 in the resistor array may further include a parallel resistor array or a series resistor array, respectively, according to actual situations, and the specific structural form is as shown in fig. 3.
Referring to fig. 2, a schematic circuit diagram of the automatic offset voltage correction circuit for the class D power amplifier circuit is shown.
In this embodiment, the power amplifier module 110 includes: a first operational amplifier I1, a second operational amplifier I2, a first capacitor C1, a second capacitor C2, a first comparator I3, a second comparator I4, a first gate driver I5, a second gate driver I6, a first output pair transistor I7, a second output pair transistor I8, and the resistor array (not shown). One end of the first resistor R1 is electrically connected to a positive input terminal INP, and the other end of the first resistor R1 is electrically connected to the first input terminal of the first operational amplifier I1 and one end of the third resistor R3, respectively; one end of the second resistor R2 is electrically connected to a negative input terminal INN, and the other end of the second resistor R2 is electrically connected to the second input terminal of the first operational amplifier I1 and one end of the fourth resistor R4, respectively; a first output terminal of the first operational amplifier I1 is electrically connected to the other terminal of the third resistor R3 and one terminal of the fifth resistor R5, respectively, and a second output terminal of the first operational amplifier I1 is electrically connected to the other terminal of the fourth resistor R4 and one terminal of the sixth resistor R6, respectively; the other end of the fifth resistor R5 is electrically connected to one end of the seventh resistor R7, one end of the first capacitor C1 and the first input end of the second operational amplifier I2, respectively; the other end of the sixth resistor R6 is electrically connected to one end of the eighth resistor R8, one end of the second capacitor C2 and the second input end of the second operational amplifier I2, respectively; a first output terminal of the second operational amplifier I2 is electrically connected to the other terminal of the first capacitor C1 and a first input terminal of the first comparator I3, respectively, and a second output terminal of the second operational amplifier I2 is electrically connected to the other terminal of the second capacitor C2 and a first input terminal of the second comparator I4, respectively; a second input terminal of the first comparator I3 and a second input terminal of the second comparator I4 both receive a triangular wave signal, an output terminal of the first comparator I3 is electrically connected to an input terminal of the first gate driver I5, and an output terminal of the second comparator I4 is electrically connected to an input terminal of the second gate driver I6; the output end of the first gate driver I5 is electrically connected to the first output pair transistor I7; the output end of the second gate driver I6 is electrically connected to the second output pair transistor I8; the other end of the seventh resistor R7 is electrically connected to the first output terminal of the first output pair I7, and the other end of the eighth resistor R8 is electrically connected to the second output terminal of the second output pair I8.
Further, the first output pair transistor I7 includes a first switch transistor and a second switch transistor electrically connected to the first switch transistor. The second output pair transistor I8 includes a third switch transistor and a fourth switch transistor electrically connected to the third switch transistor. In this embodiment, the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are MOS tubes, and in other embodiments, the invention is not limited thereto. That is, the first output pair transistor I7 includes a first MOS transistor M1 and a second MOS transistor M2 electrically connected to the first MOS transistor M1; the second output pair transistor I8 includes a third MOS transistor M3 and a fourth MOS transistor M4 electrically connected to the third MOS transistor M3. Specifically, the gate of the first MOS transistor M1 is electrically connected to the first gate driver I5, the source of the first MOS transistor M1 is electrically connected to the drain of the second MOS transistor M2, and the drain of the first MOS transistor M1 receives an input voltage. The gate of the second MOS transistor M2 is electrically connected to the first gate driver I5, the drain of the second MOS transistor M2 is electrically connected to the source of the first MOS transistor M1, and the source of the second MOS transistor M2 is grounded. The common connection point of the first MOS transistor M1 and the second MOS transistor M2 is electrically connected to the first output terminal of the first output pair transistor I7. Similarly, the gate of the third MOS transistor M3 is electrically connected to the second gate driver I6, the source of the third MOS transistor M3 is electrically connected to the drain of the fourth MOS transistor M4, and the drain of the third MOS transistor M3 receives an input voltage. The gate of the fourth MOS transistor M4 is electrically connected to the second gate driver I6, the drain of the fourth MOS transistor M4 is electrically connected to the source of the third MOS transistor M3, and the source of the fourth MOS transistor M4 is grounded. The common connection point of the third MOS transistor M3 and the fourth MOS transistor M4 is electrically connected to the first output terminal of the second output pair transistor I8. As shown in fig. 2, the first output terminal of the first pair of output transistors I7 and the first output terminal of the second pair of output transistors I8 are coupled to a load (the load is an electronic component, such as a speaker, but not limited thereto).
In this embodiment, the detecting module 120 includes: the filter comprises a first filter I9, a second filter I10, a third comparator I11 and a fourth comparator I12.
An input terminal of the first filter I9 is electrically connected to the first output terminal of the first output pair I7, and an output terminal of the first filter I9 is electrically connected to the first input terminal of the third comparator I11. That is, the input terminal of the first filter I9 is electrically connected to the common node of the first MOS transistor M1 and the second MOS transistor M2.
An input terminal of the second filter I10 is electrically connected to the first output terminal of the second output pair I8, and an output terminal of the second filter I10 is electrically connected to the first input terminal of the fourth comparator I12. The input end of the second filter I10 is electrically connected to the common node of the third MOS transistor M3 and the fourth MOS transistor M4.
Wherein the first filter I9 and the second filter I10 are both low pass filters, wherein the low pass filters comprise RC type circuits or RC active filters with operational amplifiers and RC elements, as shown in fig. 4.
A second input terminal of the third comparator I11 and a second input terminal of the fourth comparator I12 both receive a reference voltage, and an output terminal of the third comparator I11 and an output terminal of the fourth comparator I12 are both electrically connected to the control logic module 130.
With reference to fig. 2, in the present embodiment, the control logic module 130 includes a logic circuit I13, a first input terminal of the logic circuit I13 is electrically connected to the output terminal of the third comparator I11, and a second input terminal of the logic circuit I13 is electrically connected to the output terminal of the fourth comparator I12. The logic circuit I13 is electrically connected to the power amplifier circuit.
The execution module 140 includes: a first output terminal of the logic circuit I13, a second output terminal of the logic circuit I13, and a third output terminal of the logic circuit I13; the first output terminal of the logic circuit I13 outputs a first control signal CT1 to a seventh resistor R7 in the resistor array to adjust the resistance of the seventh resistor R7; the second output terminal of the logic circuit I13 outputs a second control signal CT2 to an eighth resistor R8 in the resistor array to adjust the resistance of the eighth resistor R8; a third output terminal of the logic circuit I13 outputs a third control signal CT3 to a first switch SW1 of the power amplifier module 110, wherein two ends of the first switch SW1 are electrically connected to one end of the first resistor R1 and one end of the second resistor R2, respectively.
In this embodiment, further, the third control signal CT3 outputs high enable or low enable according to the type of the first switch SW 1.
In the present embodiment, the third control signal CT3 is directly electrically connected to the first switch SW 1. Of course, in some other embodiments, the third control signal may also be electrically connected to the first switch SW1 through a delay circuit.
After the automatic output offset voltage correcting circuit of the class D power amplifier circuit is electrified, the first switch SW1 is in a closed state so as to prevent external input signals (through positive and negative input ends) from entering the power amplifier circuit in the chip, and at the moment, the voltage difference value between the output voltages of the two output geminate transistors is generated by the chip due to manufacturing process deviation and component mismatching. The two groups of output tube voltages are compared with a reference level after low-pass filtering action of a first filter I9 and a second filter I10, and three logic control signals CT1, CT2 and CT3 are generated. Wherein the CT1 and CT2 respectively control a seventh resistor R7 and an eighth resistor R8 in the resistor array. The resistor array increases or decreases the corresponding resistance value step by step according to the control signal, so that the voltage difference of the output voltages of the output pair transistors is gradually reduced. When the output voltages of the output pair transistors are the same as the reference level, the first control signal CT1 and the second control signal CT2 of the control logic circuit I13 make the resistor array in a locked state, the resistance values of the corresponding resistors in the resistor array do not change any more, and the third control signal CT3 makes the first switch SW1 switch to an open state, so that the chip can receive an external input signal and is in a normal working state.
The automatic correction circuit for the output offset voltage of the class D power amplifier circuit has the advantages that when the class D power amplifier circuit starts to work, the automatic correction circuit for the output offset voltage of the class D power amplifier circuit can automatically detect the deviation of the output direct-current voltage, and corrects the deviation through the control circuit, so that the POP noise of starting is reduced.
In addition, on the basis of the technical scheme, the invention can be further improved as follows.
The first switch SW1 is used to prevent external input signals from entering the chip during power-up, and the first switch SW1 is connected to the first resistor R1 and the second resistor R2. This signal may also be connected to the near differential operational amplifier terminals of the first resistor R1 and the second resistor R2.
As a refinement of the present invention, the third control signal CT3 controls the first switch SW 1. This signal can control the first switch SW1 and at the same time, the third resistor R3 and the fourth resistor R4 can be short-circuited during the power-up process.
As a modification of the present invention, the seventh resistor R7 and the eighth resistor R8 are objects (resistor arrays) of the execution module 140, and the fifth resistor R5 and the sixth resistor R6 may also be implemented as resistor arrays.
As a modification of the present invention, the seventh resistor R7 and the eighth resistor R8 are objects (resistor arrays) of the execution module 140, and may also be implemented by the third resistor R3 and the fourth resistor R4 as resistor arrays.
As a modification of the present invention, the seventh resistor R7 and the eighth resistor R8 are objects (resistor arrays) of the execution module 140, and may be implemented by the first resistor R1 and the second resistor R2 as resistor arrays.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. The utility model provides a D class power amplifier circuit output offset voltage automatic correction circuit which characterized in that includes:
the power amplifier module comprises a power amplifier circuit;
the detection module is electrically connected with the power amplifier module and is used for acquiring the output voltage of the power amplifier circuit and comparing the output voltage with a reference voltage;
the control logic module is electrically connected with the detection module and is used for carrying out logic processing according to the comparison result of the output voltage of the power amplification circuit and the reference voltage and outputting a plurality of different control signals;
and the execution module is electrically connected with the control logic module and the power amplifier module respectively, and is used for receiving a plurality of different control signals and correspondingly adjusting the resistance value of the resistor array in the power amplifier module according to the control signals so as to enable the difference value between the output voltages of the two output geminate transistors in the power amplifier module to be zero.
2. The automatic correction circuit for output offset voltage of class-D power amplifier circuit according to claim 1, wherein said resistor array comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor; the first resistor, the second resistor, the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all fixed resistors, and the seventh resistor and the eighth resistor are all variable resistors.
3. The class-D power amplifier circuit output offset voltage auto-calibration circuit of claim 2, wherein the power amplifier module comprises: a first operational amplifier, a second operational amplifier, a first capacitor, a second capacitor, a first comparator, a second comparator, a first gate driver, a second gate driver, a first output pair transistor, a second output pair transistor and the resistor array; one end of the first resistor is electrically connected to a positive input end, and the other end of the first resistor is electrically connected to the first input end of the first operational amplifier and one end of the third resistor, respectively; one end of the second resistor is electrically connected with a negative input end, and the other end of the second resistor is respectively and electrically connected with the second input end of the first operational amplifier and one end of the fourth resistor; a first output end of the first operational amplifier is electrically connected to the other end of the third resistor and one end of the fifth resistor respectively, and a second output end of the first operational amplifier is electrically connected to the other end of the fourth resistor and one end of the sixth resistor respectively; the other end of the fifth resistor is electrically connected to one end of the seventh resistor, one end of the first capacitor and the first input end of the second operational amplifier respectively; the other end of the sixth resistor is electrically connected to one end of the eighth resistor, one end of the second capacitor and the second input end of the second operational amplifier respectively; a first output end of the second operational amplifier is electrically connected to the other end of the first capacitor and a first input end of the first comparator respectively, and a second output end of the second operational amplifier is electrically connected to the other end of the second capacitor and a first input end of the second comparator respectively; the second input end of the first comparator and the second input end of the second comparator both receive a triangular wave signal, the output end of the first comparator is electrically connected to the input end of the first grid driver, and the output end of the second comparator is electrically connected to the input end of the second grid driver; the output end of the first grid driver is electrically connected to the first output pair transistor; the output end of the second grid driver is electrically connected to the second output pair transistor; the other end of the seventh resistor is electrically connected to the first output end of the first output pair transistor, and the other end of the eighth resistor is electrically connected to the second output end of the second output pair transistor.
4. The automatic output offset voltage correction circuit of a class-D power amplifier circuit according to claim 3, wherein said first pair of output transistors comprises a first switch transistor and a second switch transistor electrically connected to said first switch transistor; the second output pair transistor comprises a third switch transistor and a fourth switch transistor electrically connected with the third switch transistor.
5. The circuit of claim 3, wherein the detection module comprises: the first filter, the second filter, the third comparator and the fourth comparator; the input end of the first filter is electrically connected to the first output end of the first output geminate transistor, and the output end of the first filter is electrically connected to the first input end of the third comparator; the input end of the second filter is electrically connected to the first output end of the second output geminate transistor, and the output end of the second filter is electrically connected to the first input end of the fourth comparator; the second input end of the third comparator and the second input end of the fourth comparator both receive a reference voltage, and the output end of the third comparator and the output end of the fourth comparator are both electrically connected to the control logic module.
6. The circuit of claim 5, wherein the control logic module comprises a logic circuit, a first input terminal of the logic circuit is electrically connected to the output terminal of the third comparator, and a second input terminal of the logic circuit is electrically connected to the output terminal of the fourth comparator; the logic circuit is electrically connected to the power amplifier circuit.
7. The circuit of claim 5, wherein the execution module comprises: a first output of the logic circuit, a second output of the logic circuit, and a third output of the logic circuit; the first output end of the logic circuit outputs a first control signal to a seventh resistor in the resistor array so as to adjust the resistance value of the seventh resistor; the second output end of the logic circuit outputs a second control signal to an eighth resistor in the resistor array so as to adjust the resistance value of the eighth resistor; and a third output end of the logic circuit outputs a third control signal to a first switch in the power amplifier module, wherein two ends of the first switch are electrically connected to one end of the first resistor and one end of the second resistor respectively.
8. The automatic output offset voltage correction circuit of class-D power amplifier circuit of claim 5, wherein said first filter and said second filter are both low pass filters, and wherein said low pass filters comprise RC type circuits or RC active filters with operational amplifiers and RC elements.
9. The class-D power amplifier circuit output offset voltage auto-calibration circuit of claim 7, wherein the third control signal outputs a high enable or a low enable according to a type of the first switch.
10. The class-D power amplifier circuit output offset voltage auto-calibration circuit of claim 7, wherein said third control signal is electrically connected to said first switch through a delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911280492.3A CN110855257A (en) | 2019-12-13 | 2019-12-13 | Automatic correction circuit for output offset voltage of class-D power amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911280492.3A CN110855257A (en) | 2019-12-13 | 2019-12-13 | Automatic correction circuit for output offset voltage of class-D power amplifier circuit |
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| Publication Number | Publication Date |
|---|---|
| CN110855257A true CN110855257A (en) | 2020-02-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911280492.3A Pending CN110855257A (en) | 2019-12-13 | 2019-12-13 | Automatic correction circuit for output offset voltage of class-D power amplifier circuit |
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| Country | Link |
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| CN (1) | CN110855257A (en) |
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2019
- 2019-12-13 CN CN201911280492.3A patent/CN110855257A/en active Pending
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