CN110851264A - Scheduling module integrated output system - Google Patents
Scheduling module integrated output system Download PDFInfo
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- CN110851264A CN110851264A CN201911121261.8A CN201911121261A CN110851264A CN 110851264 A CN110851264 A CN 110851264A CN 201911121261 A CN201911121261 A CN 201911121261A CN 110851264 A CN110851264 A CN 110851264A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
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Abstract
The invention discloses a scheduling module integrated output system, which comprises: the system comprises a processing module, a scheduling module, a conversion output module and a digital-to-analog conversion module, wherein a user can select a 3-wire or 4-wire serial port interface to allow a plurality of internal parameters to be programmed and read back, and the processing module adopts the scheduling module, so that the processing module can schedule the sequence of processing data through the scheduling module, and the system design is more flexible.
Description
Technical Field
The invention relates to the field of protocol standards of converters, in particular to a scheduling module integrated output system.
Background
A process is a concept virtualized by an operating system and used for organizing tasks in a computer, but as the process is endowed with more and more tasks, the process seems to have a real life, and the process is executed along with processor time from birth until finally disappearing, but the life of the process is taken the care of by an operating system kernel, and is just like a mother kernel which is tired of taking care of several children must make a decision on how to allocate limited computing resources among the processes and finally obtain the best use experience for users, and a module arranged in the kernel for executing the process is called a scheduler. The process is automatically changed to a ready state after it is created, and if the kernel allocates processor time to the process, the process is changed from the ready state to an execution state.
The scheduler is the manager of processor time, and the scheduler needs to be responsible for doing two things: one thing is to select certain ready processes to execute; another thing is to break some executing processes and bring them back to a ready state. However, not all schedulers have the second function. The state switching of some schedulers is unidirectional, which only can change the ready process into the execution state and can not change the process in execution back into the ready state. Schedulers that support bidirectional state switching are referred to as preemptive schedulers. The scheduler, when it has one process back ready, immediately has another ready process start executing. The multiple processes take over using the processor to make most efficient use of the processor time, although if the executing process actively enters a blocked state, the scheduler may also select another ready process to consume the processor time. The context switch refers to the process of switching execution of the process in the processor, the kernel undertakes the task of context switch and is responsible for storing and rebuilding the state of the processor before the process is switched off, so that the process does not feel that the execution of the process is interrupted, and the developer of the application program does not need to write codes specially to process the context switch when writing the computer program.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a scheduling module, so that a processing module can process a scheduling module integration output system of data sequence through the scheduling module.
The technical scheme adopted by the invention for solving the technical problems is as follows: constructing a scheduling module consolidated output system, comprising:
the processing module comprises a scheduling module, processes the priority of the data through the scheduling module and carries out scheduling in sequence to generate a processed data scheduling result, receives and processes the first data according to the processed data scheduling result and generates second data; the conversion output module is electrically connected with the processing module and generates a package according to the second data; and the digital-to-analog conversion module is electrically connected with the conversion output module, receives the package, converts the package into analog quantity and outputs the analog quantity.
In the system of the invention, the processing module is a JESD 204B IP core.
In the system of the present invention, the scheduling module further includes data whose first priority is an address resolution protocol request, data whose second priority is an operation human-computer interface, and data whose third priority is received by the analog-to-digital conversion module.
In the system of the present invention, the conversion output module provides a physical layer of a high-speed channel.
In the system of the present invention, the digital-to-analog conversion module is an AD9144 digital-to-analog converter.
In the system of the present invention, further comprising:
the register module is used for accessing initialization data and the first data; the data control module is respectively electrically connected with the registering module and the processing module and transmits the first data to the processing module through the data control module; and the serial port interface module is respectively and electrically connected with the register module and the digital-to-analog conversion module, and transmits initialization data to the digital-to-analog conversion module through the serial port interface module to carry out initialization operation.
In the system of the present invention, the data control module further reads and writes the read address data and the read and write times corresponding to the data reference module through the register module to generate various sine waveforms.
The scheduling module integrated output system has the following beneficial effects: the user-selectable 3-wire or 4-wire serial port interface module allows for programming and readback of a number of internal parameters, and the processing module employs its scheduling module, so that the processing module can schedule the processing data sequence through its scheduling module, making the system design more flexible.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an integrated output system of a scheduling module according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the embodiment of the scheduling module integrated output system of the present invention, a schematic structural diagram of the scheduling module integrated output system is shown in fig. 1. In the figure, the scheduling module integrates an output system, the system includes a processing module 1, a conversion output module 2, a digital-to-analog conversion module 3, a register module 4, a data control module 5 and a serial port interface module 6, wherein the processing module 1 includes a scheduling module 11.
In this embodiment, the processing module 1 is a JESD 204B IP core, and includes a scheduling module 11, which processes the priority of data and performs sequential scheduling by using the scheduling module 11 to generate a data processing scheduling result, receives and processes the first data D1 according to the data processing scheduling result, and generates the second data D2; the conversion output module 2 provides a physical layer of the high-speed channel, is electrically connected with the processing module 1, and generates a packet according to the second data D2; the digital-to-analog conversion module 3 is an AD9144 digital-to-analog converter, is electrically connected with the conversion output module block 2, receives the package, converts the package into analog quantity and outputs the analog quantity; the register module 4 accesses the initialization data D0 and the first data D1; the data control module 5 is electrically connected to the register module 4 and the processing module 1, and transmits the first data D1 to the processing module 1 through the data control module 5; the serial port interface module 6 is electrically connected to the register module 4 and the digital-to-analog conversion module 3, and transmits the initialization data D0 to the digital-to-analog conversion module 3 through the serial port interface module 6 for initialization.
TABLE 1
In this embodiment, the serial port interface module 6 performs initialization operation by using a 4-wire system, and first processes priority of data through the scheduling module 11 via the processing module 1 and performs scheduling in order to generate a processed data scheduling result, where the scheduling module 11 further includes data whose first priority is an address resolution protocol request, data whose second priority is an operation human-computer interface, and data whose third priority is received by the analog-to-digital conversion module, and receives and processes the first data D1 according to the processed data scheduling result, generates the second data D2, generates a packet according to the second data D2 via the conversion output module 2, and finally converts the packet into an analog quantity through the digital-to-analog conversion module and outputs the analog quantity.
The invention enables a user to select a 3-wire or 4-wire serial port interface to allow programming and reading back of a plurality of internal parameters, and the processing module adopts the scheduling module thereof, so that the processing module can schedule the processing data sequence through the scheduling module thereof, and the system design is more flexible.
The above description is only exemplary of the present invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A scheduling module consolidated output system, comprising: the processing module comprises a scheduling module, processes the priority of the data through the scheduling module and carries out scheduling in sequence to generate a processed data scheduling result, receives and processes the first data according to the processed data scheduling result and generates second data; the conversion output module is electrically connected with the processing module and generates a package according to the second data; and the digital-to-analog conversion module is electrically connected with the conversion output module, receives the package, converts the package into analog quantity and outputs the analog quantity.
2. The system of claim 1, wherein the processing module is a JESD 204B IP core.
3. The system of claim 1, wherein the scheduling module further comprises a first priority for data requested by an address resolution protocol, a second priority for data to operate a human-machine interface, and a third priority for data received by the analog-to-digital conversion module.
4. The system of claim 1, wherein the translation output module provides a physical layer of a high speed channel.
5. The system of claim 1, wherein the digital-to-analog conversion module is an AD9144 digital-to-analog converter.
6. The system of claim 1, further comprising: the register module is used for accessing initialization data and the first data; the data control module is respectively electrically connected with the registering module and the processing module and transmits the first data to the processing module through the data control module; and the serial port interface module is respectively and electrically connected with the register module and the digital-to-analog conversion module, and transmits initialization data to the digital-to-analog conversion module through the serial port interface module to carry out initialization operation.
7. The system of claim 6, wherein the data control module further reads and writes the read address data and the read/write times corresponding to the data reference module through the register module to generate various sine waveforms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911121261.8A CN110851264A (en) | 2019-11-15 | 2019-11-15 | Scheduling module integrated output system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911121261.8A CN110851264A (en) | 2019-11-15 | 2019-11-15 | Scheduling module integrated output system |
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| CN110851264A true CN110851264A (en) | 2020-02-28 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109709851A (en) * | 2018-12-25 | 2019-05-03 | 北京无线电计量测试研究所 | A kind of complex modulated signal high speed generating means and method |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109709851A (en) * | 2018-12-25 | 2019-05-03 | 北京无线电计量测试研究所 | A kind of complex modulated signal high speed generating means and method |
Non-Patent Citations (1)
| Title |
|---|
| 刘少华: "基于 FPGA的宽带多通道信号发生器研制" * |
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