CN110838451A - Semiconductor device and three-dimensional packaging method - Google Patents
Semiconductor device and three-dimensional packaging method Download PDFInfo
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- CN110838451A CN110838451A CN201911118664.7A CN201911118664A CN110838451A CN 110838451 A CN110838451 A CN 110838451A CN 201911118664 A CN201911118664 A CN 201911118664A CN 110838451 A CN110838451 A CN 110838451A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000001681 protective effect Effects 0.000 claims abstract description 48
- 229910000679 solder Inorganic materials 0.000 claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 15
- 239000003292 glue Substances 0.000 claims description 9
- 238000004528 spin coating Methods 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 4
- 238000007493 shaping process Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 9
- 230000006872 improvement Effects 0.000 description 7
- 238000012360 testing method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005336 cracking Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor device and a three-dimensional packaging method, wherein the three-dimensional packaging method comprises the following steps: s1, forming a through hole connected to the front side bonding pad on the back side of the bare chip; s2, forming a circuit connected to the bonding pad on the back side of the bare chip and the through hole; s3, forming a protective cover which closes the opening and extends to the inside of the through hole at the opening of the through hole; and S4, forming a solder mask layer covering the protective cover on the back surface of the bare chip. In the three-dimensional packaging method, after the circuit is formed and before the solder mask is formed, the protective cover for closing the opening of the through hole is formed on the back surface of the chip, and the protective cover is arranged, so that the problem that the solder mask is filled into the through hole when the solder mask is formed in the prior art, and the bonding pad on the front surface of the chip is crushed is effectively avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a three-dimensional packaging method.
Background
With the development of semiconductor manufacturing technology, the integration level of semiconductor chips is continuously improved, however, with the gradual failure of moore's law, in order to meet the demand for chip miniaturization, the three-dimensional packaging technology becomes a key point for breaking through chip integration.
Compared with a two-dimensional packaging technology, the three-dimensional packaging technology is to stack chips in the Z-axis direction, and at present, the three-dimensional stacking technology based on Through Silicon Vias (TSVs) is the most promising three-dimensional packaging mode. Compared with other packaging modes, the TSV-based three-dimensional packaging technology has the advantages of high integration level, short interconnection pitch, capability of greatly reducing RC delay caused by packaging and the like, and can integrate chips with different functions (such as power, radio frequency, memory, logic and MEMS) and even passive devices together to realize multifunctional System In Package (SiP).
However, in the package form in which the through-silicon via is formed on the back of the chip and connected to the front pad, the solder mask is formed by dry film pressing, and reliability tests (especially temperature cycle tests) cause failures such as pad cracking and delamination at the bottom of the TSV hole, especially for ultra-thin pad chips, MEMS with special pad structures, stack chips, and the like. Therefore, it is necessary to provide a further solution to the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a semiconductor device and a three-dimensional packaging method, which are used for overcoming the defects in the prior art.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a three-dimensional packaging method, comprising the steps of:
s1, forming a through hole connected to the front side bonding pad on the back side of the bare chip;
s2, forming a circuit connected to the bonding pad on the back side of the bare chip and the through hole;
s3, forming a protective cover which closes the opening and extends to the inside of the through hole at the opening of the through hole;
and S4, forming a solder mask layer covering the protective cover on the back surface of the bare chip.
As an improvement of the three-dimensional packaging method of the present invention, before forming the wiring connected to the pad, the method further includes: an insulating layer is formed on the back side of the die and the walls of the vias.
As a modification of the three-dimensional packaging method of the present invention, the step S3 includes:
s31, forming a photoresist layer at the opening of the through hole on the back of the bare chip by spin coating liquid glue;
and S32, standing the photoresist layer before the photoresist layer is solidified, so that the photoresist layer suspended at the opening of the through hole extends to the inside of the through hole.
As an improvement of the three-dimensional packaging method of the present invention, the step S3 further includes:
s33, primarily curing the photoresist layer to form a shape after standing;
s34, removing the photoresist layer in the area except the opening of the through hole by means of exposure and development;
and S35, carrying out secondary curing and shaping on the photoresist layer left after exposure and development.
As an improvement of the three-dimensional packaging method, the photoresist layer is primarily cured in a soft baking mode, and the photoresist layer is secondarily cured and shaped in a hard baking mode.
As an improvement of the three-dimensional packaging method, the protective cover and the solder mask are made of different materials.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a semiconductor device, comprising: the chip comprises a chip, a bonding pad, an interconnection layer, a protective cover and a solder mask layer;
the chip is provided with a front side and a back side, the bonding pad is arranged on the front side of the chip, a through hole communicated to the bonding pad is formed in the back side of the chip, the interconnection layer is located in the back side of the chip and the through hole and connected to the bonding pad, the protective cover is buckled at an opening formed in the back side of the through hole and seals the opening, and the solder mask is arranged on the back side of the chip and covers the solder mask of the protective cover.
As an improvement of the semiconductor device of the present invention, the protective cover extends into the through hole.
As an improvement of the semiconductor device of the present invention, an insulating layer is further provided between the interconnection layer and the chip.
In the semiconductor device of the present invention, the protective cover is made of a material different from that of the solder resist.
As an improvement of the semiconductor device of the present invention, a hollow-out region is further disposed on the solder mask layer, and a solder ball is disposed at the hollow-out region and connected to the interconnection layer.
Compared with the prior art, the invention has the beneficial effects that: in the three-dimensional packaging method, after the circuit is formed and before the solder mask is formed, the protective cover for closing the opening of the through hole is formed on the back surface of the chip, and the protective cover is arranged, so that the problem that the solder mask is filled into the through hole when the solder mask is formed in the prior art, and the bonding pad on the front surface of the chip is crushed is effectively avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a top view of a wafer having a plurality of chips thereon;
FIGS. 2 to 4 are views A-A in FIG. 1’The process schematic in the cross-sectional direction. Specifically, the method comprises the following steps:
FIG. 2 is a schematic diagram of a process for suspending a photoresist layer to a certain thickness on the surface of a die and a via;
FIG. 3 is a schematic diagram of a process of extending a photoresist layer suspended at an opening of a via hole to the inside of the via hole by standing;
FIG. 4 is a schematic view of a process for removing the photoresist layer in the region except the opening of the via hole by exposure and development;
FIG. 5 is a schematic diagram of a process for forming a solder mask layer covering a protective cover on the back side of a die, and a schematic diagram of a structure of a semiconductor device;
FIG. 6 is an electron microscope image of the protective cap formed at the opening of the through hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to solve the problems of pad cracking, layering and the like in the background technology, and provides a protective cover of a solder mask layer on a hole with controllable cavity size in a vertical through-silicon-via (TSV) formed by a spin coating mode, and on the basis, the solder mask layer can be formed by other process modes such as spin coating, spray coating, dry film pressing and the like, so that the damage to a pad at the bottom of the hole when the solder mask layer is formed is effectively improved, the layering tensile stress of the pad in a temperature cycle test can be greatly reduced, and the packaging reliability is effectively improved.
Because, forming the protective cover can avoid a large amount of glue from being accumulated in the hole compared with a mode of filling the hole with glue, the protective cover can avoid stress caused by mismatching of CTE of different materials, particularly glue and a bonding pad in the bottom of the hole in reliability tests such as temperature cycling.
In summary, the protective cap serves to protect the pad by preventing direct contact between the pad and other materials than the interconnect metal during the process and the via bottom pad and by preventing stress due to local CTE mismatch during reliability testing.
As shown in fig. 1 to 6, the three-dimensional packaging method of the present invention includes the steps of:
s1, forming a via on the back side of the die 10 connected to the front side pad 11;
s2, forming lines 14 connected to the pads 11 on the back side of the die 10 and in the through holes;
s3, forming a protective cover which closes the opening and extends to the inside of the through hole at the opening of the through hole;
s4, forming a solder mask layer on the back side of the bare chip 10 to cover the protective cover.
Further, before forming the wiring 14 connected to the pad 11, there are further included: an insulating layer 13 is formed on the back surface of the die 10 and the wall of the through hole.
Further, in order to form the protective cover, in one embodiment, the protective cover is mainly formed by spin-coating a liquid photoresist on the surface of the die 10 and the through hole to form a photoresist layer 100 with a certain thickness.
Specifically, the step S3 includes:
s31, forming a photoresist layer 100 at the opening of the via hole on the back side of the die 10 by spin coating liquid photoresist;
s32, before the photoresist layer 100 is cured, standing to make the photoresist layer 100 suspended at the opening of the through hole extend to the inside of the through hole.
Therefore, by controlling the standing time, the amount of the photoresist entering the through hole can be controlled, and the size of the formed cavity is further controlled, so that a target cavity with the required size is formed. The purpose of controlling the size of the cavity is that, since the mechanism of breaking the pad is caused by local stress, it should be required that the cavity where the pad is located should not be filled with glue, but if the cavity is too small, the mismatch between the glue and the stress of the metal line is caused, and the stress is transferred to the pad under the glue. Meanwhile, the formed cavity is not too large, i.e. the thickness of the protective cover or the thickness of the glue above the hole is not too small, otherwise the bubbles in the hole are broken and the water vapor cannot be blocked. Therefore, the control of the standing time is of great significance for achieving the purpose of the invention.
In order to enable the protective cover to be disposed only at the opening of the through hole on the back surface of the chip, the step S3 further includes:
s33, primarily curing the photoresist layer 100 to form a shape after standing;
s34, removing the photoresist layer 100 in the area except the opening of the through hole by means of exposure and development to form a protective cover shape with controllable shape and size;
and S35, carrying out secondary curing and shaping on the residual photoresist layer 100 after exposure and development to obtain the protective cover permanently left at the hole.
In one embodiment, the photoresist layer 100 is primarily cured by soft baking, and the photoresist layer 100 is secondarily cured and shaped by hard baking.
The protective cover and the solder mask layer can be made of different materials, and the arrangement is considered in such a way that the formed protective cover has the function of preventing the material for forming the solder mask layer subsequently from entering the through hole, and different materials can not cause other packaging problems, so that different materials and different process methods for forming the solder mask layer can be selected, and the packaging method has universality.
Finally, the three-dimensional packaging method of the present invention further comprises: the wafer 1 on which the dies 10 are located is diced to form individual packages.
Based on the same inventive concept, the invention also provides a semiconductor device.
As shown in fig. 5, the semiconductor device includes: chip 10, pads 11, interconnect layer 14, protective cover 15, and solder mask 16.
The chip 10 has a front surface and a back surface, the bonding pad 11 is disposed on the front surface of the chip 10, and a through hole communicated to the bonding pad 11 is disposed on the back surface of the chip 10. The interconnection layer 14 is located on the back surface of the chip 10 and in the through hole and connected to the pad 11, and an insulating layer 13 is further disposed between the interconnection layer 14 and the chip 10.
The protective cover 15 is fastened to the opening formed in the back of the through hole and used for closing the opening, and the solder resist layer 16 is arranged on the back of the chip 10 and covers the solder resist layer 16 of the protective cover 15. With this arrangement, the protective cover 15 is provided to effectively prevent solder resist material from filling the through holes and damaging the pads 11 on the front surface of the chip 10 when the solder resist layer 16 is formed in the prior art.
The protective cover 15 extends into the through hole, and forms a cavity with the pad 11 inside the through hole. By controlling the length of the protective cover 15 extending into the through hole, the size of the formed cavity is controlled, so as to obtain the target cavity with the required size.
The protective cover 15 and the solder mask 16 may be made of different materials, and this arrangement is to consider that the protective cover is formed to prevent the material for forming the solder mask from entering the through hole, and different materials do not cause other packaging problems, so that different materials and different processes for forming the solder mask can be selected, and the packaging method of the present invention has universality.
In addition, a hollow area is further disposed on the solder mask layer 16, a solder ball 17 is disposed at the hollow area, and the solder ball 17 is connected to the interconnection layer 14.
In summary, in the three-dimensional packaging method of the present invention, after the circuit is formed and before the solder mask is formed, the protective cover for closing the opening of the through hole is formed on the back surface of the chip, and by providing the protective cover, it is effectively avoided that the solder mask is filled into the through hole when the solder mask is formed in the prior art, and the pad on the front surface of the chip is damaged by pressure.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A three-dimensional packaging method is characterized by comprising the following steps:
s1, forming a through hole connected to the front side bonding pad on the back side of the bare chip;
s2, forming a circuit connected to the bonding pad on the back side of the bare chip and the through hole;
s3, forming a protective cover which closes the opening and extends to the inside of the through hole at the opening of the through hole;
and S4, forming a solder mask layer covering the protective cover on the back surface of the bare chip.
2. The three-dimensional packaging method according to claim 1, further comprising, before forming the wiring connected to the pad: an insulating layer is formed on the back side of the die and the walls of the vias.
3. The three-dimensional packaging method according to claim 1, wherein the step S3 includes:
s31, forming a photoresist layer at the opening of the through hole on the back of the bare chip by spin coating liquid glue;
and S32, standing the photoresist layer before the photoresist layer is solidified, so that the photoresist layer suspended at the opening of the through hole extends to the inside of the through hole.
4. The three-dimensional packaging method according to claim 3, wherein the step S3 further comprises:
s33, primarily curing the photoresist layer to form a shape after standing;
s34, removing the photoresist layer in the area except the opening of the through hole by means of exposure and development;
and S35, carrying out secondary curing and shaping on the photoresist layer left after exposure and development.
5. The three-dimensional packaging method according to claim 4, wherein the photoresist layer is primarily cured by soft baking, and the photoresist layer is secondarily cured and shaped by hard baking.
6. The three-dimensional packaging method according to any one of claims 1 to 5, wherein the protective cover and the solder resist layer are made of different materials.
7. A semiconductor device, characterized in that the semiconductor device comprises: the chip comprises a chip, a bonding pad, an interconnection layer, a protective cover and a solder mask layer;
the chip is provided with a front side and a back side, the bonding pad is arranged on the front side of the chip, a through hole communicated to the bonding pad is formed in the back side of the chip, the interconnection layer is located in the back side of the chip and the through hole and connected to the bonding pad, the protective cover is buckled at an opening formed in the back side of the through hole and seals the opening, and the solder mask is arranged on the back side of the chip and covers the solder mask of the protective cover.
8. The semiconductor device of claim 6, wherein the protective cap extends into the via.
9. The semiconductor device according to claim 6, wherein an insulating layer is further provided between the interconnect layer and the chip.
10. The semiconductor device according to any one of claims 7 to 9, wherein the protective cover and the solder resist layer are made of different materials.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911118664.7A CN110838451A (en) | 2019-11-15 | 2019-11-15 | Semiconductor device and three-dimensional packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911118664.7A CN110838451A (en) | 2019-11-15 | 2019-11-15 | Semiconductor device and three-dimensional packaging method |
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| Publication Number | Publication Date |
|---|---|
| CN110838451A true CN110838451A (en) | 2020-02-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201911118664.7A Pending CN110838451A (en) | 2019-11-15 | 2019-11-15 | Semiconductor device and three-dimensional packaging method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333570A (en) * | 2000-07-11 | 2002-01-30 | 精工爱普生株式会社 | Optical element and making method thereof electronic device |
| CN101419952A (en) * | 2008-12-03 | 2009-04-29 | 晶方半导体科技（苏州）有限公司 | Wafer stage chip encapsulation method and encapsulation construction |
| CN102903763A (en) * | 2011-07-29 | 2013-01-30 | 精材科技股份有限公司 | Chip package and method for forming the same |
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- 2019-11-15 CN CN201911118664.7A patent/CN110838451A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1333570A (en) * | 2000-07-11 | 2002-01-30 | 精工爱普生株式会社 | Optical element and making method thereof electronic device |
| CN101419952A (en) * | 2008-12-03 | 2009-04-29 | 晶方半导体科技（苏州）有限公司 | Wafer stage chip encapsulation method and encapsulation construction |
| CN102903763A (en) * | 2011-07-29 | 2013-01-30 | 精材科技股份有限公司 | Chip package and method for forming the same |
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Application publication date: 20200225 |