CN110827778B - Grid scanning driving circuit and display panel - Google Patents
Grid scanning driving circuit and display panel Download PDFInfo
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- CN110827778B CN110827778B CN201911024828.XA CN201911024828A CN110827778B CN 110827778 B CN110827778 B CN 110827778B CN 201911024828 A CN201911024828 A CN 201911024828A CN 110827778 B CN110827778 B CN 110827778B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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Abstract
The application discloses a grid scanning driving circuit and a display panel, wherein the grid scanning driving circuit sequentially comprises a memory, a plurality of temporary registers, a plurality of logic circuits, a plurality of potential shifters and a plurality of digital buffer amplifiers; the memory is respectively connected with the plurality of temporary registers, the plurality of temporary registers are connected with the plurality of logic circuits one by one, the plurality of logic circuits are connected with the plurality of potential shifters one by one, and the plurality of potential shifters are connected with the plurality of digital buffer amplifiers one by one; the memory stores grid scanning data, and the display panel displays according to the grid scanning data. The storage provided by the application stores grid scanning data, and programs the grid scanning data, so that the display panel is controlled to drive and display according to the programmed grid scanning data.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to a gate scan driving circuit and a display panel.
Background
Liquid crystal panels are popular among people because of their small size, light weight, and superior display quality. The circuit driving system of the liquid crystal panel generally includes a Timing Controller (TCON), a Driver IC, a power manager (PWN), a programmable Gamma correction buffer circuit (P-Gamma IC), etc., where the Timing Controller (TCON) outputs a video signal to the Driver IC, and the power manager outputs a voltage to the Driver IC and the programmable Gamma correction buffer circuit. The driving chip further includes a Gate chip (Gate IC) for supplying a line scanning signal to the liquid crystal panel and a source chip (source IC) for supplying a data signal to the liquid crystal panel.
As for an internal driving circuit of a Gate chip (Gate IC), a common structure is shown in fig. 1, a Gate scan driving circuit 11 mainly includes a shift register (shift register)12, a Logic circuit (Logic)13, a Level shifter (Level shifter)14, and a Digital buffer amplifier (Digital buffer)15, which are connected in sequence, and the shift register 12 sequentially shifts a Gate start signal according to a Gate shift clock signal; that is, every time a clock cycle passes, the logic state of the input stage is transmitted to the output stage, and at the beginning of the frame time, the synchronization signal (Vsync, in) scanned in the vertical direction is sent to the first stage shift register, and then each scanning line is opened line by using Vclock. The logic circuit 13 performs a logic operation on the output signal of the shift register 12 and an enable input signal OE supplied from a Timing Controller (TCON). The potential shifter 14 converts the output signal from the logic circuit 13 into an analog voltage signal suitable for driving the gate line by using a high level signal VGH and a low level signal VGL which are externally input, that is, performs potential shifting, for example, to a low potential logic level of 3V/0V or 5V/0V to a potential of 20V or more and-5V or less required for switching the pixel TFT. The digital buffer amplifier 15 amplifies and buffers the analog voltage signal of the potential shifter 14, and increases the driving capability of a Gate chip (Gate IC).
The above-mentioned method is suitable for a general display panel driving method, and the progressive scanning driving method is shown in fig. 2, but in some special display panel driving methods, the progressive-on scanning method is not suitable, for example, in some non-equal-cutting PWM driving modes, some special driving application environments, such as some special driving methods that need line skipping scanning, specify a certain line scanning, or do not scan according to the sequence of the arrangement positions, the above-mentioned driving method cannot be suitable.
Disclosure of Invention
The application provides a gate scanning driving circuit and a display panel, which can solve the problems generated by some special driving modes in some special driving application environments in the prior art, such as line skipping scanning, specified line scanning or scanning according to the sequence of the arrangement positions.
In order to solve the above technical problem, another technical solution adopted by the present application is: providing a grid scanning driving circuit, wherein the grid scanning driving circuit sequentially comprises a memory, a plurality of temporary registers, a plurality of logic circuits, a plurality of potential shifters and a plurality of digital buffer amplifiers; the memory is respectively connected with the plurality of temporary registers, the plurality of temporary registers are connected with the plurality of logic circuits one by one, the plurality of logic circuits are connected with the plurality of potential shifters one by one, and the plurality of potential shifters are connected with the plurality of digital buffer amplifiers one by one; the plurality of logic circuits are connected with each other, the plurality of potential shifters are connected with each other, and the plurality of digital buffer amplifiers are connected with each other; the memory stores grid scanning data, and the display panel displays according to the grid scanning data.
The driving circuit comprises an input control circuit, and the input control circuit is respectively connected with the memory, the temporary registers and the logic circuits.
The input control circuit comprises a clock input signal, and the clock input signal is respectively connected with the memory and the plurality of temporary registers.
Wherein the input control circuit includes a vertical synchronization input signal, the vertical synchronization input signal being connected to the memory.
Wherein the input control circuit includes enable input signals respectively connected to the plurality of logic circuits.
In order to solve the above technical problem, another technical solution adopted by the present application is: providing a display panel, wherein the display panel comprises a grid scanning driving circuit, a source driving circuit, a time schedule controller and an array substrate; the time schedule controller is respectively connected with the grid scanning driving circuit and the source driving circuit, and the grid scanning driving circuit and the source driving circuit are respectively connected with the array substrate; the grid scanning driving circuit sequentially comprises a memory, a plurality of temporary registers, a plurality of logic circuits, a plurality of potential shifters and a plurality of digital buffer amplifiers; the memory is respectively connected with the plurality of temporary registers, the plurality of temporary registers are connected with the plurality of logic circuits one by one, the plurality of logic circuits are connected with the plurality of potential shifters one by one, and the plurality of potential shifters are connected with the plurality of digital buffer amplifiers one by one; the plurality of logic circuits are connected with each other, the plurality of potential shifters are connected with each other, and the plurality of digital buffer amplifiers are connected with each other; the memory stores grid scanning data, and the display panel displays according to the grid scanning data.
The time schedule controller comprises an output control circuit, and the output control circuit is respectively connected with the memory, the plurality of temporary registers and the plurality of logic circuits.
The output control circuit comprises a clock output signal, and the clock output signal is respectively connected with the memory and the plurality of temporary registers.
Wherein the output control circuit includes a vertical synchronization output signal, the vertical synchronization output signal being connected with the memory.
The output control circuit comprises enable output signals which are respectively connected with the logic circuits.
The beneficial effect of this application is: different from the prior art, the application provides a gate scanning driving circuit and a display panel, and through the memory provided by the application, the memory stores gate scanning data, and the gate scanning data is programmed, so that the display panel is controlled to drive and display according to the programmed gate scanning data.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic diagram of a gate scan driving circuit according to an embodiment of the prior art;
FIG. 2 is a timing diagram of a progressive scan driving scheme in the prior art;
FIG. 3 is a schematic structural diagram of an embodiment of a gate scan driving circuit according to the present application;
FIG. 4 is a timing diagram illustrating sequential scanning of the gate scan driver circuit of the present application;
FIG. 5 is a timing diagram of a skip scan of the gate scan driving circuit of the present application;
FIG. 6 is a timing diagram illustrating a single row skipping scanning of the gate scan driving circuit of the present application;
FIG. 7 is a timing diagram of a multi-row skip scan of the gate scan driving circuit of the present application;
FIG. 8 is a schematic structural diagram of an embodiment of a display panel according to the present application;
fig. 9 is a schematic structural diagram of an embodiment of a display according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a gate scan driving circuit according to an embodiment of the present application.
As shown in fig. 3, the gate scan driving circuit 100 sequentially includes a memory 110, a plurality of registers 120, a plurality of logic circuits 130, a plurality of potential shifters 140, and a plurality of digital buffer amplifiers 150.
The memory 110 is connected to the registers 120, the registers 120 are connected to the logic circuits 130, the logic circuits 130 are connected to the potential shifters 140, and the potential shifters 140 are connected to the digital buffer amplifiers 150. The gate scan driving circuit 100 is configured by interconnecting a plurality of logic circuits 130, a plurality of potential shifters 140, and a plurality of digital buffer amplifiers 150.
The memory 110 provided in this embodiment stores gate scan data, and programs the gate scan data, so as to control the display panel to drive and display according to the programmed gate scan data. The gate scan data can be programmed according to a specific application environment, such as skipping, designating, or multi-line scanning, so as to realize a new driving method.
In this embodiment, the gate scan driving circuit 100 includes an input control circuit 160, and the input control circuit 160 is respectively connected to the memory 110, the plurality of registers 120, and the plurality of logic circuits 130.
Specifically, the input control circuit 160 includes a clock input signal Vclock, and the clock input signal Vclock is respectively connected to the memory 110 and the plurality of registers 120. The input control circuit 160 includes vertical synchronization input signals Vsync, in, which are connected to the memory 110. The input control circuit includes an enable input signal OE, which is connected to the plurality of logic circuits 130.
In this embodiment, modification is performed on the basic architecture of the existing gate scan driving circuit 11, the shift register 12 is replaced with a common register 120, the register 120 is only used for storing data of one clock cycle, the memory is small, and the response speed is high; meanwhile, a memory 110 is added to the front end of the temporary memory 120 for storing gate scan line driving data (scan data), which is externally transmitted to the memory 110, for example, outputted from a timing controller. The gate scan line driving data may be modified or programmed such that the gate scan line driving data controls to turn on a designated scan line every clock cycle or to turn on a plurality of designated scan lines simultaneously.
Specifically, the timing controller transmits gate scan line driving data to the memory 110, when the clock input signal Vclock and the vertical synchronization input signal Vsync, in are simultaneously active, the memory 110 transmits the gate scan line driving data to the temporary memory 120, and then transmits one gate scan line driving data to the temporary memory 120 every clock period; the register 120 is connected to the logic circuit 130, and the logic circuit 130 performs a logic operation on an output signal of the register 120 and an enable input signal OE provided by a Timing Controller (TCON); the logic circuit 130 is connected to a potential shifter 140, and the potential shifter 140 performs potential shifting by converting an output signal from the logic circuit 130 into an analog voltage signal suitable for driving the gate scanning line by using an externally input high level signal and low level signal, for example, a low potential logic level of 3V/0V or 5V/0V to a potential of 20V or more and-5V or less required for switching the pixel TFT. The potential shifter 140 is connected to a digital buffer amplifier 150, and the digital buffer amplifier 150 amplifies and buffers the analog voltage signal output by the potential shifter 140, so as to enhance the driving capability of the analog voltage signal and increase the driving capability of the gate scan driving circuit 100.
The steps of the memory 110 transmitting the gate scan driving data to the register 120 are as follows:
and 3, repeating the step 2, wherein N is equal to N +1 until N is equal to N.
For example, the following steps are carried out:
for the gate scan driving circuit 100 with n rows of outputs, a data array with n × n bits is stored in the memory 110, and the scanning sequence corresponding to the gate scan lines is from top to bottom. The data stored in each row in the data array corresponds to a case of scanning of a gate scanning line, each bit in the row represents a gate scanning line, and can be represented by "1" to turn on the scanning of the gate scanning line, and "0" to turn off the scanning of the gate scanning line. When the gate scanning line scans, array data of each row is sequentially read according to a clock pulse Vclock, and the read data is stored in the register 120 for output. This allows the scanning situation to be changed once per clock pulse Vclock, wherein the scanning order can be controlled by modifying the data of the data array.
The gate scan driving circuit 100 outputting 10 rows is taken as an example below.
1. If the data array of each row is read from top to bottom in the sequential scanning (generally, other applications can also implement), a "1" in each row represents that the gate scan line of the row is turned on, a "0" represents that the gate scan line of the row is turned off, and the scanning timing chart of the gate scan line is shown in fig. 4.
2. If the data array of each row is still read sequentially from top to bottom according to the condition of line skipping scanning (other applications cannot be realized, and the present application can be realized), a "1" in each row represents that the gate scanning line of the row is turned on, and a "0" represents that the gate scanning line of the row is turned off, the line skipping scanning is realized through the data stored in the data array, and a specific gate scanning line scanning timing chart is shown in fig. 5.
It should be noted that there may be only one "1" in each row of gate scan lines, which means that only one gate scan line is turned on at the same time, and the sequence thereof may be programmed, for example, the scan sequence turns on the scan lines in the order of 3-2-4-1, and the timing chart of the single-row skipping scan is shown in fig. 6; a plurality of "1" s may also appear, which means that a plurality of gate scan lines are turned on simultaneously, for example, the 3 rd scan line and the 4 th scan line are turned on simultaneously first, and the 1 st scan line and the 2 nd scan line are turned on simultaneously in the next clock cycle, and a timing chart of a multi-row skipping scan is shown in fig. 7, and the scanning time is saved by scanning a plurality of rows simultaneously; wherein, a "1" can be used to represent an on gate scan line, and a "0" can be used to represent an off gate scan line; or "0" represents an on gate scan line and "1" represents an off gate scan line.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
As shown in fig. 8, the display panel 200 includes a gate scan driving circuit 100, a source driving circuit 210, a timing controller 220, and an array substrate 230; the timing controller 220 is connected to the gate scan driving circuit 100 and the source driving circuit 210, respectively, and the gate scan driving circuit 100 and the source driving circuit 210 are connected to the array substrate 230, respectively.
The specific circuit structure of the gate scan driving circuit 100 is as described above, and is not described herein again.
In this embodiment, the timing controller 220 includes an output control circuit 260, and the output control circuit 260 is respectively connected to the memory, the plurality of registers, and the plurality of logic circuits of the gate scan driving circuit 100.
Specifically, the output control circuit 260 includes a clock output signal Vclock, and the clock output signal Vclock is respectively connected to the memory and the plurality of temporary registers of the gate scan driving circuit 100. The output control circuit 260 includes vertical synchronization output signals Vsync, in, which are connected to the memory of the gate scan driving circuit 100. The output control circuit 260 includes an enable output signal OE, which is connected to the plurality of logic circuits of the gate scan driving circuit 100, respectively.
In the above manner, the gate scan driving circuit of the display panel is provided with the memory, the memory stores the gate scan data, and programs the gate scan data, so as to control the display panel to drive and display according to the programmed gate scan data. The gate scan data can be programmed according to a specific application environment, such as skipping, designating, or multi-line scanning, so as to realize a new driving method.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a display according to the present application, the display 300 includes the display panel 200 with any structure described above, and the structure of the display panel 200 is described in detail in the foregoing embodiments and is not repeated herein.
In summary, it is easily understood by those skilled in the art that the present application provides a gate scan driving circuit and a display panel, in which the memory provided by the present application stores gate scan data, and programs the gate scan data, so as to control the display panel to drive and display according to the programmed gate scan data. The gate scan data can be programmed according to a specific application environment, such as skipping, designating, or multi-line scanning, so as to realize a new driving method.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (10)
1. A grid scanning driving circuit is characterized by comprising a memory, a plurality of temporary registers, a plurality of logic circuits, a plurality of potential shifters and a plurality of digital buffer amplifiers in sequence;
the memory is respectively connected with the plurality of temporary registers, the plurality of temporary registers are connected with the plurality of logic circuits one by one, the plurality of logic circuits are connected with the plurality of potential shifters one by one, and the plurality of potential shifters are connected with the plurality of digital buffer amplifiers one by one; the plurality of logic circuits are connected with each other, the plurality of potential shifters are connected with each other, and the plurality of digital buffer amplifiers are connected with each other;
the memory stores a plurality of grid scanning data expressed in a data array format of n x n bits, the display panel displays according to the grid scanning data, each bit in the grid scanning data of each row in the data array corresponds to the on and off of one grid scanning line, when scanning is carried out, the grid scanning data are sequentially read according to a plurality of clock pulses and stored in a plurality of temporary registers for output, each clock pulse changes one-time scanning condition, the difference of the grid scanning data of different rows represents different scanning sequences, and n is a positive integer.
2. The driving circuit of claim 1, wherein the driving circuit comprises an input control circuit, and the input control circuit is respectively connected to the memory, the plurality of temporary registers, and the plurality of logic circuits.
3. The driving circuit of claim 2, wherein the input control circuit comprises a clock input signal, and the clock input signal is respectively connected to the memory and the plurality of temporary registers.
4. The driving circuit of claim 2, wherein the input control circuit comprises a vertical synchronization input signal, the vertical synchronization input signal being coupled to the memory.
5. The drive circuit according to claim 2, wherein the input control circuit includes enable input signals respectively connected to the plurality of logic circuits.
6. The display panel is characterized by comprising a grid scanning driving circuit, a source driving circuit, a time schedule controller and an array substrate; the time schedule controller is respectively connected with the grid scanning driving circuit and the source driving circuit, and the grid scanning driving circuit and the source driving circuit are respectively connected with the array substrate; wherein the content of the first and second substances,
the grid scanning driving circuit sequentially comprises a memory, a plurality of temporary registers, a plurality of logic circuits, a plurality of potential shifters and a plurality of digital buffer amplifiers; wherein the content of the first and second substances,
the memory is respectively connected with the plurality of temporary registers, the plurality of temporary registers are connected with the plurality of logic circuits one by one, the plurality of logic circuits are connected with the plurality of potential shifters one by one, and the plurality of potential shifters are connected with the plurality of digital buffer amplifiers one by one; the plurality of logic circuits are connected with each other, the plurality of potential shifters are connected with each other, and the plurality of digital buffer amplifiers are connected with each other;
the memory stores a plurality of grid scanning data expressed in a data array format of n x n bits, the display panel displays according to the grid scanning data, each bit in the grid scanning data of each row in the data array corresponds to the on and off of one grid scanning line, when scanning is carried out, the grid scanning data are sequentially read according to a plurality of clock pulses and stored in a plurality of temporary registers for output, each clock pulse changes one-time scanning condition, the difference of the grid scanning data of different rows represents different scanning sequences, and n is a positive integer.
7. The display panel according to claim 6, wherein the timing controller comprises an output control circuit, and the output control circuit is connected to the memory, the plurality of temporary registers, and the plurality of logic circuits, respectively.
8. The display panel according to claim 7, wherein the output control circuit includes clock output signals respectively connected to the memory and the plurality of temporary registers.
9. The display panel according to claim 7, wherein the output control circuit includes a vertical synchronization output signal, and wherein the vertical synchronization output signal is connected to the memory.
10. The display panel according to claim 7, wherein the output control circuit includes enable output signals, and the enable output signals are respectively connected to a plurality of the logic circuits.
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