CN110825575A - Memory detection method - Google Patents
Memory detection method Download PDFInfo
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- CN110825575A CN110825575A CN201911104855.8A CN201911104855A CN110825575A CN 110825575 A CN110825575 A CN 110825575A CN 201911104855 A CN201911104855 A CN 201911104855A CN 110825575 A CN110825575 A CN 110825575A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
The invention discloses a memory detection method, which comprises the following steps: data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the information read by the data written before is consistent with the written data, if not, sends abnormal information and generates a record report, and the data are written again: the external equipment sends the data needing to be written into the memory again; according to the invention, by setting the process flows of data writing, data re-writing, data outputting and cache releasing, the problems of low memory detection precision and low memory detection efficiency of the existing memory detection method are solved.
Description
Technical Field
The invention relates to the technical field of information, in particular to a memory detection method.
Background
The memory is one of the important components in the computer, and is a bridge communicating with the CPU, and the operation of all programs in the computer is performed in the memory, so that the performance of the memory has a great influence on the computer, the memory is also called an internal memory and a main memory, and is used for temporarily storing operation data in the CPU and data exchanged with an external memory such as a hard disk, and as long as the computer is in operation, the CPU transfers data to be operated into the memory for operation, and after the operation is completed, the CPU transfers the result out, and the operation of the memory also determines the stable operation of the computer.
The memory is composed of a memory chip, a circuit board, a golden finger and the like, but the current memory detection method only carries out simple detection, so that the detection accuracy is low, and the detection efficiency is influenced by too many memory detection steps.
Disclosure of Invention
The invention aims to provide a memory detection method, which has the advantages of increasing the memory detection precision and improving the memory detection efficiency, and solves the problems of low memory detection precision and low memory detection efficiency of the conventional memory detection method.
In order to achieve the purpose, the invention provides the following technical scheme: a memory detection method comprises the following steps:
step 1: data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the read information of the data written before is consistent with the written data, and if the read information is not consistent with the written data, sends abnormal information and generates a record report;
step 2: and (3) writing the data again: the external equipment sends the data needing to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, and if the address space has the residual space, the memory writes the data into the same address space;
and step 3: and (3) data output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, and if so, allows the output to continue;
and 4, step 4: releasing the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
Preferably, in step 1, whenever data writing, outputting, releasing, or the like occurs, the behavior is determined.
Preferably, in step 1, each time data is written, the written data and the read data need to be compared to determine whether an abnormality occurs.
Preferably, in step 1, the generated record report is stored in a connected storage device and is specially marked.
Preferably, in step 2, the address space is used to represent a storage location in the physical unit of memory.
Preferably, in step 2, if it is detected that the address space in which the previous data was written does not have a space, the data to be written is rewritten into another address space.
Preferably, in step 3, each time data is output, the output request and the output data need to be compared, and a comparison result and an operation record are generated.
Preferably, in step 3, if the request for outputting data does not match the data in the designated area of the memory, the output is immediately suspended and an abnormal signal is issued.
Preferably, in step 4, every time the memory is released, the memory release information is acquired and recorded in the operation record.
Preferably, in step 4, the customized dynamic library is set in the system and stored in a system disk of the computer storage device.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, through setting the process flows of data writing, data re-writing, data output and cache release, the problems of low memory detection precision and low memory detection efficiency of the existing memory detection method are solved by utilizing multiple comparison and judgment, so that the memory detection precision is increased, and the memory detection efficiency can be improved.
Detailed Description
The present invention will now be described in more detail by way of examples, which are given by way of illustration only and are not intended to limit the scope of the present invention in any way.
The invention provides a technical scheme that: a memory detection method comprises the following steps:
step 1: data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the read information of the data written before is consistent with the written data, and if the read information is not consistent with the written data, sends abnormal information and generates a record report;
step 2: and (3) writing the data again: the external equipment sends the data needing to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, and if the address space has the residual space, the memory writes the data into the same address space;
and step 3: and (3) data output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, and if so, allows the output to continue;
and 4, step 4: releasing the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
The first embodiment is as follows:
data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the information read by the data written before is consistent with the written data, if not, sends abnormal information and generates a record report, and the data are written again: the external device sends the data to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, if so, the memory writes the data of this time into the same address space, and the data are output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, if so, allows to continue outputting, and releases the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
Example two:
in the first embodiment, the following steps are added:
in step 1, as long as data writing, outputting, releasing and other behaviors occur, the behaviors are judged, and the written data and the read data need to be compared each time data is written, so that whether an abnormality occurs is judged; the generated record report is stored in the connected storage device and is specially marked.
Data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the information read by the data written before is consistent with the written data, if not, sends abnormal information and generates a record report, and the data are written again: the external device sends the data to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, if so, the memory writes the data of this time into the same address space, and the data are output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, if so, allows to continue outputting, and releases the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
Example three:
in the second embodiment, the following steps are added:
in step 2, the address space is used to indicate a storage unit in the physical unit of the memory, and if it is detected that the address space in which the last data is written has no space left, the data to be written is rewritten into the other address space.
Data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the information read by the data written before is consistent with the written data, if not, sends abnormal information and generates a record report, and the data are written again: the external device sends the data to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, if so, the memory writes the data of this time into the same address space, and the data are output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, if so, allows to continue outputting, and releases the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
Example four:
in the third embodiment, the following steps are added:
in step 3, each time data is output, the output request and the output data need to be compared, a comparison result and an operation record are generated, if the request of the output data is inconsistent with the data in the designated area of the memory, the output is immediately suspended, and an abnormal signal is sent out.
Data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the information read by the data written before is consistent with the written data, if not, sends abnormal information and generates a record report, and the data are written again: the external device sends the data to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, if so, the memory writes the data of this time into the same address space, and the data are output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, if so, allows to continue outputting, and releases the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
Example five:
in the fourth example, the following steps were added:
in step 4, each time the memory is released, the memory release information is obtained and recorded in the operation record, and the customized dynamic library is set in the system and stored in the system disk of the computer storage device.
Data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the information read by the data written before is consistent with the written data, if not, sends abnormal information and generates a record report, and the data are written again: the external device sends the data to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, if so, the memory writes the data of this time into the same address space, and the data are output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, if so, allows to continue outputting, and releases the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A memory detection method is characterized in that: the method comprises the following steps:
step 1: data writing: the external equipment sends data needing to be written into the memory, the memory detects the data entering and exiting, verifies whether the data are the data written into the memory, finds that the data are the data written into the memory, the memory writes the data, reads the written data, compares whether the read information of the data written before is consistent with the written data, and if the read information is not consistent with the written data, sends abnormal information and generates a record report;
step 2: and (3) writing the data again: the external equipment sends the data needing to be written into the memory again, after the memory verifies the data written into the memory, whether the address space written by the previous data has a residual space is detected, and if the address space has the residual space, the memory writes the data into the same address space;
and step 3: and (3) data output: the external device sends a request for reading output data to the memory, the memory verifies the request, confirms that the request is the request for outputting data from the memory, allows relevant devices to read the output data from the specified area, compares whether the output data, the request for outputting the data and the data in the specified area of the memory are consistent or not, and if so, allows the output to continue;
and 4, step 4: releasing the cache: when the process in the related equipment requests to release the memory, the self-defined dynamic library is searched, the memory executes the memory release interception function in the dynamic library, and the designated data in the designated area is released.
2. The memory detection method according to claim 1, wherein: in step 1, as long as data writing, outputting, releasing, and the like occur, the behavior is determined.
3. The memory detection method according to claim 1, wherein: in step 1, each time data is written, the written data and the read data need to be compared, and whether an abnormality occurs is determined.
4. The memory detection method according to claim 1, wherein: in step 1, the generated record report is stored in the connected storage device and is specially marked.
5. The memory detection method according to claim 1, wherein: in step 2, the address space is used to represent a memory location in the physical unit of memory.
6. The memory detection method according to claim 1, wherein: in step 2, if it is detected that the address space in which the previous data was written has no space left, the data to be written is rewritten into another address space.
7. The memory detection method according to claim 1, wherein: in step 3, each time data is output, the output request and the output data need to be compared, and a comparison result and an operation record are generated.
8. The memory detection method according to claim 1, wherein: in step 3, if the request for outputting data is inconsistent with the data in the designated area of the memory, the output is immediately suspended, and an abnormal signal is sent out.
9. The memory detection method according to claim 1, wherein: in step 4, every time the memory is released, the memory release information is acquired and recorded in the operation record.
10. The memory detection method according to claim 1, wherein: in step 4, the customized dynamic library is set in the system and stored in the system disk of the computer storage device.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102843396A (en) * | 2011-06-22 | 2012-12-26 | 中兴通讯股份有限公司 | Data writing and reading method and device in distributed caching system |
| US20150186059A1 (en) * | 2013-12-27 | 2015-07-02 | Fujitsu Limited | Memory management program, memory management method, and memory management device |
| CN108388517A (en) * | 2018-03-14 | 2018-08-10 | 深圳怡化电脑股份有限公司 | A kind of internal-memory detection method, device, equipment and storage medium |
| CN109614048A (en) * | 2018-12-10 | 2019-04-12 | 深圳市硅格半导体有限公司 | Data read-write method, device and computer readable storage medium based on flash memory |
| CN110413521A (en) * | 2019-07-24 | 2019-11-05 | 杭州迪普信息技术有限公司 | A kind of the write-overflow detection method and device of heap memory |
-
2019
- 2019-11-13 CN CN201911104855.8A patent/CN110825575B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102843396A (en) * | 2011-06-22 | 2012-12-26 | 中兴通讯股份有限公司 | Data writing and reading method and device in distributed caching system |
| US20150186059A1 (en) * | 2013-12-27 | 2015-07-02 | Fujitsu Limited | Memory management program, memory management method, and memory management device |
| CN108388517A (en) * | 2018-03-14 | 2018-08-10 | 深圳怡化电脑股份有限公司 | A kind of internal-memory detection method, device, equipment and storage medium |
| CN109614048A (en) * | 2018-12-10 | 2019-04-12 | 深圳市硅格半导体有限公司 | Data read-write method, device and computer readable storage medium based on flash memory |
| CN110413521A (en) * | 2019-07-24 | 2019-11-05 | 杭州迪普信息技术有限公司 | A kind of the write-overflow detection method and device of heap memory |
Non-Patent Citations (2)
| Title |
|---|
| 刘发贵 等: "嵌入式软件动态内存检测工具的设计与实现", 《计算机工程》 * |
| 翟高寿 等: "设备驱动故障注入方法的研究与实现", 《信息网络安全》 * |
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