CN110799935A

CN110799935A - Data storage method, flash memory device, intelligent battery and movable platform

Info

Publication number: CN110799935A
Application number: CN201880041365.5A
Authority: CN
Inventors: 张华森; 江帆
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd; Shenzhen Dajiang Innovations Technology Co Ltd
Priority date: 2018-12-04
Filing date: 2018-12-04
Publication date: 2020-02-14
Also published as: WO2020113440A1

Abstract

A data storage method, a flash memory device, an intelligent battery and a movable platform are provided. A method of data storage, comprising: if a data storage request is received, determining the storage times of the flash memory device; comparing the storage times with a preset time threshold value to obtain a comparison result; and determining whether to perform address conversion on a reserved storage unit in the flash memory device according to the comparison result. In the embodiment, by setting the storage time threshold, address conversion is performed on the reserved storage units in the flash memory device when the storage time threshold is reached, so that data is prevented from being written into the same minimum storage unit for many times, the probability that each minimum storage unit in the flash memory device is erased tends to be consistent, the effect of balancing the erasing times is achieved, and the service life of the flash memory device is prolonged. In addition, in the embodiment, only data of a part of minimum storage units are processed, requirements on storage space and computing resources are low, and the flash memory device is suitable for a flash memory device using a single chip microcomputer MCU as a processor.

Description

Data storage method, flash memory device, intelligent battery and movable platform

Technical Field

The embodiment of the invention relates to the technical field of storage, in particular to a data storage method, a flash memory device, an intelligent battery and a movable platform.

Background

Flash memory Flash devices are widely used in the embedded field because of their erasable, programmable, non-loss of power-down data and fast read access support. In practical use, a flash memory device must perform an erase operation in which data is written, and the erase operation is performed in units of minimum erase units (sectors). Since the erase count of each minimum erase unit is limited, usually only 10 ten thousand, the erase count of each minimum erase unit needs to be managed, so as to ensure the erase count to be balanced.

In an existing Flash memory device, such as a fixed hard disk SSD, a usb disk, etc., a Flash Transform Layer (FTL) suitable for the Flash memory device is usually configured to manage the erase times of each minimum erase unit, so as to avoid a situation that a part of the minimum erase units reaches an upper limit of the erase times and a part of the minimum erase units are not erased yet.

However, the existing Flash translation layer needs to track and manage the erasing times of each minimum erasing unit, and needs more storage space and computing resources. For electronic equipment using a single chip microcomputer MCU as a microprocessor, a Flash conversion layer is difficult to realize due to limited storage space and computing resources.

Disclosure of Invention

The embodiment of the invention provides a data storage method, a flash memory device, an intelligent battery and a movable platform.

In a first aspect, an embodiment of the present invention provides a data storage method, including:

if a data storage request is received, determining the storage times of the flash memory device;

comparing the storage times with a preset time threshold value to obtain a comparison result;

and determining whether to perform address conversion on a reserved storage unit in the flash memory device according to the comparison result.

In a second aspect, an embodiment of the present invention provides a flash memory apparatus, including a processor, a memory, and a flash memory device, where the flash memory device is provided with a plurality of minimum storage units, and the processor implements, after reading an executable instruction from the memory:

In a third aspect, an embodiment of the present invention provides an intelligent battery, including a processor, a memory, and a flash memory device, where the flash memory device is provided with a plurality of minimum storage units, and the processor reads an executable instruction from the memory to implement:

In a fourth aspect, an embodiment of the present invention provides a movable platform, including the smart battery of the third aspect.

In a fifth aspect, the present invention provides a readable storage medium, on which computer instructions are stored, and when executed, the computer instructions implement the steps of the method in the first aspect.

As can be seen from the above technical solutions, in this embodiment, after the data storage request is received, the storage frequency of the flash memory device can be determined. Then, whether the storage times and the time threshold value are equal or not is compared, and whether address conversion is carried out on the storage units in the flash memory device or not is determined according to the comparison result. It can be seen that, in the embodiment, by setting the storage time threshold, address conversion is performed on the reserved storage units in the flash memory device when the storage time threshold is reached, so that data is prevented from being written into the same minimum storage unit for many times, and the probability of erasing each minimum storage unit in the flash memory device tends to be consistent, thereby achieving the effect of balancing the erasing times and being beneficial to prolonging the service life of the flash memory device. In addition, in the embodiment, only data of a part of minimum storage units are processed, requirements on storage space and computing resources are low, and the flash memory device is suitable for a flash memory device using a single chip microcomputer MCU as a processor.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

Fig. 1 is a schematic flow chart of a data storage method according to an embodiment of the present invention;

fig. 2 is a schematic flow chart of obtaining the storage times according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of another method for obtaining storage times according to an embodiment of the present invention;

FIG. 4 is a flow chart illustrating writing data according to the storage status of the first memory cell according to an embodiment of the present invention;

FIGS. 5(a) -5 (b) are schematic diagrams illustrating the result of writing data when the first storage unit is not full of data according to the embodiment of the present invention;

6(a) -6 (c) are schematic diagrams illustrating a process of writing data when the first storage unit is full of data according to an embodiment of the present invention;

FIG. 7 is a flow chart illustrating a write-first data-then-address translation process according to an embodiment of the present invention;

FIGS. 8(a) -8 (f) are schematic diagrams illustrating a process of writing data first and then performing address translation according to an embodiment of the present invention;

FIG. 9 is a flowchart illustrating a process of writing data after address translation according to an embodiment of the present invention;

10(a) -10 (d) are schematic diagrams illustrating a process of writing data after address conversion when the first storage unit is full of data according to an embodiment of the present invention;

11(a) -11 (c) are schematic diagrams illustrating a process of writing data after address translation if the first storage unit is not full of data according to an embodiment of the present invention;

FIG. 12 is a flow chart illustrating address translation according to an embodiment of the present invention;

FIGS. 13(a) -13 (d) are schematic diagrams illustrating the process of performing address translation and writing data simultaneously when the first memory cell is full of data according to an embodiment of the present invention;

FIG. 14 is a flow chart illustrating a data storage method according to an embodiment of the present invention;

15(a) -15 (b) are schematic diagrams of a process of removing a bad block as a first storage unit according to an embodiment of the present invention;

16(a) -16 (b) are schematic diagrams illustrating a process of removing bad blocks to reserve storage units according to an embodiment of the present invention;

17(a) -17 (b) are schematic diagrams of a process of removing a bad block as a second storage unit according to an embodiment of the present invention;

18(a) -18 (h) are schematic process diagrams of a data storage method according to an embodiment of the present invention;

FIG. 19 is a block diagram of a flash memory device provided by an embodiment of the present invention;

fig. 20 is a block diagram of a smart battery according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. In addition, the features in the embodiments and the examples described below may be combined with each other without conflict.

In view of the scheme for balancing the erase times of the minimum erase units of the existing flash memory device, the translation layer FTL needs to manage the erase times of each minimum erase unit, so as to avoid the situation that part of the minimum erase units reaches the upper limit of the erase times soon and part of the minimum erase units are not erased or are erased very rarely.

However, since the number of minimum erase units in the flash memory device is large, in the process of tracking and managing the erase times of each minimum erase unit, a large amount of storage space and calculation resources are required, which makes it difficult to equalize the erase times for the MCU having a single chip microcomputer with limited storage space and calculation resources.

The invention is characterized in that a reserved storage unit is arranged, then the reserved storage unit is subjected to address conversion when the storage frequency of the flash memory device reaches a frequency threshold value, and the data is prevented from being written into the same minimum storage unit for many times through the address conversion, so that the probability of storing the data in each minimum storage unit tends to be consistent, even if the erasure frequency of each minimum storage unit tends to be consistent, the balanced effect is achieved.

In this embodiment, the mapping relationship between the Logical Address (LA) and the Physical Address (PA) may be stored in advance in the flash memory device. For convenience of describing the scheme, in the following embodiments, the physical address refers to a first address of the minimum storage unit, and the logical address refers to a first address of a logical block having a mapping relationship with the minimum storage unit.

It should be noted that the mapping relationship including the logical address and the physical address can be stored in any minimum storage unit in the flash memory device. In some embodiments, the mapping relationship is stored in the last minimum storage location of the flash memory device. Of course, the technical staff may also store the mapping relationship in an external storage, a cloud, and the like, and under the condition that the scheme of the embodiment can be implemented, the corresponding scheme falls into the protection scope of the application.

The minimum memory cell in this embodiment refers to the smallest physical area (i.e., the minimum erase unit) that can be operated each time the flash memory device is erased, for example, 4 kbits. Of course, the technician may also adjust the size of the minimum storage unit according to the specific scenario, and the corresponding scheme falls within the scope of the present application.

Fig. 1 is a schematic flow chart of a data storage method according to an embodiment of the present invention, and referring to fig. 1, a data storage method includes steps 101 to 103, where:

in step 101, if a data storage request is received, the storage times of the flash memory device are determined.

In this embodiment, the FTL software in the flash memory device may interact with the application software. The user may select a location for storing data by the application software, which may include a logical address or a plurality of logical addresses. Considering that in the scenario of multiple logical addresses, the writing process of each logical address still starts from the first logical address, and is similar to the writing scheme of one logical address, the following embodiments select a scenario description scheme of one logical address.

In this embodiment, in the interaction process, the flash memory device may receive a data storage request of the application software. Wherein the data storage request comprises a first logical address, the first logical address being mappable to a physical address, the physical address representing a head address of a minimum unit of storage and also representing a head address of a plurality of minimum units of storage.

In this embodiment, each time a data storage request is received, the FTL software records the data storage request or modifies the storage frequency of the data stored in the flash memory device, so as to determine the storage frequency of the flash memory device. It should be noted that when determining the storage times, the records may be acquired first, and then the storage times may be determined by combining with the data storage request of this time; the data storage request can be recorded first, and then the storage times of the flash memory device can be determined. The technician may set the setting according to a specific scenario, and is not limited herein.

In one embodiment, storing the number of times may include: from the perspective of the storage device, the number of times data has been written to the flash memory device. In this scenario, referring to fig. 2, determining the number of times of storage of the flash memory device may include:

after receiving the data storage request, the FTL software adjusts the recorded storage times (corresponding to step 201). The adjustment mode can be to record the data storage request and then count the recorded data storage request so as to obtain the storage times; the number of times after adjustment may be used as the determined number of times of storage for increasing 1 on the basis of the previous number of times of storage. Then, the recorded storage count is read to obtain the storage count of the flash memory device (corresponding to step 202).

In another embodiment, the storing the number of times may further include: the number of times data has been written to the first memory cell from the perspective of the minimum memory cell. In this scenario, referring to fig. 3, determining the number of times of storage of the flash memory device may include:

after receiving the data storage request, acquiring a first logical address in the data storage request, wherein the first logical address refers to a logical address where a user desires to write data. The FTL software adjusts the storage count of the first logical address in the data storage request, where the storage count of the first logical address points to the number of times data has been written in the first logical address (corresponding to step 301). Then, the FTL software reads the storage count of the first logical address in the data storage request to obtain the storage count of the flash memory device (corresponding to step 302).

In step 102, comparing the storage times with a preset time threshold to obtain a comparison result.

In this embodiment, a number threshold may be preset, and the number threshold may be adjusted according to details, for example, according to an empirical value, or for example, according to statistics performed in a big data manner, and a number threshold corresponding to the longest life of the flash memory device or the same, similar, or least different number of times of erasing of each minimum memory cell is taken as the number threshold of this embodiment. Technical personnel can also set the number threshold value according to other modes, and under the condition that the scheme of the application can be realized, the corresponding scheme falls into the protection scope of the application.

Wherein the number threshold may be stored in any one of the smallest memory cells in the flash memory device. In some embodiments, the threshold number of times is stored in the last minimum memory location of the flash memory device.

In this embodiment, the FTL software may compare the storage times with the time threshold, and may obtain a comparison result. The comparison result may include that the storage times are equal to the time threshold, or that the storage times are different from the time threshold.

It should be noted that, when the storage count is equal to the count threshold, the FTL software in this embodiment also clears the storage count. The zeroing mode may include deleting the recorded storage data storage request, marking the recorded storage data storage request, and zeroing the storage time variable.

In step 103, it is determined whether to perform address translation on a reserved storage unit in the flash memory device according to the comparison result.

In this embodiment, the FTL software may determine whether to perform address translation on the reserved memory unit in the flash memory device according to the comparison result, which may include:

comparative result 1

And if the comparison result shows that the storage times are not equal to the time threshold, determining to keep the current mapping relation of the storage units, and storing the data to the first storage unit mapped by the first logical address in the data storage request.

Wherein, the current mapping relation of the reserved storage unit is maintained, i.e. the mapping relation between the reserved address and the reserved storage unit is not subjected to address translation.

In addition, the FTL software storing data to the first storage unit of the first logical address mapping in the data storage request, referring to fig. 4, may include:

FTL software may determine a storage status of a first storage unit, wherein the storage status may comprise data indicating that the first storage unit is not full and data indicating that the first storage unit is full (corresponding to step 401).

The FTL software then determines whether the storage status indicates that the first storage unit is not full of data or that the first storage unit is full of data (corresponding to step 402).

Then, if the storage status indicates that the first storage unit is not full of data, the FTL software writes the data into the tail portion of the stored data (corresponding to step 403), that is, directly writes the data into the first storage unit without erasing the first storage unit. Referring to fig. 5(a) -5 (b), taking the first logical address as the first logical address LA0 of the logical address space as an example, the FTL software determines that the data XX0 already stored in the first memory cell PA1 and the size of the data XX0 is smaller than the size of the first memory cell PA1, that is, the first memory cell PA1 is not full of data, and the FTL software writes data from the tail of the data XX0, so as to obtain the result shown in fig. 5 (b).

If the storage status indicates that the first memory cell is full of data, the FTL software erases the first memory cell and then writes data into the first memory cell (corresponding to step 404). Referring to fig. 6(a) -6 (c), continuing to take the first logical address as the first logical address LA0 of the logical address space as an example, the FTL software determines that the data XX1 already stored in the first memory cell PA1 and the size of the data XX1 is equal to the size of the first memory cell PA1, that is, the first memory cell PA1 is full of data, the FTL software erases the data XX1 in the first memory cell PA1, and indicates that no data is stored with FF, and the result is shown in fig. 6 (b). The FTL software then writes the data to the first memory unit PA1, with the result shown in fig. 6 (c).

For convenience of reading, fig. 5(a) to 5(b) and fig. 6(a) to 6(c) are shown by groups and underlined.

Comparative result 2

In a first scenario, if the comparison result indicates that the storage times are equal to the time threshold, it is determined that address conversion is performed on the reserved storage unit. Address translation may include the following:

in a first mode

Referring to fig. 7, first, the FTL software writes data into the first storage unit (corresponding to step 701), and a scenario of writing data may consider that the first storage unit is full of data or not full of data, specifically refer to the contents in fig. 5(a) -5 (b) and fig. 6(a) -6 (c), which is not described herein again. The FTL software then erases the reserved memory location and copies the data in the first memory location to the reserved memory location (corresponding to step 702). The FTL software then maps the first logical address to the reserved memory location and maps the reserved address to the first memory location, completing the address translation (corresponding to step 703).

Referring to FIG. 8(a), taking the reserved address RS mapped to the reserved memory cell PA0 and the first logical address LA0 and the data XX1 stored in the first memory cell PA1 as an example, the FTL software erases the data XX1 in the first memory cell PA1 to become data FF, and the result is shown in FIG. 8 (b). Then, the FTL software writes data into the first memory unit PA1, and the result is as shown in fig. 8 (c). After that, the FTL software erases the reserved memory cell PA0, and the data in the reserved memory cell PA0 is changed from XX2 to FF, as shown in fig. 8 (d). Furthermore, the FTL software copies the data in the first storage unit PA1 to the reserved storage unit PA0, and the data in the reserved storage unit PA0 is changed from FF to FFData ofThe results are shown in FIG. 8 (e). Finally, the FTL software maps the first logical address LA0 to the reserved memory unit PA0 and the reserved address RS to the first memory unit PA1, completing the address translation, the result of which is shown in fig. 8 (f).

For convenience of reading, fig. 8(a) to 8(f) show the changes in the form of groups and underlines.

Mode two

Referring to fig. 9, FTL software maps the first logical address to the reserved memory location and maps the reserved address to the first memory location, completing the address translation (corresponding to step 901). The FTL software then stores the data to the reserved memory location of the first logical address mapping (corresponding to step 902).

In step 902, the case may be included: in case one, if the reserved memory cell is not full of data, data is written from the tail of the stored data. In case two, if the reserved memory cell is full of data, the data is written after the reserved memory cell is erased.

In the case where the reserved memory cell is full of data, referring to fig. 10(a), the mapping of the reserved address RS to the reserved memory cell PA0 and the first logical address LA0 is continued, and the data XX1 stored in the first memory cell PA1 is taken as an example. FTL software maps first logical address LA0 to reserved memory unit PA0 and reserved address RS to first memory unit PA1, completing address translation, the result is shown in fig. 10 (b). Then, the FTL software erases the data XX2 in the reserved memory cell PA0 to become the data FF, with the result as shown in fig. 10 (c). Finally, the FTL software writes to the reserved memory location PA0Data ofThe results are shown in FIG. 10 (d).

In the case that the reserved memory cell is not full of data, referring to fig. 11(a), the mapping of the reserved address RS to the reserved memory cell PA0 and the first logical address LA0 is continued, and the data XX1 stored in the first memory cell PA1 is taken as an example. FTL software maps first logical address LA0 to reserved memory unit PA0 and reserved address RS to first memory unit PA1, completing address translation, the result is shown in fig. 11 (b). The FTL software then writes after reserving data XX2 in memory cell PA0Data ofThe results are shown in FIG. 11 (c).

For convenience of reading, fig. 10(a) to 10(d) and fig. 11(a) to 11(c) are shown in groups and underlined.

And in a second scenario, the reserved storage unit is not adjacent to the first storage unit, and the reserved storage unit is adjacent to the second storage unit. Referring to fig. 12, address translation may include:

the FTL software writes the data to the first memory location (corresponding to step 1201). The manner of writing data into the first storage unit can refer to the contents of fig. 5(a) -5 (b) and fig. 6(a) -6 (c), which are not described herein again.

And, the FTL software erases the reserved memory cell to erase the reserved memory cell (corresponding to step 1202). The FTL software then copies the data in the second storage unit to the reserved storage unit (corresponding to step 1203). Finally, the FTL software maps the reserved address to the second memory location and the second logical address to the reserved memory location, completing the address translation (corresponding to step 1204).

It should be noted that the order of step 1201 and steps 1202 to 1204 is not limited, step 1201 may precede steps 1202 to 1204, step 1201 may follow steps 1202 to 1204, and step 1201 may be executed simultaneously with steps 1202 to 1204. Fig. 13(a) to 13(d) illustrate an example in which step 1201 is executed simultaneously with steps 1202 to 1204.

Referring to fig. 13(a), the reserved memory cell PA0 is mapped with the reserved address RS, and the second logical address LA0 is mapped to the second memory cell PA1, the first logical address LA5 is mapped to the first memory cell PA5, and the reserved memory cell PA0 stores data XX2, the second memory cell PA1 stores data XX3, and the first memory cell PA5 stores data XX 1. Then, the FTL software erases the data XX1 in the first memory cell PA5 to become data FF, and erases the data XX2 in the remaining memory cell PA0 to become data FF, with the result as shown in fig. 13 (b). Thereafter, the FTL software writes the data in the first memory cell PA5 and copies the data XX3 in the second memory cell PA1 into the reserved memory cell PA0, that is, the data FF in the reserved memory cell PA0 becomes XX3, with the result as shown in fig. 13 (c). Finally, FTL software reserves address RS mapping to second memory unit PA1 and second logical address LA0 mapping to reserved memory unit PA0, completing address translation, the result is shown in fig. 13 (d).

Therefore, in this embodiment, after the data storage request is received, the storage frequency of the flash memory device may be determined. Then, whether the storage times and the time threshold value are equal or not is compared, and whether address conversion is carried out on the storage units in the flash memory device or not is determined according to the comparison result. It can be seen that, in the embodiment, by setting the storage time threshold, address conversion is performed on the reserved storage units in the flash memory device when the storage time threshold is reached, so that data is prevented from being written into the same minimum storage unit for many times, and the probability of erasing each minimum storage unit in the flash memory device tends to be consistent, thereby achieving the effect of balancing the erasing times and being beneficial to prolonging the service life of the flash memory device. In addition, in the embodiment, only data of a part of minimum storage units are processed, requirements on storage space and computing resources are low, and the flash memory device is suitable for a flash memory device using a single chip microcomputer MCU as a processor.

In practical applications, in consideration of the situation that the minimum storage unit in the flash memory device may store a bad block, in this embodiment, state information may be set for each minimum storage unit, where the state information may be used to record a health state of each minimum storage unit, and the state information at least includes a health state and other states, and the other states include at least one of the following states: read failure, write failure, and erase failure.

For this reason, when the comparison result is that the storage count is equal to the count threshold, on the basis of the data storage method shown in fig. 1, referring to fig. 14, a data storage method may further include:

first, FTL software obtains status information of each minimum memory cell of the flash memory device (corresponding to step 1401). In this embodiment, the FTL software may obtain the state information of all the minimum storage units in the flash memory device, so that the state information of any one of the minimum storage units may be quickly queried. In this embodiment, the FTL software may further obtain the minimum storage unit related to the data storage and the address translation, so that the obtained data amount is small, and the query speed is fast. Then, when determining that the state information of each minimum memory unit is in a healthy state, the FTL software performs a step of determining whether to perform address translation on the storage unit in the flash memory device according to the comparison result (corresponding to step 1402), and the content of determining whether to perform address translation on the storage unit in the flash memory device according to the comparison result may refer to fig. 1 and related contents, which are not described herein again.

In another embodiment, when it is determined that the state information of the first memory cell of the first logical address mapping is in a state other than a healthy state, the FTL software replaces the first memory cell and performs the step of determining whether to perform address translation on the storage unit stored in the flash memory device according to the comparison result. For determining whether to perform address translation on the storage unit in the flash memory device according to the comparison result, refer to fig. 1 and related contents, which are not described herein again.

In this embodiment, replacing the first storage unit may include: referring to fig. 15(a), since the state information of the first memory cell PA1 is in another state, the FTL software uses the third memory cell PA2 adjacent to the first memory cell PA1 as the replaced first memory cell, and then establishes a mapping relationship between the first logical address LA0 and the replaced first memory cell (i.e., the third memory cell PA2), and as a result, fig. 15(b) shows. The first memory cell PA in fig. 15(a) is a bad block and is shown with a gray background, and the third logical address in fig. 15(b) has no mapping relationship and is also shown with a gray background. Thus, in this embodiment, the bad block (i.e., the first storage unit PA1) can be removed from the mapping relationship, so as to achieve the purpose of managing the bad block. Meanwhile, in this embodiment, the third logical address LA1 is removed from the mapping relationship, so as to ensure the relationship between the logical address and each minimum storage unit in the mapping relationship.

In yet another embodiment, the minimum storage location where the FTL software obtains the status information further includes a reserved storage location. If the state information of the reserved storage unit is in other states, the FTL software takes a minimum storage unit closest to the reserved storage unit as a replaced reserved storage unit, and establishes a mapping relation between a reserved address and the replaced reserved storage unit. Referring to fig. 16(a), when detecting that the state information of the reserved memory cell PA0 is in another state, the FTL software detects that the closest minimum memory cell of the reserved memory cell PA0 is the second memory cell PA1, so that the FTL software uses the second memory cell PA1 as the replaced reserved memory cell and establishes a mapping relationship between the reserved address RS and the second memory cell PA1, and the result is as shown in fig. 16 (b).

It should be noted that the reserved storage unit PA0 before replacement is a bad block, and is removed from the mapping relationship; the second logical address LA0 has no minimum storage unit mapped to it to be culled, the culling being shown with a grey background.

In another embodiment, the minimum storage unit for the FTL software to obtain the status information further includes a second storage unit. If the state information of the second storage unit is in other states, the FTL software takes a minimum storage unit closest to the second storage unit as a reserved storage unit after replacement, and establishes a mapping relationship between the reserved address and the reserved storage unit after replacement. Referring to fig. 17(a), when it is detected that the state information of the second memory cell PA1 is in another state, the FTL software detects that the closest minimum memory cell of the second memory cell PA1 is the fourth memory cell PA2, so that the FTL software uses the fourth memory cell PA2 as the replaced reserved memory cell, establishes a mapping relationship between the reserved address RS and the fourth memory cell PA2, and rejects the second memory cell PA1 and the fourth logical address LA1 represented by the grayscale background, and the result is shown in fig. 17 (b).

Note that the latest minimum memory cell of the replaced reserve memory cell RS is changed from the second memory cell PA1 to the fourth memory cell PA 2. If the reserved storage unit RS needs address translation, the address translation may be performed according to the address translation method shown in fig. 4 or fig. 7, which is not described herein again.

The data storage method provided by the embodiment of the present invention is described below with reference to the embodiment and the drawings, wherein the number threshold is 1, that is, each time a user writes data into the flash memory device, the address RS is reserved for address conversion. In practical applications, the FTL software may present the logical address to the user, and the user selects the logical address to store the data. For convenience of description, in this embodiment, the scheme of this embodiment is described in a manner that a user sequentially selects logical addresses.

Referring to fig. 18(a), the reserved address RS is mapped to the reserved storage location PA0, and the logical addresses LA1 to LA N-1 are sequentially mapped to the minimum storage locations PA1 to PA N, where the minimum storage location SA stores data such as state data and mapping relation required by the FTL software, and the minimum storage location SA is invisible to the application software or the user (shown by oblique line background).

Referring to FIG. 18(b), the first time data is stored, the FTL software detects a user selection to write data to the first logical address LA0, which now maps to PA 1. Since the storage times of the flash memory device reach 1 time and the state information of each minimum memory cell is in a healthy state, the FTL software performs address translation on the reserved memory cell and writes the data XX0, and as a result, as shown in fig. 18(c), the logical address LA0 is mapped to the minimum memory cell PA0, and the storage address is mapped to the minimum memory cell PA1, that is, the minimum memory cell PA1 becomes the reserved memory cell.

Referring to FIG. 18(d), the second time the data is stored, the FTL software detects the user's selection to write the data to the first logical address LA1, which now maps to PA 2. Since the number of times of storage of the flash memory device reaches 1 time, the FTL software detects that the first storage unit PA2 is a bad block (the status information is other status), as shown in fig. 18 (d). The FTL software replaces the first memory cell first, and since the closest memory cell to the minimum memory cell PA2 is the minimum memory cell PA3, the minimum memory cell PA3 is the first memory cell after replacement, and the result is shown in fig. 18 (e). Then, FTL software performs address translation on the reserved memory unit PA1 and writes data XX1, and as a result, as shown in fig. 18(f), the logical address LA1 is mapped to the minimum memory unit PA1, and the saving address RS is mapped to the minimum memory unit PA3, that is, the minimum memory unit PA3 becomes the reserved memory unit.

Thereafter, the user continues to check the data 3, 4, … …, N-3 times, resulting in the result shown in FIG. 18(g), where the save address RS is mapped to the minimum memory location PA N-1.

When the FTL software detects that the user writes data XX N-2 to the minimum storage unit LA0, the result shown in fig. 18(h) is obtained through address translation and data writing.

Thus, fig. 18(a) -18 (h) show the circulation process of the reserved memory cells sequentially passing through the minimum memory cells PA0, PA1, PA3, … … and PA N-1 and returning to the minimum memory cell PA 0.

In this embodiment, the data written by the user can be stored in different minimum storage units by setting the reserved storage units, so that the situation that the erasing times of the same minimum storage unit are increased too fast when the user writes data into the same logical address for multiple times can be avoided, and the effect of balancing the erasing times of each storage unit is achieved. In addition, in the present embodiment, in a scenario where data is written and address translation is not required, FTL software only manages the first storage unit mapped by the first logical address; in a scene of data writing and address conversion, FTL software only manages a first storage unit and a reserved storage unit (which are adjacent to each other); in a scene that data is written in and address conversion is needed and the first storage unit and the reserved storage unit are not adjacent, the FTL software only manages the first storage unit, the reserved storage unit and the second storage unit, namely the number of the storage units managed by the FTL software each time is greatly reduced, the requirements on storage resources and computing resources are low, and the FTL software is suitable for a scene that a single chip microcomputer is adopted as a processor.

Fig. 19 is a block diagram of a flash memory device according to an embodiment of the present invention. Referring to fig. 19, a flash memory apparatus 1900 includes a processor 1901, a memory 1902, and a flash memory device 1904, where the flash memory device has a plurality of minimum memory cells, and each memory cell can be used for data; the processor 1901 communicates with the memory 1902 via a communication bus 1903, and the processor 1901, upon reading executable instructions from the memory 1902, implements:

In some embodiments, the processor 1901 configured to determine the number of times of storage of the flash memory device comprises:

adjusting a recorded number of times of storage, the recorded number of times of storage including a number of times data has been written to the flash memory device;

and reading the recorded storage times to obtain the storage times of the flash memory device.

adjusting the storage times of a first logic address in the data storage request, wherein the storage times of the first logic address are times pointing to data written in the first logic address;

and reading the storage times of the first logic address in the data storage request to obtain the storage times of the flash memory device.

In some embodiments, the processor 1901 configured to determine whether to address-translate a reserved location in the flash memory device according to the comparison comprises:

and if the comparison result shows that the storage times are not equal to the time threshold, determining to keep the current mapping relation of the reserved storage units, and storing the data to a first storage unit mapped by a first logical address in the data storage request.

In some embodiments, the first storage unit of the processor 1901 for storing data to the first logical address mapping in the data storage request comprises:

determining a storage state of a first storage unit;

if the storage state indicates that the first storage unit is not full of data, writing data from the tail of the stored data;

and if the storage state indicates that the first storage unit is full of data, erasing the first storage unit and then writing the data.

and if the comparison result shows that the storage times are equal to the time threshold, determining to perform address conversion on the reserved storage unit.

In some embodiments, if the reserved memory location is adjacent to a first memory location of a first logical address mapping in the data storage request, the processor 1901 configured to perform address translation on the reserved memory location comprises:

writing data to the first memory cell;

erasing the reserved storage unit, and copying the data in the first storage unit to the reserved storage unit;

mapping the first logical address to the reserved storage location and mapping the reserved address to the first storage location, completing address translation.

In some embodiments, the flash memory device includes a reserved memory location mapped with a reserved address; if the reserved memory location is adjacent to the first memory location mapped by the first logical address in the data storage request, the processor 1901 is configured to perform address translation on the reserved memory location and includes:

mapping the reserved address to the first storage unit and mapping the first logic address to the reserved storage unit to complete address translation;

storing data to reserved memory locations of the first logical address mapping.

In some embodiments, the reserved storage locations of the processor 1901 for storing data to the first logical address map comprises:

if the reserved storage unit is not full of data, writing data from the tail of the stored data;

and if the reserved storage unit is full of data, erasing the reserved storage unit and then writing the data.

In some embodiments, the flash memory device includes a reserved storage unit mapped with a reserved address and a second storage unit mapped with a second logical address, the reserved storage unit being adjacent to the second storage unit and not adjacent to the first storage unit, the processor 1901 configured to address convert the reserved storage unit includes:

writing data to the first memory cell; and the number of the first and second groups,

erasing the reserved storage unit, and copying the data in the second storage unit to the reserved storage unit;

and mapping the reserved address to the second storage unit and mapping the second logic address to the reserved storage unit to finish address translation.

In some embodiments, if the comparison result is that the storage count is equal to the count threshold, the processor 1901 is further configured to:

acquiring state information of each minimum storage unit in the flash memory device; the state information is used for recording the health state of each minimum storage unit; the status information comprises at least a health status;

and if the state information of each minimum storage unit is in a healthy state, determining whether to perform address conversion on the storage units in the flash memory device according to the comparison result.

In some embodiments, the minimum storage units include a first storage unit, and after the processor 1901 is configured to obtain the state information of the minimum storage units in the flash memory device, the processor is further configured to:

and if the state information of the first storage unit of the first logical address mapping is in other states except the healthy state, replacing the first storage unit and executing the step of determining whether to perform address conversion on the storage unit in the flash memory device according to the comparison result.

In some embodiments, the processor 1901 configured to replace the first storage unit comprises:

and taking a third storage unit adjacent to the first storage unit as a replaced first storage unit, and establishing a mapping relation between the first logic address and the replaced first storage unit.

In some embodiments, the minimum storage units include reserved storage units, and after the processor 1901 is configured to obtain the state information of the minimum storage units in the flash memory device, the processor is further configured to:

and if the state information of the reserved storage unit is in other states, taking a minimum storage unit closest to the reserved storage unit as a replaced reserved storage unit, and establishing a mapping relation between a reserved address and the replaced reserved storage unit.

In some embodiments, the minimum storage units include a second storage unit adjacent to the reserved storage unit, and after the processor 1901 is configured to obtain the state information of the minimum storage units in the flash memory device, the processor is further configured to:

and if the state information of the second storage unit is in other states, taking a fourth storage unit adjacent to the second storage unit as a replaced second storage unit, and establishing a mapping relation between the second logic address and the replaced second storage unit.

In some embodiments, the other states include at least one of: read failure, write failure, and erase failure.

In some embodiments, any storage unit in the flash memory device stores a mapping relationship between the first logical address and the first storage unit and a mapping relationship between the reserved address and the reserved storage unit.

In some embodiments, the any memory cell is a last memory cell in the flash memory device.

The embodiment of the invention also provides an intelligent battery, and fig. 19 is a block diagram of the intelligent battery provided by the embodiment of the invention. Referring to fig. 20, a smart battery 2000 is characterized by comprising a processor 2001, a memory 2002 and a flash memory device 2004, wherein the flash memory device 2004 is provided with a plurality of minimum storage units, and the processor 2001 realizes that after reading executable instructions from the memory 2002:

In some embodiments, the processor 2001 is configured to determine the number of times the flash memory device is stored includes:

In some embodiments, the processor 2001 is configured to determine whether to perform address translation on a reserved memory location in the flash memory device according to the comparison result includes:

In some embodiments, the first storage unit of the processor 2001 for storing data to the first logical address mapping in the data store request comprises:

determining a storage state of a first storage unit;

In some embodiments, if the reserved memory location is adjacent to the first memory location of the first logical address mapping in the data storage request, the processor 2001 is configured to perform address translation on the reserved memory location, including:

writing data to the first memory cell;

In some embodiments, the flash memory device includes a reserved memory location mapped with a reserved address; if the reserved memory location is adjacent to the first memory location mapped by the first logical address in the data storage request, the processor 2001 is configured to perform address translation on the reserved memory location, including:

storing data to reserved memory locations of the first logical address mapping.

In some embodiments, the reserved storage locations of the processor 2001 for storing data to the first logical address map include:

In some embodiments, the flash memory device comprises a reserved memory location mapped with a reserved address and a second memory location mapped with a second logical address, the reserved memory location being adjacent to the second memory location and not adjacent to the first memory location, the processor 2001 is configured to perform address translation on the reserved memory location comprising:

In some embodiments, if the comparison result is that the storage count is equal to the count threshold, the processor 2001 is further configured to:

In some embodiments, the minimum storage units include a first storage unit, and the processor 2001 is configured to, after obtaining the state information of the minimum storage units in the flash memory device, further:

In some embodiments, the processor 2001 for replacing the first storage unit includes:

In some embodiments, the minimum storage units include reserved storage units, and the processor 2001 is configured to, after obtaining the state information of the minimum storage units in the flash memory device, further:

In some embodiments, the minimum storage units include a second storage unit adjacent to the reserved storage unit, and after the processor 2001 is configured to obtain the state information of the minimum storage units in the flash memory device, the processor is further configured to:

The embodiment of the invention also provides a movable platform which can comprise the intelligent battery. Wherein, portable platform can be for equipment such as unmanned aerial vehicle, smart mobile phone, panel computer, handheld equipment of shooing.

The embodiments of the present invention further provide a readable storage medium, where a plurality of computer instructions are stored on the readable storage medium, and when the computer instructions are executed, the steps of the data storage method shown in the foregoing embodiments are implemented, and specific contents may refer to the embodiments of the data storage method, and are not described herein again.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above detailed description of the detection apparatus and method provided by the embodiments of the present invention has been presented, and the present invention has been made by applying specific examples to explain the principle and the implementation of the present invention, and the above description of the embodiments is only used to help understanding the method and the core idea of the present invention; to sum up, the present disclosure should not be construed as limiting the invention, which will be described in the following description but will be modified within the scope of the invention by the spirit of the present disclosure.

Claims

1. A method of storing data, comprising:

2. The data storage method of claim 1, wherein determining the number of times the flash memory device stores comprises:

3. The data storage method of claim 1, wherein determining the number of times the flash memory device stores comprises:

4. The data storage method of claim 1, wherein determining whether to address-translate a retention location in the flash memory device according to the comparison comprises:

5. The data storage method of claim 4, wherein storing data to the first storage location of the first logical address map in the data storage request comprises:

determining a storage state of a first storage unit;

6. The data storage method of claim 1, wherein determining whether to address-translate a retention location in the flash memory device according to the comparison comprises:

7. The data storage method of claim 6, wherein if the reserved memory location is adjacent to a first memory location of a first logical address mapping in the data storage request, performing address translation on the reserved memory location comprises:

writing data to the first memory cell;

8. The data storage method of claim 6, wherein the flash memory device includes a reserved memory location mapped with a reserved address; if the reserved memory cell is adjacent to the first memory cell mapped by the first logical address in the data storage request, performing address translation on the reserved memory cell comprises:

storing data to reserved memory locations of the first logical address mapping.

9. The data storage method of claim 8, wherein storing data to the reserved memory locations of the first logical address map comprises:

10. The data storage method of claim 6, wherein the flash memory device includes a reserved memory location mapped to a reserved address and a second memory location mapped to a second logical address, the reserved memory location being adjacent to the second memory location and not adjacent to the first memory location, wherein address translating the reserved memory location comprises:

11. The data storage method of claim 6, wherein if the comparison result indicates that the storage count is equal to the count threshold, the method further comprises:

12. The data storage method according to claim 11, wherein the minimum storage units include a first storage unit, and after the status information of the minimum storage units in the flash memory device is obtained, the method further comprises:

13. The data storage method of claim 12, wherein replacing the first storage unit comprises:

14. The data storage method according to claim 12, wherein the minimum storage units include reserved storage units, and after the status information of the minimum storage units in the flash memory device is obtained, the method further comprises:

15. The data storage method according to claim 12, wherein the minimum storage units include a second storage unit adjacent to the reserved storage unit, and after the status information of the minimum storage units in the flash memory device is obtained, the method further comprises:

16. A data storage method according to any one of claims 12 to 15, wherein said other states include at least one of: read failure, write failure, and erase failure.

17. The data storage method according to claim 1, wherein any storage unit in the flash memory device stores a mapping relationship between the first logical address and the first storage unit and a mapping relationship between the reserved address and the reserved storage unit.

18. The data storage method of claim 17, wherein the any memory cell is a last memory cell in the flash memory device.

19. A flash memory device is characterized by comprising a processor, a memory and a flash memory device, wherein the flash memory device is provided with a plurality of minimum storage units, and the processor realizes that after reading executable instructions from the memory:

20. The flash memory apparatus of claim 19, wherein the processor is configured to determine a number of times the flash memory device has been stored comprises:

21. The flash memory apparatus of claim 19, wherein the processor is configured to determine a number of times the flash memory device has been stored comprises:

22. The flash memory apparatus of claim 19, wherein the processor configured to determine whether to address-translate a persistent storage unit in the flash memory device according to the comparison comprises:

23. The flash memory device of claim 22, wherein the processor is configured to store data to the first storage location of the first logical address map in the data storage request comprises:

determining a storage state of a first storage unit;

24. The flash memory apparatus of claim 19, wherein the processor configured to determine whether to address-translate a persistent storage unit in the flash memory device according to the comparison comprises:

25. The flash memory device of claim 24, wherein if the reserved memory location is adjacent to the first memory location of the first logical address map in the data storage request, the processor is configured to address convert the reserved memory location comprising:

writing data to the first memory cell;

26. The flash memory apparatus of claim 24, wherein the flash memory device comprises a reserved memory location mapped with a reserved address; if the reserved memory location is adjacent to a first memory location mapped by a first logical address in the data storage request, the performing, by the processor, address translation on the reserved memory location includes:

storing data to reserved memory locations of the first logical address mapping.

27. The flash memory device of claim 26, wherein the processor is configured to store data to the reserved storage location of the first logical address map comprises:

28. The flash memory apparatus of claim 24, wherein the flash memory device comprises a reserved memory location mapped to a reserved address and a second memory location mapped to a second logical address, the reserved memory location being adjacent to the second memory location and not adjacent to the first memory location, and wherein the processor is configured to address translate the reserved memory location comprising:

29. The flash memory device of claim 24, wherein if the comparison result is that the number of times of storage is equal to the number threshold, the processor is further configured to:

30. The flash memory device of claim 29, wherein the minimum storage units comprise a first storage unit, and the processor is configured to, after obtaining the state information of the minimum storage units in the flash memory device, further:

31. The flash memory device of claim 30, wherein the processor being configured to replace the first memory unit comprises:

32. The flash memory device of claim 30, wherein the minimum storage units comprise reserved storage units, and the processor is configured to, after obtaining the state information of the minimum storage units in the flash memory device, further:

33. The flash memory device of claim 30, wherein the minimum storage units comprise a second storage unit adjacent to the reserved storage unit, and the processor is configured to, after obtaining the status information of the minimum storage units in the flash memory device, further:

34. The flash memory device according to any of claims 30 to 33, wherein the other states comprise at least one of: read failure, write failure, and erase failure.

35. The flash memory device of claim 19, wherein any memory cell in the flash memory device stores a mapping between the first logical address and the first memory cell and a mapping between the reserved address and the reserved memory cell.

36. The flash memory device of claim 35 wherein said any memory cell is the last memory cell in said flash memory device.

37. An intelligent battery, comprising a processor, a memory and a flash memory device, wherein the flash memory device is provided with a plurality of minimum storage units, and the processor realizes that after reading executable instructions from the memory:

38. The smart battery of claim 37, wherein the processor is configured to determine a number of times the flash memory device has been stored comprises:

39. The smart battery of claim 37, wherein the processor is configured to determine a number of times the flash memory device has been stored comprises:

40. The smart battery of claim 37, wherein the processor configured to determine whether to address-translate a persistent storage unit in the flash memory device according to the comparison comprises:

41. The smart battery of claim 40, wherein the processor is configured to store data to the first storage location of the first logical address mapping in the data storage request comprises:

determining a storage state of a first storage unit;

42. The smart battery of claim 37, wherein the processor configured to determine whether to address-translate a persistent storage unit in the flash memory device according to the comparison comprises:

43. The smart battery of claim 42, wherein the processor, if the reserved memory location is adjacent to a first memory location of a first logical address mapping in the data storage request, is configured to perform address translation for the reserved memory location comprising:

writing data to the first memory cell;

44. The smart battery of claim 42 wherein the flash memory device comprises a reserved memory location mapped with a reserved address; if the reserved memory location is adjacent to a first memory location mapped by a first logical address in the data storage request, the performing, by the processor, address translation on the reserved memory location includes:

storing data to reserved memory locations of the first logical address mapping.

45. The smart battery of claim 44 wherein the processor is configured to store data to the reserved storage location of the first logical address mapping comprises:

46. The smart battery of claim 42, wherein the flash memory device comprises a reserved memory location mapped to a reserved address and a second memory location mapped to a second logical address, the reserved memory location being adjacent to the second memory location and not adjacent to the first memory location, wherein the processor is configured to address translate the reserved memory location comprising:

47. The smart battery of claim 42, wherein if the comparison result indicates that the number of times of storage is equal to the number threshold, the processor is further configured to:

48. The smart battery of claim 47, wherein the minimum storage units comprise a first storage unit, and the processor is configured to, after obtaining the status information of the minimum storage units in the flash memory device, further:

49. The smart battery of claim 48, wherein the processor being configured to replace the first storage unit comprises:

50. The smart battery of claim 48, wherein the minimum storage units comprise reserved storage units, and the processor is configured to, after obtaining the status information of the minimum storage units in the flash memory device, further:

51. The smart battery of claim 48, wherein the minimum storage units comprise a second storage unit adjacent to the reserved storage unit, and the processor is configured to, after obtaining the status information of the minimum storage units in the flash memory device, further:

52. The smart battery of any of claims 48-51, wherein the other states comprise at least one of: read failure, write failure, and erase failure.

53. The smart battery of claim 37, wherein any of the storage units in the flash memory device stores a mapping relationship between the first logical address and the first storage unit and a mapping relationship between the reserved address and the reserved storage unit.

54. The smart battery of claim 553, wherein the any memory cell is a last memory cell in the flash memory device.

55. A mobile platform comprising the smart battery of any one of claims 37-54.

56. A readable storage medium having stored thereon computer instructions which, when executed, implement the steps of the method of any one of claims 1 to 18.