CN110797077B - Memory chip, data processing circuit and data processing method thereof - Google Patents
Memory chip, data processing circuit and data processing method thereof Download PDFInfo
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Abstract
The invention discloses a memory chip, a data processing circuit and a data processing method thereof. In the test mode, the data pattern generator automatically starts a preset test command, test data are generated based on the preset test command, the test data are subjected to parallel-serial conversion through the parallel-serial conversion circuit to generate a first data signal, the first data signal is used for controlling the port driving module to output a first result, and power consumption parameters of the memory chip are monitored based on the first result. Data do not need to be written in advance, and the test time is shortened; and the test sampling interval is not limited by the maximum address upper limit of the data, so that the test difficulty is reduced, and the test precision is improved.
Description
Technical Field
The invention relates to the technical field of memory chips, in particular to a memory chip, a data processing circuit and a data processing method thereof.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present. Memory chips are an important electronic component of electronic devices. The memory chip requires a built-in circuit for power consumption testing.
Referring to fig. 1 and 2, fig. 1 is a circuit diagram of a test system when a conventional memory chip performs a power consumption test, and fig. 2 is a schematic diagram of a built-in circuit used for performing the power consumption test in the memory chip, when the memory chip is subjected to the power consumption test, it is necessary to control and supply power to the memory chip 12 through a tester 11, and receive output data of the memory chip 12, and perform processing judgment to confirm the power consumption. The tester 11 may control the memory chips 12 to operate in different test modes to measure the average power consumption of the memory chips 12. Wherein, test machine 11 includes: a power module 111 for supplying power to the memory chip 12; a control module 112 for command input to the memory chip 12; and the data processing module 113 is configured to obtain data output of the memory chip 12, and perform data processing to obtain power consumption data. The power consumption test of the memory chip 12 is related to the data content and can be implemented using existing user commands.
In the conventional memory chip 12, as shown in fig. 2, after a command is input through another circuit 121, a logic controller 126 is triggered to turn on a parallel-serial conversion circuit 124 and a port driving module 125, so that data stored in a storage array 122 sequentially passes through a sense amplifier circuit 123, the parallel-serial conversion circuit 124 and the port driving module 125, and then data output is realized. The memory chip 12 has at least two voltage domains, such as a core voltage domain and a data transmission voltage domain, and the power consumption test principle for the data transmission voltage domain is shown in fig. 3.
Referring to fig. 3, fig. 3 is a flowchart of a method for performing a power consumption test on a conventional memory chip, in which after a write command, write data, and read command and read data are sequentially completed, whether the data reaches a maximum address is determined, if so, data output does not roll, data reading is ended, and if not, data reading is continued until the maximum read address is reached, and data reading is ended.
As can be seen from the above description, when the power consumption test is performed on the conventional memory chip 12, the operation steps are multiple, data needs to be written in first according to the test rule, so that the test time is increased, the test is not convenient to continue, the memory data of the memory array needs to be read in the test process, the power consumption test needs to be completed before the maximum read address is reached, and the test difficulty is increased.
Disclosure of Invention
In view of this, the present application provides a memory chip, a data processing circuit thereof, and a data processing method thereof, and the scheme is as follows:
a data processing circuit of a memory chip, comprising:
the device comprises a data pattern generator, a parallel-serial conversion circuit and a port driving module;
in a test mode, the data pattern generator is used for automatically starting a preset test command, generating test data based on the preset test command, performing parallel-to-serial conversion on the test data through the parallel-to-serial conversion circuit to generate a first data signal, the first data signal being used for controlling the port driving module to output a first result, and monitoring the power consumption parameter of the memory chip based on the first result.
Preferably, the data processing circuit further includes: a sensitive amplifying circuit;
in a data reading mode, the storage data in the storage array is subjected to parallel-serial conversion through the amplification of the sensitive amplifying circuit and the parallel-serial conversion circuit in sequence to generate a second data signal, the second data signal is used for controlling the port driving module to output a second result, and the second result is used for representing the storage data.
Preferably, in the data processing circuit, the data pattern generator and the sensitive amplifying circuit are connected to the parallel-serial conversion circuit through the same two-way gate;
the first input end of the double-path gate is connected with the data pattern generator, the second input end of the double-path gate is connected with the sensitive amplifying circuit, and the output end of the double-path gate is connected with the input end of the parallel-serial conversion circuit.
Preferably, in the data processing circuit, the sensitive amplifying circuit includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a storage capacitor and a latch;
the control electrode of the first MOS tube is used for inputting a first control signal, the first electrode of the first MOS tube is connected with a power supply, and the second electrode of the first MOS tube is connected with a common node;
the control electrode of the second MOS tube is used for inputting a second control signal, the first electrode of the second MOS tube is connected with the common node, and the second electrode of the second MOS tube is connected with the first electrode of the third MOS tube;
the control electrode of the third MOS tube is used for inputting a third control signal, and the second electrode of the third MOS tube is used for connecting the storage array;
one polar plate of the storage capacitor is connected with the common node, and the other polar plate is grounded;
the input end of the latch is connected with the common node, and the output end of the latch is used for outputting the amplified storage data.
Preferably, the data processing circuit further includes: a logic controller;
in a test mode, the logic controller is configured to execute a test instruction to control a first input end of the two-way gate to be connected to an output end of the two-way gate, and control the parallel-serial conversion circuit and the port driving module to be turned on, so that test data output by the graphics generator sequentially passes through the two-way gate, the parallel-serial conversion circuit and the port driving module, and then outputs the first result;
in the data reading mode, the logic controller is further configured to execute a data reading instruction to control a second input end of the two-way gate to be connected to an output end of the two-way gate, and control the parallel-serial conversion circuit and the port driving module to be turned on, so that the stored data sequentially passes through the two-way gate, the parallel-serial conversion circuit and the port driving module, and then the second result is output.
Preferably, in the data processing circuit, the data pattern generator includes: the system comprises a random data generator, a protocol data generator, an extreme value data generator and a three-way gate;
the random data generator is connected with a first input end of the three-way gate and is used for outputting random data;
the second input end of the three-way gate of the protocol data generator is connected, and the protocol data generator is used for outputting data following a communication protocol;
the extreme value data generator is connected with a third input end of the three-way gate and is used for outputting limit value data;
the three-way gate is used for selecting data input by one input end of the three-way gate to be used as the test data and outputting the test data through an output end of the three-way gate.
Preferably, in the data processing circuit, the port driver module includes: the device comprises a trigger D, a control circuit, a pull-up MOS tube, a pull-down MOS tube and a load capacitor;
a first electrode of the pull-up MOS tube is connected with a power supply, and a second electrode of the pull-up MOS tube is connected with the output end of the port driving module; a first electrode of the pull-down MOS tube is connected with the output end of the port driving module; the control electrodes of the pull-up MOS tube and the pull-down MOS tube are respectively connected with one output end of the control circuit; the output end of the port driving module is grounded through the load capacitor;
one input end of the D trigger is used for inputting an enabling signal, the other input end of the D trigger is connected with the output end of the parallel-serial conversion circuit, and the output end of the D trigger is connected with the input end of the control circuit;
and the control circuit controls the conduction of the pull-up MOS tube and the pull-down MOS tube based on the output signal of the D trigger so as to control the output result of the output end of the port driving module.
The present invention also provides a memory chip comprising:
a data processing circuit as claimed in any preceding claim.
The invention also provides a data processing method of the memory chip, which comprises the following steps:
and acquiring a measurement result of the memory chip by adopting the data processing circuit to determine a power consumption parameter.
As can be seen from the above description, in the memory chip, the data processing circuit and the data processing method provided in the technical solution of the present invention, the data processing circuit built in the memory chip includes a data pattern generator, a parallel-to-serial conversion circuit and a port driver module. In a test mode, the data pattern generator automatically starts a preset test command, test data are generated based on the preset test command, the test data are subjected to parallel-serial conversion through the parallel-serial conversion circuit to generate a first data signal, the first data signal is used for controlling the port driving module to output a first result, and power consumption parameters of the memory chip are monitored based on the first result. Therefore, the data pattern generator automatically starts the preset test command without independently writing the command operation, so that the test operation steps are simplified, the operation is simple, the test time is shortened, and the power consumption test efficiency is improved. Moreover, the data pattern generator can directly generate test data based on a preset test command, a data storage output process is not required to be performed through a storage array, the limitation of the maximum address upper limit is avoided, the test difficulty is reduced, and the test precision is improved.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a circuit diagram of a test system for power consumption testing of a conventional memory chip;
FIG. 2 is a schematic diagram of a built-in circuit for performing power consumption testing in a memory chip;
FIG. 3 is a flowchart of a method for performing a power consumption test on a conventional memory chip;
FIG. 4 is a schematic structural diagram of a data processing circuit of a memory chip according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a data processing circuit of another memory chip according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a data processing circuit of a memory chip according to another embodiment of the present invention;
FIG. 7 is a schematic diagram of a data processing circuit of a memory chip according to another embodiment of the present invention;
fig. 8 is a schematic structural diagram of a sensitive amplifying circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a data pattern generator according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a port driver module according to an embodiment of the present invention;
fig. 11 is a flowchart of a method for processing data of a memory chip according to an embodiment of the present invention.
Detailed Description
The embodiments of the present application will be described in detail and fully with reference to the accompanying drawings, wherein the description is only for the purpose of illustrating the embodiments of the present application and is not intended to limit the scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a data processing circuit of a memory chip according to an embodiment of the present invention, where the data processing circuit includes: a data pattern generator 21, a parallel-to-serial conversion circuit 22 and a port driving module 23.
In the test mode, the data pattern generator 21 is configured to automatically start a preset test command, output test data based on the preset test command, perform parallel-to-serial conversion on the test data through the parallel-to-serial conversion circuit 22 to generate a first data signal, where the first data signal is used to control the port driving module 23 to output a first result, and monitor a power consumption parameter of the memory chip based on the first result.
In the data processing circuit of the embodiment of the invention, the data pattern generator 21 automatically starts the preset test command without independently writing the command operation, thereby simplifying the test operation steps, simplifying the operation, shortening the test time and improving the power consumption test efficiency. Moreover, the data pattern generator 21 can directly generate test data based on the preset test command, a storage data output process through a storage array of a memory chip is not needed, the limitation of the maximum address upper limit is avoided, the test difficulty is reduced, and the test precision is improved.
The data processing circuit is suitable for testing the power consumption of a data transmission voltage domain related circuit in a memory chip, namely testing the power consumption of the parallel-serial conversion circuit 22 and the port driving module 23.
Referring to fig. 5, fig. 5 is a schematic structural diagram of another data processing circuit of a memory chip according to an embodiment of the present invention, and based on the manner shown in fig. 4, the data processing circuit further includes: a sensitive amplification circuit 24; in a data reading mode, the storage data in the storage array is amplified by the sensitive amplifying circuit 24 and is subjected to parallel-to-serial conversion by the parallel-to-serial conversion circuit 22 in sequence to generate a second data signal, the second data signal is used for controlling the port driving module 23 to output a second result, and the second result is used for representing the storage data.
In the manner shown in fig. 5, based on the user operation, a power consumption test mode may be selected to conduct the data pattern generator 21 and the parallel-serial conversion circuit 22, and the power consumption test mode is conducted, at this time, the sense amplifier circuit 24 and the parallel-serial conversion circuit 22 are disconnected, or a data reading mode may be selected to conduct the sense amplifier circuit 24 and the parallel-serial conversion circuit 22, and data reading is conducted, at this time, the data pattern generator 21 and the parallel-serial conversion circuit 22 are disconnected. In this way, the same parallel-serial conversion circuit 22 and the same port driving module 23 can be multiplexed, power consumption testing is performed in the test mode, data reading is performed in the data reading mode, and the circuit structure of the memory chip is simple.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a data processing circuit of another memory chip according to an embodiment of the present invention, and based on the manner shown in fig. 5, the data pattern generator 21 and the sensitive amplifying circuit 24 are connected to the parallel-serial conversion circuit 22 through the same two-way gate 25; a first input end of the two-way gate 25 is connected to the data pattern generator 21, a second input end of the two-way gate 25 is connected to the sensitive amplifying circuit 24, and an output end of the two-way gate 25 is connected to an input end of the parallel-serial conversion circuit 22. The two-way gate 25 can select one input terminal to be conducted with the output terminal thereof and make the other input terminal be disconnected with the output terminal thereof based on the control signal of the control terminal.
In other ways, the data pattern generator 21 and the sensitive amplifying circuit 24 may be connected to the parallel-serial conversion circuit 22 through a switch respectively.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a data processing circuit of a memory chip according to another embodiment of the present invention, and based on the manner shown in fig. 6, the data processing circuit further includes: a logic controller 26; the logic controller 26 is connected to the two- way gates 25 and 22 and the respective control terminals of the port driving module 23. In the test mode, the logic controller 26 is configured to execute a test instruction to control a first input terminal of the two-way gate 25 to be connected to an output terminal of the two-way gate 25, and control the parallel-serial conversion circuit 22 and the port driving module 23 to be turned on, so that the test data output by the pattern generator 21 sequentially passes through the two-way gate 25, the parallel-serial conversion circuit 22 and the port driving module 23, and then outputs the first result; in the data reading mode, the logic controller is further configured to execute a data reading instruction to control a second input end of the two-way gate 25 to be connected to an output end of the two-way gate 25, and control the parallel-serial conversion circuit 22 and the port driving module 23 to be turned on, so that the stored data sequentially passes through the two-way gate 25, the parallel-serial conversion circuit 22 and the port driving module 23, and then the second result is output.
In the manner shown in fig. 7, the data pattern generator 21 may be automatically triggered to enter the test mode based on a user operation, and a test command may be input to the logic controller 26 to start the power consumption test, and control the parallel-serial conversion circuit and the port driver module to be turned on.
In the embodiment of the present invention, the sensitive amplifying circuit 24 may be as shown in fig. 8.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a sensitive amplifying circuit according to an embodiment of the present invention, where the sensitive amplifying circuit includes: first MOS transistor MPCHA second MOS transistor MSELAnd a third MOS transistor MHVAnd a storage capacitor CSOAnd a LATCH LATCH; the first MOS transistor MPCHFor inputting a first control signal PCH, a first electrical signal ofA pole of the power supply is connected with a power supply VDD, and a second pole of the power supply is connected with a common node SO; the second MOS transistor MSELThe control electrode of (1) is used for inputting a second control signal SEL, the first electrode of the control electrode is connected with the common node SO, and the second electrode of the control electrode is connected with the third MOS tube MHVA first electrode of (a); the third MOS transistor MHVThe control electrode of (a) is used for inputting a third control signal HV, and the second electrode of the control electrode of (b) is used for connecting the storage array; the storage capacitor CSOOne of the plates is connected to the common node SO and the other plate is grounded; the LATCH has an input terminal connected to the common node SO, and an output terminal OUT for outputting the amplified storage data.
The memory array of the memory chip has a plurality of memory cells for storing data. Each MOS tube controls the switching state of the first electrode and the second electrode through a control signal input by the control electrode of the MOS tube. Optionally, the first MOS transistor MPCHIs PMOS, the second MOS transistor MSELAnd a third MOS transistor MHVIs an NMOS. The LATCH control terminal of the LATCH performs LATCH control by a LATCH control signal LAT. The third MOS transistor MHVIs connected with the corresponding memory cell through the bit line bl (n) to acquire the memory data.
The sensitive amplifying circuit 24 can amplify and transmit weak signals in the memory array. The basic operation flow is gating-precharging-discharging-detecting-latching output, in particular to a second MOS tube MSELGating the memory cells in the memory array through the first MOS transistor MPCHAnd a common node SO is precharged, the storage unit is enabled to discharge to the common node SO through the third MOS tube, and when the LATCH LATCH detects the voltage change of the common node SO, data judgment and latching are completed within a set time and output is performed.
In the embodiment of the present invention, the data pattern generator 21 may be as shown in fig. 9.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a data pattern generator according to an embodiment of the present invention, where the data pattern generator 21 includes: a random data generator 211, a protocol data generator 212, an extreme data generator 213, and a three-way gate 214; the random data generator 211 is connected to a first input terminal of the three-way gate 214, and the random data generator 211 is configured to output random data; the protocol data generator 212 is connected to a second input terminal of the three-way gate 214, and the protocol data generator 212 is configured to output data conforming to a communication protocol; the extreme data generator 213 is connected to the third input terminal of the three-way gate 214, and the extreme data generator 213 is configured to output extreme data; the three-way gate 214 is configured to select data input at one input end thereof as the test data, and output the test data through an output end thereof, so as to complete power consumption tests in different modes under different test data.
The data pattern generator 21 may select different test modes based on the input command Mode <1:0> to provide different data outputs based on the test modes. If the setting command Mode <1:0> is 00, the random data generator 211 is invoked, so that the output signal pdg of the data pattern generator 21 is random data; if the command Mode <1:0> -01 is set, the protocol data generator 212 is invoked, so that the output signal pdg of the data pattern generator 21 follows the protocol requirements, such as 5A-AA-a5-55 cycles; if the command Mode <1:0> is set to 10, the extremum data generator 213 is invoked, so that the output signal pdg of the data pattern generator 21 may be, for example, a 00-FF cycle, depending on the chip design. Wherein A and F are hexadecimal numbers.
The logic controller 26 controls the gating state of the two-way gate 25 through a control signal Bist _ en. If the control signal Bist _ en can be set to 1, the two-way gate 25 selects the output signal pgd of the data pattern generator 21 as the output signal gd of the two-way gate 25, sets the control signal Bist _ en to 0, and the two-way gate 25 selects the output signal agd of the sense amplifier circuit 24 as the output signal gd of the two-way gate 25.
The parallel-serial conversion circuit 22 serializes the output signal gd having a certain bit width, and converts the serialized output signal gd into single-bit data sout for output. The logic controller 26 controls the parallel-serial conversion circuit 22 through the control signal Bist _ en, and enables the parallel-serial conversion circuit 22 to perform data conversion if the control signal Bist _ en is equal to 1.
The logic controller 26 may receive the test command, enter the built-in power consumption test mode, set the control signal Bist _ en to 1, and set the control signal io _ en to 1. The control signal io _ en ═ 1 enables the port driver module 23.
In the embodiment of the present invention, the port driving module 23 may be as shown in fig. 10.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a port driver module according to an embodiment of the present invention, where the port driver module 23 includes: the D flip-flop 231, the control circuit 232, the pull-up MOS transistor M1, the pull-down MOS transistor M2, and the load capacitor C0; the port driver module 23 is an IO (input output) driver.
A first electrode of the pull-up MOS transistor M1 is connected to a power supply VDD, and a second electrode thereof is connected to an output terminal PAD of the port driving module 23; a first electrode of the pull-down MOS transistor M2 is connected to an output terminal PAD of the port driving module 23; the control electrodes of the pull-up MOS transistor M1 and the pull-down MOS transistor M2 are respectively connected to an output terminal of the control circuit 232; the output PAD of the port driving module 23 is grounded through the load capacitor C0; one input end endred of the D flip-flop 231 is used for inputting an enable signal enable, and the other input end DATA # is connected to the output end of the parallel-serial conversion circuit 22 to obtain an output signal sout of the parallel-serial conversion circuit 22, and the output end thereof is connected to the input end of the control circuit 232; the control circuit 232 controls the conduction of the pull-up MOS transistor M1 and the pull-down MOS transistor M2 based on the output signal of the D flip-flop 231, so as to control the output result of the output terminal of the port driving module 23. The pull-up MOS transistor M1 may be a PMOS, and the pull-down MOS transistor M2 may be an NMOS.
In the power consumption test mode, the port driving module 23 is configured to amplify the weak signal sout, the control signal io _ en is 1, the port driving module 23 is enabled, and the output PAD of the port driving module 23 outputs power consumption test data.
When the memory chip according to the embodiment of the present invention performs the test mode based on the user input operation, the data pattern generator 21 may select the data pattern, that is, execute the preset test instruction, so as to generate the corresponding test data based on the preset test instruction. The test is started by the test command, and the data pattern is gated to the global data signal, and is output by the port driving module 23 after the parallel-serial conversion is completed. And the power consumption test period can be continuously tested, after the test is finished, the data output is stopped through the test command, and the test mode operation is exited.
As can be seen, the test data of the data processing circuit is set by the data pattern generator 21, and data does not need to be written in advance, thereby shortening the test time; and the test sampling interval is not limited by the maximum address upper limit of the data, so that the test difficulty is reduced, and the test precision is improved.
Based on the foregoing embodiment, another embodiment of the present invention further provides a memory chip, where the memory chip includes the data processing circuit described in the foregoing embodiment, and test data is set by the data pattern generator, so that data does not need to be written in advance, and test time is shortened; and the test sampling interval is not limited by the maximum address upper limit of the data, so that the test difficulty is reduced, and the test precision is improved.
Based on the foregoing embodiment, another embodiment of the present invention further provides a data processing method for a memory chip, where the data processing method includes: the data processing circuit described in the above embodiment is used to obtain the measurement result of the memory chip to determine the power consumption parameter.
The data processing method adopts the data processing circuit described in the above embodiment to obtain the measurement result of the memory chip to determine the power consumption parameter, the test data is set by the data pattern generator, the data does not need to be written in advance, and the test time is shortened; the test sampling interval is not limited by the maximum address upper limit of data, the test difficulty is reduced, and the test precision is favorably improved
Fig. 11 shows a method for performing a power consumption test by the data processing circuit, where fig. 11 is a flowchart of a method for processing data of a memory chip according to an embodiment of the present invention, and after a test mode is set, a test command is automatically started, so that data can be continuously read out, and after the test command is terminated, the process is terminated. Wherein, different test modes can be set by commands in the continuous data reading device to perform the average power consumption test.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. For the memory chip and the data processing method disclosed by the embodiment, since the memory chip and the data processing method disclosed by the embodiment correspond to each other, the description is relatively simple, and relevant points can be described by referring to the corresponding part of the memory chip.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A data processing circuit of a memory chip, comprising:
the device comprises a data pattern generator, a parallel-serial conversion circuit and a port driving module;
in a test mode, the data pattern generator is used for automatically starting a preset test command, generating test data based on the preset test command, performing parallel-to-serial conversion on the test data through the parallel-to-serial conversion circuit to generate a first data signal, wherein the first data signal is used for controlling the port driving module to output a first result, and monitoring power consumption parameters of a data transmission voltage domain related circuit in the memory chip based on the first result, and the data transmission voltage domain related circuit comprises the parallel-to-serial conversion circuit and the port driving module.
2. The data processing circuit of claim 1, further comprising: a sensitive amplifying circuit;
in a data reading mode, the storage data in the storage array is subjected to parallel-serial conversion through the amplification of the sensitive amplifying circuit and the parallel-serial conversion circuit in sequence to generate a second data signal, the second data signal is used for controlling the port driving module to output a second result, and the second result is used for representing the storage data.
3. The data processing circuit of claim 2, wherein the data pattern generator and the sensitive amplifying circuit are connected to the parallel-to-serial conversion circuit through the same two-way gate;
the first input end of the double-path gate is connected with the data pattern generator, the second input end of the double-path gate is connected with the sensitive amplifying circuit, and the output end of the double-path gate is connected with the input end of the parallel-serial conversion circuit.
4. The data processing circuit of claim 2, wherein the sensitive amplification circuit comprises: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a storage capacitor and a latch;
the control electrode of the first MOS tube is used for inputting a first control signal, the first electrode of the first MOS tube is connected with a power supply, and the second electrode of the first MOS tube is connected with a common node;
the control electrode of the second MOS tube is used for inputting a second control signal, the first electrode of the second MOS tube is connected with the common node, and the second electrode of the second MOS tube is connected with the first electrode of the third MOS tube;
the control electrode of the third MOS tube is used for inputting a third control signal, and the second electrode of the third MOS tube is used for connecting the storage array;
one polar plate of the storage capacitor is connected with the common node, and the other polar plate is grounded;
the input end of the latch is connected with the common node, and the output end of the latch is used for outputting the amplified storage data.
5. The data processing circuit of claim 3, further comprising: a logic controller;
in a test mode, the logic controller is configured to execute a test instruction to control a first input end of the two-way gate to be connected to an output end of the two-way gate, and control the parallel-serial conversion circuit and the port driving module to be turned on, so that test data output by the graphics generator sequentially passes through the two-way gate, the parallel-serial conversion circuit and the port driving module, and then outputs the first result;
in the data reading mode, the logic controller is further configured to execute a data reading instruction to control a second input end of the two-way gate to be connected to an output end of the two-way gate, and control the parallel-serial conversion circuit and the port driving module to be turned on, so that the stored data sequentially passes through the two-way gate, the parallel-serial conversion circuit and the port driving module, and then the second result is output.
6. The data processing circuit of claim 1, wherein the data pattern generator comprises: the system comprises a random data generator, a protocol data generator, an extreme value data generator and a three-way gate;
the random data generator is connected with a first input end of the three-way gate and is used for outputting random data;
the second input end of the three-way gate of the protocol data generator is connected, and the protocol data generator is used for outputting data following a communication protocol;
the extreme value data generator is connected with a third input end of the three-way gate and is used for outputting limit value data;
the three-way gate is used for selecting data input by one input end of the three-way gate to be used as the test data and outputting the test data through an output end of the three-way gate.
7. The data processing circuit of claim 1, wherein the port driver module comprises: the device comprises a trigger D, a control circuit, a pull-up MOS tube, a pull-down MOS tube and a load capacitor;
a first electrode of the pull-up MOS tube is connected with a power supply, and a second electrode of the pull-up MOS tube is connected with the output end of the port driving module; a first electrode of the pull-down MOS tube is connected with the output end of the port driving module; the control electrodes of the pull-up MOS tube and the pull-down MOS tube are respectively connected with one output end of the control circuit; the output end of the port driving module is grounded through the load capacitor;
one input end of the D trigger is used for inputting an enabling signal, the other input end of the D trigger is connected with the output end of the parallel-serial conversion circuit, and the output end of the D trigger is connected with the input end of the control circuit;
and the control circuit controls the conduction of the pull-up MOS tube and the pull-down MOS tube based on the output signal of the D trigger so as to control the output result of the output end of the port driving module.
8. A memory chip, comprising:
a data processing circuit as claimed in any one of claims 1 to 7.
9. A data processing method of a memory chip, comprising:
obtaining measurements of the memory chip with a data processing circuit according to any of claims 1-7 to determine a power consumption parameter.
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