CN110795899B - Chip power-on control device - Google Patents
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Abstract
The invention provides a chip power-on control device, which comprises a power-off PSO chain, wherein the PSO chain comprises a plurality of PSO sub-chains distributed according to the power-on sequence, each PSO sub-chain in the plurality of PSO sub-chains is provided with an adjustable delay circuit corresponding to the PSO sub-chain, and a delay signal output end of the adjustable delay circuit is connected with an input end of a first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit; the delay signal input end of the adjustable delay circuit corresponding to the first PSO subchain in the PSO subchains is connected with the power-on control signal output port of the PSO subchain, and the delay signal input end of the adjustable delay circuit corresponding to each other PSO subchain except the first PSO subchain in the PSO subchains is connected with the output end of the last PSO unit of the previous PSO subchain of the other PSO subchains. The invention can reduce the use of the always-on unit in the turn-off module, reduce the design area and wiring resource expenditure of the turn-off module, further reduce the iteration times of the low-power design and accelerate the convergence of the low-power design.
Description
Technical Field
The invention relates to the technical field of low-power consumption design of integrated circuits, in particular to a chip power-on control device.
Background
The Power Shutdown (PSO) technology is a low-power design technology commonly used in the field of integrated circuit design, and can realize fine-granularity power consumption control, and the power supply of a module circuit in an idle state in a chip is turned off, so that the electric leakage and dynamic power consumption in the chip are reduced, and the basic structure of the circuit is shown in fig. 1: in this configuration, the operating power supply of the logic function transistor is from a large PMOS transistor connected to a power supply, and the gate of the PMOS transistor is controlled by an enable control signal. When the enabling signal is turned on, current flows through the PMOS tube from the power supply to be supplied to the logic circuit; when the enable signal is turned off, the power supply of the logic function circuit is cut off, and the logic circuit stops working.
In a module design implementation of a low power design, a large number of PSO cells are typically uniformly spread, and the gate terminals of the PSO cells are connected in series to form a power-on control chain, i.e., a PSO chain, as shown in fig. 2. Before the circuit works normally, the power-on control module of the chip transmits an instruction, the instruction is transmitted to the Npwr_in, the enabling end of the PSO is controlled to be opened according to a given organization sequence, and the power-on process is completed within a limited time. The response signal Npwr_out after the power-on is finished is fed back to the control module, and the control module dispatches the functional circuit to work normally.
The power-on process is a process that PMOS tubes on the PSO enabled control link are opened one by one. In the initial stage of power-on, the power-on module has larger requirement on electric quantity, and a large amount of current flows into the power-on module in a short time along with the rapid opening of the PMOS tubes on the control link one by one, so that a surge current with higher peak value exists, and at the moment, the change rate of the current in unit time is larger, so that stronger inductance is caused, the fluctuation of the working voltage of the chip is caused, and the work of the chip is unstable; in addition, a large amount of current flows into the power-on module, so that the circuit voltage of the normal working modules around the power-on module can be lowered, and the normal working of the chip is influenced, even the chip is in error.
The current approach to this problem is to insert an appropriate amount of delay cells in the link, which slows down the power-up process. After the delay unit is inserted, the PMOS of the PSO chain is opened slowly, the current which can flow into the power-on module in unit time is limited, the current change rate is reduced, and the adverse effect of quick power-on is weakened.
In low power designs, the PSO cells on the PSO chain need to operate within the keep-alive (always-on) voltage threshold, so delay cells must be inserted on the PSO links within the turn-off modules, and cells of the always-on nature must be used. Such a unit has two sets of power and ground, which attribute can lead to an increase in the design area of the turn-off module; in addition, the need for a set of power and ground lines connected to the power plane of the analysis-on in the form of signal lines increases the overhead of the design routing resources, and in high speed and high density designs, these problems manifest themselves as anomalies that can seriously impact the convergence of low power designs.
Disclosure of Invention
The invention provides a chip power-on control device, which aims to solve the problems that an always-on attribute unit inside a turn-off module occupies a large area, wiring resource cost is high, and convergence of low-power consumption design is affected.
In order to achieve the above objective, an embodiment of the present invention provides a chip power-on control device, including a power-off PSO chain, where the PSO chain includes a plurality of PSO sub-chains distributed according to a power-on sequence, each of the plurality of PSO sub-chains is provided with an adjustable delay circuit corresponding to the PSO sub-chain, a delay signal output end of the adjustable delay circuit is connected to an input end of a first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit, and a delay control signal input end of the adjustable delay circuit is connected to a delay control signal output port;
the delay signal input end of the adjustable delay circuit corresponding to the first PSO sub-chain in the plurality of PSO sub-chains is connected with the power-on control signal output port of the PSO chain, the delay signal input end of the adjustable delay circuit corresponding to each other PSO sub-chain except the first PSO sub-chain in the plurality of PSO sub-chains is connected with the output end of the last PSO unit of the previous PSO sub-chain in the other PSO sub-chains, and the output end of the last PSO unit of the last PSO sub-chain in the plurality of PSO sub-chains is connected with the power-on completion signal output port.
Wherein the adjustable delay circuit comprises: a first decoder, a first delay circuit, a second decoder, and a second delay circuit;
the address input signal end of the first decoder and the address input signal end of the second decoder are both connected with the delay control signal output port, the output end of the first decoder is connected with the enabling signal input end of the first delay circuit, the output end of the second decoder is connected with the enabling signal input end of the second delay circuit, the delay signal input end of the second delay circuit is the delay signal input end of the adjustable delay circuit, the delay signal output end of the second delay circuit is connected with the delay signal input end of the first delay circuit, and the delay signal output end of the first delay circuit is the delay signal output end of the adjustable delay circuit;
the minimum delay output by the delay signal output end of the first delay circuit is equal to the maximum delay output by the delay signal output end of the second delay circuit.
Wherein the first decoder and the second decoder are both 3-input decoders.
The delay control signal output port is an output port of a register.
The scheme of the invention has at least the following beneficial effects:
in the embodiment of the invention, the PSO chains are divided into a plurality of independent PSO sub-chains distributed according to the power-on sequence, and an adjustable delay circuit with configurable delay is arranged for each PSO sub-chain, so that the output delay on each PSO sub-chain can be configured according to the actual power-on requirement, and meanwhile, the delay signal input end of the adjustable delay circuit corresponding to the first PSO sub-chain in the plurality of PSO sub-chains is connected with the power-on control signal output port of the PSO chain, the delay signal input end of the adjustable delay circuit corresponding to each other PSO sub-chain except the first PSO sub-chain is connected with the output end of the last PSO unit of the last PSO sub-chain of the other PSO sub-chain, the output end of the last PSO unit is connected with the power-on completion signal output port, all PSO sub-chains are connected into a complete link, so that the power consumption of a power-off module can be reduced by setting the input end of the first PSO unit of each PSO sub-chain and the output end of the last PSO unit of the PSO sub-chain into a complete link, the power-off module can be designed to the power-off module, the number of the power-off module can be reduced, the power consumption of the power-off module can be designed to be reduced, and the power consumption of the power-off module can be reduced, and the power consumption of the power consumption module can be reduced, and the power consumption can be reduced. In addition, in the silicon after-debugging, if the power-on time is too fast, the value of the delay control signal input end of the adjustable delay circuit can be changed in a software debugging mode, so that more reasonable power-on time configuration is obtained. With the increase of the working time of the chip after silicon, when a power supply battery is aged gradually, the internal resistance of the battery is increased gradually, and the power supply current is attenuated gradually, so that when the power-on time is deviated, the configuration of software can be adjusted in a mode of combining software and hardware, and more reasonable power-on control chain delay is obtained on the hardware, so that the power-on of the chip is more reasonable.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of power consumption control based on PSO technology;
FIG. 2 is an organizational chart of a PSO chain in the prior art;
FIG. 3 is a schematic diagram of a chip power-on control device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an adjustable delay circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a delay circuit according to an embodiment of the present invention.
[ reference numerals description ]
31. An adjustable delay circuit; 32. a power-on control signal output port; 33. a power-on completion signal output port; 41. a first decoder; 42. a first delay circuit; 43. a second decoder; 44. a second delay circuit; 45. an address input signal terminal; 46. a delay signal input; 47 delay signal output.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
As shown in fig. 3, an embodiment of the present invention provides a chip power-on control device, including a power-off PSO chain, where the PSO chain includes a plurality of PSO sub-chains distributed according to a power-on sequence, each of the plurality of PSO sub-chains is provided with an adjustable delay circuit 31 corresponding to the PSO sub-chain, a delay signal output end of the adjustable delay circuit 31 is connected to an input end of a first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit 31, and a delay control signal input end of the adjustable delay circuit 31 is connected to a delay control signal output port.
The delay signal input end of the adjustable delay circuit 31 corresponding to the first PSO sub-chain of the plurality of PSO sub-chains is connected to the power-on control signal output port 32 of the PSO chain, the delay signal input end of the adjustable delay circuit 31 corresponding to each other PSO sub-chain of the plurality of PSO sub-chains except the first PSO sub-chain is connected to the output end of the last PSO unit of the previous PSO sub-chain of the other PSO sub-chains, and the output end of the last PSO unit of the last PSO sub-chain of the plurality of PSO sub-chains is connected to the power-on completion signal output port 33.
It should be noted that, since the plurality of PSO subchains are ordered according to the power-on sequence, the previous PSO subchain of the other PSO subchain refers to the PSO subchain that is arranged in front of the other PSO subchain. As in fig. 3, the first PSO child chain is the previous PSO child chain of intermediate PSO child chain 1, intermediate PSO child chain 1 is the previous PSO child chain of intermediate PSO child chain 2, wherein intermediate PSO child chain 1 and intermediate PSO child chain 2 in fig. 3 are the PSO child chains between the first PSO child chain and the last PSO child chain. It will be appreciated that a plurality of PSO sub-chains are connected in series in a complete chain through a corresponding plurality of adjustable delay circuits 31.
In the embodiment of the present invention, the number of PSO units included in the multiple PSO sub-chains may be different. Preferably, the PSO units included in the first PSO subchain of the plurality of PSO subchains are suitably smaller, so that the number of PSO units opened in the early stage of power-up is conveniently controlled.
In the embodiment of the present invention, in order to reduce the number of always-on units in the turn-off module, the input end of the first PSO unit and the output end of the last PSO unit of each PSO sub-chain are led out to the boundary of the turn-off module, and the adjustable delay circuit 31 corresponding to each PSO sub-chain is located in the non-turn-off area outside the turn-off module, so that the number of always-on units in the turn-off module is reduced, and accordingly, the design area and routing resource overhead of the turn-off module are also reduced, thereby reducing the iteration number of the low power design and accelerating the convergence of the low power design.
It should be noted that the structures of the adjustable delay circuits corresponding to the PSO sub-chains are the same, and in the embodiment of the present invention, the delay time of the output of the adjustable delay circuit may be configured according to the needs, so that the delay time of each PSO sub-chain may be configured according to the needs. The delay time of the output of the adjustable delay circuit is specifically determined by the delay control signal received by the delay control signal input end of the adjustable delay circuit. It should be noted that the delay control signal is output from a delay control signal output port. As a preferred example, the delay control signal output port may be an output port of a register.
In the embodiment of the invention, the power-on current waveform of the whole PSO chain can be obtained through a simulation tool in the early design stage, and the surge current is reduced by adjusting the delay time between two adjacent PSO sub-chains, so that a better power-on current waveform is obtained, thereby providing a reference for setting the actual delay of the adjustable delay circuit. After all PSO subchains are connected by the adjustable delay circuit, the power consumption of the design changes along with the deep design, and if the best power-on current waveform is to be achieved, the configuration of the relevant register is only required to be adjusted, so that the iteration of the design is avoided.
As is well known, in a power supply system of a chip, as working time passes, a power supply battery gradually ages, internal resistance of the battery gradually increases, and power supply current gradually decays, so that power-on time of a power-on module of the chip changes. If the designed power-on system is not adjustable, the reliability of the chip operation gradually decreases as the power supply system ages. With respect to the problem, after the chip adopts the chip power-on control device provided by the embodiment of the invention, when the chip suffers from the problem of aging of a power supply during operation, the chip can work in a more perfect state by adjusting the configuration of the delay time of the adjustable delay circuit.
In an embodiment of the present invention, as shown in fig. 4, the adjustable delay circuit includes: a first decoder 41, a first delay circuit 42, a second decoder 43, and a second delay circuit 44.
The address input signal terminal 45 of the first decoder 41 and the address input signal terminal 45 of the second decoder 43 are both connected to the delay control signal output port, the output terminal of the first decoder 41 (the output terminal is used for outputting the enable signal generated by the first decoder) is connected to the enable signal input terminal of the first delay circuit 42, the output terminal of the second decoder 43 (the output terminal is used for outputting the enable signal generated by the second decoder) is connected to the enable signal input terminal of the second delay circuit 44, the delay signal input terminal 46 of the second delay circuit 44 is the delay signal input terminal of the adjustable delay circuit, the delay signal output terminal of the second delay circuit 44 (the delay signal output terminal is used for outputting the delay signal generated by the second delay circuit) is connected to the delay signal input terminal of the first delay circuit 42, and the delay signal output terminal 47 of the first delay circuit 42 (the delay signal output terminal is used for outputting the delay signal generated by the first delay circuit) is the adjustable delay signal input terminal.
Wherein the minimum delay output by the delay signal output terminal of the first delay circuit 42 is equal to the maximum delay output by the delay signal output terminal of the second delay circuit 44.
The number of delay stages of the first delay circuit 42 is determined by the number of inputs of the first decoder 42, and the number of delay stages of the second delay circuit 44 is determined by the number of inputs of the second decoder 43. As a preferred example, the first decoder 41 and the second decoder 43 are both 3-input decoders, and the first decoder 41 may control the first delay circuit 42 to generate 8-stage adjustable delay, and the second decoder 43 may control the second delay circuit 44 to generate 8-stage adjustable delay. The minimum gear delay output by the first delay circuit 42 corresponds to the maximum gear delay output by the second delay circuit 44 (i.e., the minimum gear delay output by the first delay circuit 42 is slightly greater than or equal to the maximum gear delay output by the second delay circuit 44), and each gear delay of the second delay circuit 44 corresponds to one eighth of the minimum gear delay of the first delay circuit 42.
It should be noted that, the specific structures of the first delay circuit 42 and the second delay circuit 44 may be implemented by using existing delay circuits, and the basic structures are identical, and the difference is the magnitude of the delay buffer chain in the gear, and the specific structure of the delay circuits is shown in fig. 5. The circuit structure of each gear is shown in the dashed block diagram in fig. 5, in which Dly _in is an input delay signal (i.e. a signal received at the delay signal input end of the delay circuit), en [0:m ] is an enable signal generated by decoding, m is the input number of the decoder, dly _out is a delay signal output by the delay circuit, and buf_chain is a buffer chain formed by delay buffers inserted according to design requirements. It should be further noted that, during the actual use, the register connected with the adjustable delay circuit can be configured to complete the adjustment of the enabling signal generated by decoding, thereby completing the delay gear selection of the adjustable delay circuit.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (4)
1. The power-on control device for the chip comprises a power-off PSO chain, and is characterized in that the PSO chain comprises a plurality of PSO sub-chains distributed according to the power-on sequence, each PSO sub-chain in the plurality of PSO sub-chains is provided with an adjustable delay circuit corresponding to the PSO sub-chain, the delay signal output end of the adjustable delay circuit is connected with the input end of the first PSO unit of the PSO sub-chain corresponding to the adjustable delay circuit, and the delay control signal input end of the adjustable delay circuit is connected with a delay control signal output port;
the delay signal input end of the adjustable delay circuit corresponding to the first PSO subchain in the plurality of PSO subchains is connected with the power-on control signal output port of the PSO chain, the delay signal input end of the adjustable delay circuit corresponding to each other PSO subchain except the first PSO subchain in the plurality of PSO subchains is connected with the output end of the last PSO unit of the previous PSO subchain in the other PSO subchain, and the output end of the last PSO unit of the last PSO subchain in the plurality of PSO subchains is connected with the power-on completion signal output port; the input end of the first PSO unit and the output end of the last PSO unit of each PSO sub-chain are led out to the boundary of the turn-off module, and the adjustable delay circuit corresponding to each PSO sub-chain is positioned in a non-turn-off area outside the turn-off module.
2. The on-chip control device of claim 1, wherein the adjustable delay circuit comprises: a first decoder, a first delay circuit, a second decoder, and a second delay circuit;
the address input signal end of the first decoder and the address input signal end of the second decoder are both connected with the delay control signal output port, the output end of the first decoder is connected with the enabling signal input end of the first delay circuit, the output end of the second decoder is connected with the enabling signal input end of the second delay circuit, the delay signal input end of the second delay circuit is the delay signal input end of the adjustable delay circuit, the delay signal output end of the second delay circuit is connected with the delay signal input end of the first delay circuit, and the delay signal output end of the first delay circuit is the delay signal output end of the adjustable delay circuit;
the minimum delay output by the delay signal output end of the first delay circuit is equal to the maximum delay output by the delay signal output end of the second delay circuit.
3. The on-chip control device of claim 2, wherein the first decoder and the second decoder are both 3-input decoders.
4. The power-on-chip control device according to claim 1, wherein the delay control signal output port is an output port of a register.
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| CN114650042A (en) * | 2020-12-21 | 2022-06-21 | Oppo广东移动通信有限公司 | Power-on control device and configuration method thereof, chip and electronic equipment |
| CN113935273A (en) * | 2021-09-17 | 2022-01-14 | 东科半导体(安徽)股份有限公司 | Control signal connection method of low-power-consumption module |
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| JP2015076711A (en) * | 2013-10-08 | 2015-04-20 | マイクロン テクノロジー， インク． | Semiconductor device |
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| CN102171763A (en) * | 2008-10-02 | 2011-08-31 | 国际商业机器公司 | Optimizing sram performance over extended voltage or process range using self-timed calibration of local clock generator |
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