CN110794376A - Ultra-wideband impulse radar receiver sensitivity measuring technology - Google Patents
Ultra-wideband impulse radar receiver sensitivity measuring technology Download PDFInfo
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- CN110794376A CN110794376A CN201911290986.XA CN201911290986A CN110794376A CN 110794376 A CN110794376 A CN 110794376A CN 201911290986 A CN201911290986 A CN 201911290986A CN 110794376 A CN110794376 A CN 110794376A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4004—Means for monitoring or calibrating of parts of a radar system
- G01S7/4021—Means for monitoring or calibrating of parts of a radar system of receivers
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Abstract
The invention discloses a technology for measuring the sensitivity of an ultra-wideband impulse radar receiver, which can be used in the fields of ultra-wideband radars, ultra-wideband radio detectors, ultra-wideband communication and the like. The measurement technology comprises a central control unit, a time sequence forming circuit, a transmitting trigger pulse forming circuit, an ultra-wideband signal generating circuit, band-limited filtering, numerical control attenuation, program control delay, AD acquisition, a high-stability clock and a delay circuit. The central control unit generates a measurement time sequence and provides a high-precision program-controlled delay sampling pulse and an ultra-wideband input excitation signal for the receiver. The central control unit controls the signal amplitude through numerical control attenuation, controls time domain waveform and spectrum distribution by using band-limited filtering, assists in controlling excitation time sequence by a delay circuit, and finishes the judgment of critical conditions and the automatic output of measurement results through AD acquisition and digital processing technologies. The invention solves the problem of sensitivity measurement of the ultra-wideband sampling integral receiver, and has the advantages of small volume, low cost and convenient popularization and application.
Description
Technical Field
The invention relates to the field of pulse system radar performance measurement, in particular to a technology and a device for measuring the sensitivity of an ultra-wideband impulse radar receiver. The radar sensitivity measurement technology can realize sensitivity measurement of nanosecond or even picosecond impulse narrow-pulse radar, and provides a low-cost, portable, reliable and universal sensitivity measurement method for ultra-wideband radar, ultra-wideband radio detector, ultra-wideband communication equipment and the like without using expensive large-bandwidth Gaussian pulse signal sources and high-speed oscilloscopes.
Background of the invention
Sensitivity represents the ability of the receiver to receive weak signals. The weaker the signal that can be received, the higher the sensitivity of the receiver and thus the longer the range of the radar. Sensitivity of radar receivers is typically measured by the minimum detectable signal power SiminIs defined as:
Simin＝kT0BnF0(S0/N0) (1)
currently, two methods are commonly used for measuring signal sensitivity: implantation and irradiation. For ultra-wideband impulse radar, echo signals are extremely narrow pulses of nanosecond or even picosecond magnitude, the existing microwave signal source cannot generate the signals of the type, the cost of customizing and developing the signal source is extremely high, and the control on power, frequency spectrum, time domain waveform and delay cannot be achieved. The step scanning sampling pulse required by the sensitivity measurement of the ultra-wideband receiver can not be generated by general equipment, and the customized development also needs higher cost and longer period. Therefore, no ready equipment is available at present for the sensitivity test of the receiver of the ultra-wideband impulse system radar, a non-systematic method can be used for reference, the sensitivity test method and the equipment for the system radar can be designed and developed to fill the blank of the current market, and the method has important practical significance and application and popularization value.
Disclosure of Invention
The invention provides a receiver sensitivity measuring method suitable for an ultra-wideband impulse system radar, aiming at the problem that the existing receiver measuring method cannot measure the receiving sensitivity of the ultra-wideband impulse system radar, and meeting the sensitivity measuring requirements of the ultra-wideband system radar, the ultra-wideband radio detector, the ultra-wideband communication equipment and the like.
In order to realize the functions, the invention adopts the following technical scheme: the method comprises the steps of utilizing a central control unit to generate a measurement time sequence, providing a large-range and high-precision program control delay sampling pulse (excitation 1) in picosecond level for a tested receiver through the cooperation of software delay and hardware delay, providing an input signal (excitation 2) for the tested receiver through an ultra-wideband signal generating circuit, controlling the amplitude of the signal through numerical control attenuation, utilizing band-limited filtering to control time domain waveform and frequency spectrum distribution, and controlling the time sequence of the excitation signal through a delay circuit. The central control unit controls the intermediate frequency output (response signal) of the AD acquisition receiver, continuously controls the numerical control attenuation amount, automatically interprets the signal-to-noise ratio, and gives the sensitivity measurement result of the receiver when the critical condition is met. The whole receiver sensitivity measuring system comprises a central control unit, a time sequence forming circuit, a transmitting trigger pulse forming circuit, an ultra-wideband signal generating circuit, band-limited filtering, numerical control attenuation, program-controlled delay, AD acquisition, a high-stability clock, a delay circuit and the like.
In order to ensure the sensitivity measurement precision, the ultra-wideband impulse system receiving sensitivity measurement equipment automatically adjusts the signal power fed into the receiver, automatically controls the delay scanning of sampling pulses, automatically acquires the intermediate frequency output amplitude and the noise amplitude of the receiver, automatically records the signal-to-noise ratio of different attenuation values and automatically gives the sensitivity measurement value S of the receiver through an automatic test programimin。
In order to realize the sensitivity measurement of a receiver, an AD + FPGA-based high-performance intermediate frequency signal measurement circuit is designed, the circuit collects intermediate frequency signals by using a low-cost and 14-bit large dynamic range analog-to-digital converter (AD), measures the signal-to-noise ratio of the intermediate frequency signals in the FPGA by using digital processing technologies such as sliding window detection, Constant False Alarm Rate (CFAR) threshold detection, digital filtering, mean value denoising, numerical calculation and the like, judges the proximity condition and accurately calculates the sensitivity S of the receiverimin。
The invention solves the sensitivity measurement problem of the ultra-wideband impulse system receiver for the first time, is particularly suitable for the ultra-wideband receiver of a sampling integral system, and has compact integral structure and small volume; the problem of sensitivity measurement of ultra-wideband impulse system receiving with great difficulty is solved through low-cost devices and circuits, the cost is low, and the ultra-wideband impulse system receiving sensitivity measuring circuit is suitable for common users and convenient to popularize and apply.
Drawings
The drawings of the invention are illustrated as follows:
FIG. 1 is a block diagram of the ultra-wideband impulse radar receiver sensitivity measurement of the present invention;
figure 2 is a schematic diagram of an ultra-wideband signal generating circuit of the present invention;
FIG. 3 is a circuit diagram of the step sampling pulse generation circuit of the present invention.
Detailed Description
The structure of the invention is shown in figure 1, which specifically comprises: (1) the device comprises a central control unit, (2) a time sequence forming circuit, (3) a transmitting trigger pulse forming circuit, (4) an ultra-wideband signal generating circuit, (5) band-limited filtering, (6) numerical control attenuation, (7) program control delay, (8) AD acquisition, (9) a high-stability clock and (10) a delay circuit.
A high-stability clock (9) generates a time reference signal and sends the time reference signal to a central control unit (1), and the central control unit (1) generates a time sequence pulse of a measuring circuit according to the time reference and sends the time sequence pulse to a time sequence forming circuit (2); the time sequence forming circuit (2) shapes and drives the time sequence pulse and distributes the time sequence pulse to the emission trigger pulse forming circuit (3) and the program control delay (7) for use; the transmitting trigger pulse forming circuit differentiates, compares thresholds and gates the transmitting time sequence signal, and then sends the signal to the ultra-wideband signal generating circuit (4) and generates an ultra-wideband impulse pulse signal, the ultra-wideband impulse pulse signal is sent to the band-limited filter (5) to filter out the required transmitting energy, and the signal is fed into the ultra-wideband sampling integral receiver to be tested through the delay circuit (10) and the numerical control attenuation (6); meanwhile, a receiving time sequence signal generated by the time sequence forming circuit (2) is sent to the ultra-wideband sampling integral receiver to be detected through the program control delay (7); the ultra-wideband sampling integral receiver to be tested outputs an intermediate frequency signal and sends the intermediate frequency signal to an AD acquisition unit (8), a digital sampling signal is sent to a central control unit (1), and the sensitivity of the ultra-wideband receiver to be tested is obtained after digital processing judgment by controlling the attenuation value of numerical control attenuation (6).
The specific implementation method comprises the following steps:
in testing the sensitivity of an ultra-wideband receiver, a scanning (or sliding) sampling pulse and an ultra-wideband excitation signal with controllable power need to be provided. The test equipment of the invention utilizes the ultra-wideband signal generating circuit (4) to generate ultra-wideband impulse pulse signals, controls the amplitude of the ultra-wideband impulse pulse signals through numerical control attenuation (6), changes the delay of sampling pulses through program control delay (7), ensures the normal work of a tested receiver, and completes the measurement function of sensitivity indexes by collecting the signal-to-noise ratio of the output end of the tested receiver.
The circuit principle of the ultra-wideband signal generating circuit (4) is shown in fig. 2. Triggered by the output pulse of the firing pulse forming circuit (3), the avalanche supply voltage VCC is applied to the collector of the avalanche transistor T1 via a resistor R2, which is slightly less than VCBOBut greater than VCEO. Before the trigger signal arrives, the avalanche power supply charges a capacitor C1 through resistors R2 and R59, and the voltage between the collector and the emitter of the avalanche transistor T1 is close to the voltage VCC of the avalanche power supply. Under the action of the high voltage, the collector of the avalanche transistor is reversely biased, but the collector current icSmaller, base current ib< 0, current i of emittere(> 0), the avalanche transistor T1 is in a steady state. When a trigger pulse arrives, the voltage between the base electrode and the emitter electrode rises, the emitter junction is conducted, the operating point of the avalanche transistor changes accordingly, the current in the collector junction is increased rapidly under the action of an avalanche effect, the avalanche transistor breaks down, and at the moment, the capacitor C1 discharges rapidly through the avalanche transistor, and a large instantaneous current is formed on the load R59. The pulse formed at this time is a negative pulse since the direction of the current is from the collector to the emitter. When the capacitor C1 discharges to a certain extent, the instantaneous current becomes small, the avalanche transistor returns to the off state, and the avalanche power supply charges the C1 again to wait for the arrival of the next trigger pulse.
The band-limiting filtering (5) is realized by a hairpin-finger type micro-strip filter, a band-pass filter with proper bandwidth is designed according to the working bandwidth of the tested receiver, and the time domain waveform and the frequency spectrum distribution of the test signal fed into the receiver are controlled.
The numerical control attenuation (6) is realized by an ultra-wideband and high-precision numerical control chip, the bandwidth coverage of the numerical control attenuation (6) reaches 12GHz, the insertion loss is less than 1dB, the attenuation step is 0.5dB, the attenuation range is 0-60 dB, and the coaxial fixed attenuators (10dB, 20dB, 30dB and 60dB) are used for assisting, so that the power control and adjustment in a larger range can be realized, and the test requirement of a high-sensitivity receiver is ensured.
The delay circuit (10) is used to control the time delay, i.e. the excitation timing, of the measurement signal fed into the receiver and is formed by a low-loss coaxial cable of adjustable length or implemented using a fixed delay chip. The invention adopts a low-loss phase-stable coaxial cable and calculates the delay time tau and the cable length l according to a formula (2).
τ＝l·c/√εe(2)
Wherein √ εeIs the equivalent dielectric constant of the coaxial cable; l is the length of the coaxial cable; c is 3X 108And m/s is the electromagnetic wave propagation speed. The delay line has a large bandwidth (tens of GHz even tens of GHz), a flat amplitude-frequency characteristic and a linear delay frequency characteristic, and low distortion of an ultra-wideband time domain waveform is guaranteed.
The program control delay (7) is realized by comprehensively adopting a method of software delay and hardware delay. The software delay usually uses a high-speed clock as a counting unit, realizes large-range delay through a logic time sequence, and has large control range and flexible control. The hardware delay adopts a counter delay, and the circuit consists of a fast ramp generator, a step wave generator, a voltage comparator and a pulse shaping circuit, as shown in figure 3. Receiving a fast ramp generator in a time sequence pulse trigger stepping delay circuit to generate a fast ramp voltage signal which has the same frequency as a trigger pulse, short delay time and good linearity; the step wave generator converts the analog signal into a step wave signal with digital property through a DA converter; the fast ramp signal and the step signal are compared by the voltage comparator, and when the fast ramp meets a step level, a signal is generated and is output as a step pulse through the shaping circuit. When the next trigger signal comes, the newly generated fast ramp wave is compared with the new step wave again, and a pulse delayed by delta t relative to the previous step pulse is output, so that a continuous step sampling pulse signal is generated.
The central control unit is a main controller of a sensitivity measuring circuit of the ultra-wideband receiver, and realizes the following functions:
1. generating a working time sequence pulse of the test equipment, controlling the ultra-wideband signal generating circuit (4) to output a test signal, and exciting a tested receiver;
2. controlling the delay amount of the program control delay (7) to enable the receiving sampling pulse to generate ps-level stepping delay and ensure that the tested receiver finishes sampling integration processing;
3. controlling the attenuation value of the numerical control attenuation (6) and adjusting the signal power fed into the tested receiver;
4. the signal acquired (8) by AD is processed and the noise level and the level of the intermediate frequency signal are determined by sliding window detection. When the signal-to-noise ratio SNRout is 1 (critical condition), the sensitivity of the ultra-wideband receiver is obtained according to the attenuation value at (db) of the numerical control attenuation (6) and the power value pt (dbm) of the ultra-wideband signal when the ultra-wideband signal is not attenuated: simin ═ pt (dbm) -at (db).
The central control unit is based on a high-performance FPGA, the time sequence control is flexible, the processing capacity is strong, and the internal storage space meets the capacity requirement of the system in data storage and processing.
Claims (6)
1. The ultra-wideband impulse radar receiver sensitivity measurement technology is characterized in that: the method can realize the measurement of the sensitivity of the ultra-wideband sampling integral receiver by generating a time sequence controlled high-precision step scanning sampling pulse and an ultra-wideband impulse narrow pulse, and specifically comprises (1) a central control unit, (2) a time sequence forming circuit, (3) a transmitting trigger pulse forming circuit, (4) an ultra-wideband signal generating circuit, (5) band-limited filtering, (6) numerical control attenuation, (7) program control delay, (8) AD acquisition, (9) a high-stability clock and (10) a delay circuit.
2. The ultra-wideband impulse radar receiver sensitivity measurement technique of claim 1, characterized in that: an ultra-wideband signal generating circuit (4) is realized by utilizing an avalanche transistor design, frequency spectrum and time domain waveform control is realized by utilizing band-limited filtering (5), power control is realized by utilizing numerical control attenuation (6), excitation time sequence control is realized by utilizing a delay circuit (10), and an ultra-wideband impulse excitation signal required by receiver sensitivity measurement is generated.
3. The ultra-wideband impulse radar receiver sensitivity measurement technique of claim 1, characterized in that: the central control unit (1) generates sampling pulses required by the sensitivity measurement of the receiver by adopting a method of combining software delay and hardware delay, and the method not only ensures the scanning range of the received sampling pulses, but also ensures the stepping precision of the received sampling pulses.
4. The ultra-wideband impulse radar receiver sensitivity measurement technique of claim 1, characterized in that: the method adopts the technologies of high-precision AD (analog-digital converter) acquisition, CFAR (constant frequency analog-digital converter) detection, sliding window detection, digital filtering and the like.
5. The ultra-wideband impulse radar receiver sensitivity measurement technique of claim 1, characterized in that: by measuring the amplitude and the noise amplitude of the intermediate frequency output signal of the receiver to be measured, the numerical control attenuation quantity is manually or automatically controlled, and whether the output signal-to-noise ratio reaches a critical condition is judged, so that the sensitivity measurement result of the receiver is obtained.
6. The ultra-wideband impulse radar receiver sensitivity measurement technique of claim 1, characterized in that: and a digital processor based on FPGA, a singlechip, an embedded processor and the like can be used as the processor, so that the digitization and the automation of the measuring system are ensured.
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| CN113126049A (en) * | 2021-06-17 | 2021-07-16 | 北京宏动科技有限公司 | Sensitivity measuring equipment and method applied to ultra-wideband sampling receiver |
| CN115361074A (en) * | 2022-08-18 | 2022-11-18 | 北京宏动科技股份有限公司 | Carrier-free ultra-wideband time control array technology verification system |
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