CN110783461A - Transistor and method of manufacturing the same - Google Patents
Transistor and method of manufacturing the same Download PDFInfo
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- CN110783461A CN110783461A CN201910879619.7A CN201910879619A CN110783461A CN 110783461 A CN110783461 A CN 110783461A CN 201910879619 A CN201910879619 A CN 201910879619A CN 110783461 A CN110783461 A CN 110783461A
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/80—Constructional details
- H10K10/82—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
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- H—ELECTRICITY
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- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
Abstract
The application discloses a transistor and a manufacturing method thereof, which mainly comprises the following steps: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotube; forming a side wall covering the gate stack structure; forming a sacrificial layer at least covering the side wall; forming a metal layer covering the carbon nano tube and the sacrificial layer, wherein part of the metal layer positioned in the source drain region is used as an electric contact contacted with the carbon nano tube; removing a portion of the metal layer to expose the sacrificial layer; and removing the sacrificial layer to expose the side wall. In the manufacturing method, when the metal layer is formed, the metal layer directly covers the sacrificial layer and the carbon nano tube, the side wall is prevented from being in direct contact with the metal layer through the isolation of the sacrificial layer, the metal layer covered on the sacrificial layer is separated from a device through the removal of the sacrificial layer, and the source-drain contact structure is formed, so that the source-drain metal can effectively generate good wettability with the carbon nano tube, and low-resistance ohmic contact is realized.
Description
Technical Field
The present disclosure relates to the field of semiconductor integrated circuit device fabrication, and more particularly, to a transistor and a method of fabricating the same.
Background
As semiconductor technology continues to scale down to technology nodes below 3nm, silicon-based integrated circuits are likely to reach the limits of silicon materials and physical quantum mechanics. With the continued development of microelectronics, there is an urgent need to find new materials with more potential and advantages to replace silicon materials, and the limit of moore's law is broken through. The Carbon Nano Tube (CNT) has excellent electrical, thermal and mechanical properties and chemical stability and a unique one-dimensional nano structure, so that the CNT becomes an ideal functional material applied to micro-nano electronic devices. Carbon Nanotubes (CNTs), which have advantages in terms of high speed, low power consumption, etc., are considered to be one of the best channel materials for constructing field effect transistors in the future, compared to conventional silicon-based electronic devices.
One of the biggest difficulties in fabricating carbon nanotube devices compared to the mainstream silicon-based semiconductor technology is how to effectively form source and drain electrodes. For a silicon-based device, source and drain metals can form a silicide material with a silicon substrate through annealing, and the source and drain metals deposited on the surface of the side wall are removed through a subsequent wet cleaning process. For the carbon nano tube device, the source and drain metal is difficult to form good alloy contact with the carbon nano tube, so that the characteristic similar to that of the metal on the side wall is shown. Therefore, the great difficulty is how to remove the metal material deposited on the sidewall surface of the sidewall with high selectivity, and to minimize the influence of parasitic capacitance, which is one of the biggest challenges faced in the manufacturing process of the carbon nanotube device.
In the prior art, a gate stack structure is formed on a carbon nanotube, then a sidewall structure is formed by deposition and etching, and then a corresponding source-drain metal material is deposited on the whole wafer surface. Then, the metal on the surface of the side wall is removed by combining photolithography and proper etching, but the alignment deviation problem is caused because the precision of the photolithography process is not enough, so that the controllable source drain contact region cannot be accurately obtained, that is, the method is a non-self-aligned forming technology, and uncontrollable hidden troubles are brought to a series of subsequent processes. In particular, as the device size is gradually reduced, the alignment deviation is more and more non-negligible compared to the size of the gate line. Therefore, the manufacturing process of the source-drain contact of the carbon nanotube device must be further improved, and the difficulty of removing the metal layer on the side wall is reduced, so that an accurate self-aligned source-drain contact electrode is formed, and good ohmic contact is realized.
Disclosure of Invention
In view of this, the present invention provides a transistor and a method for manufacturing the same, in which a sacrificial layer is used to protect a sidewall, so that the surface of the sidewall is not covered by a metal layer, thereby preventing the sidewall from directly contacting the metal layer.
According to an aspect of the present invention, there is provided a method of manufacturing a transistor, including: forming carbon nanotubes on a substrate; forming a gate stack structure on the carbon nanotube; forming a side wall covering the side wall of the gate stack structure; forming a sacrificial layer at least covering the side wall; forming a metal layer covering the carbon nano tube and the sacrificial layer, wherein part of the metal layer positioned in the source drain region is used as an electric contact contacted with the carbon nano tube; removing a part of the metal layer by adopting a wet etching process or a dry etching process to expose the sacrificial layer; and removing the sacrificial layer by adopting a wet etching process or a dry etching process to expose the side wall, wherein when the sacrificial layer is removed by adopting the wet etching process or the dry etching process, the sacrificial layer has a preset selection ratio compared with the carbon nano tube, the gate stack structure, the side wall and the electric contact.
Preferably, the step of removing the sacrificial layer comprises: and dissolving the sacrificial layer by using a solution, wherein the metal layer covering the sacrificial layer enters the solution.
Preferably, the solution dissolves the sacrificial layer at a rate greater than the metal layer.
Preferably, the rate of dissolving the sacrificial layer by the solution is greater than the rate of dissolving the side wall and the gate stack structure.
Preferably, the step of removing the metal layer includes etching or corroding the metal layer and stopping on the surface of the sacrificial layer.
Preferably, the thickness of the metal layer covering the carbon nanotubes is greater than the thickness of the metal layer at least partially covering the sacrificial layer, and the reaction parameters are controlled such that etching or corrosion is stopped when the sacrificial layer is exposed.
Preferably, the method further includes forming a mask layer on the gate stack structure, wherein the sidewall covers a sidewall of the mask layer, and the sacrificial layer also covers a surface of the mask layer.
Preferably, the sacrificial layer further covers the carbon nanotubes, and before the metal layer is formed, the manufacturing method further includes removing a portion of the sacrificial layer to form at least two pattern regions, where the at least two pattern regions are respectively located on two sides of the gate stack structure, and at least a portion of the carbon nanotubes are exposed through the pattern regions.
Preferably, at least on the surface of the carbon nanotube, the thickness of the sacrificial layer is greater than the thickness of the metal layer.
Preferably, when the material of the sidewall comprises silicon oxide, the material of the sacrificial layer comprises one or a combination of silicon nitride, amorphous silicon, an organic material and a spin-on medium with high fluidity; when the material of the side wall comprises silicon nitride, the material of the sacrificial layer comprises one or a combination of silicon oxide, amorphous silicon, an organic material and a high-fluidity spin-on medium.
Preferably, the predetermined selection ratio is not less than 3: 1.
According to another aspect of the present invention, there is provided a transistor formed by the manufacturing method as described above.
According to the transistor and the manufacturing method thereof provided by the invention, the sacrificial layer covering the side wall is formed, when the metal layer is formed, the metal layer covers the sacrificial layer and the carbon nano tube, and the side wall is prevented from being directly contacted with the metal layer through the isolation of the sacrificial layer. When the sacrificial layer is removed by adopting a wet etching process or a dry etching process, the sacrificial layer has a preset selection ratio compared with other functional layers, and the other functional layers are prevented from being damaged when the sacrificial layer is removed. After the sacrificial layer is removed, the metal layer covered above the sacrificial layer is separated from the device, and the rest metal layer is positioned on the carbon nano tube to form a source-drain contact structure, so that the source-drain metal can effectively generate good wettability with the carbon nano tube, and low-resistance ohmic contact is realized. Compared with the prior art, the transistor manufacturing method provided by the invention can avoid forming a source-drain contact structure by using a non-self-alignment technology, conveniently and efficiently removes redundant metal layers, forms an accurate self-alignment source-drain contact electrode and improves the yield of devices.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
Fig. 1 shows a schematic structural diagram of a transistor according to an embodiment of the present invention.
Fig. 2a to 2f show cross-sectional views of a method of manufacturing a transistor at various stages according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, a semiconductor device obtained after several steps can be described in one drawing.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 1 shows a schematic structural diagram of a carbon nanotube transistor according to an embodiment of the present invention.
As shown in fig. 1, the transistor of the embodiment of the present invention includes: a substrate 101, a carbon nanotube 110, a gate stack structure 120, electrical contacts including a source contact structure 130 and a drain contact structure 140, a mask layer 102, and sidewalls 103.
The carbon nanotubes 110 are located on the substrate 101. The gate stack structure 120 covers a portion of the carbon nanotube 110. The mask layer 102 is located on the surface of the gate stack structure 120. The spacers 103 are located on both sides of the gate stack structure 120 and the mask layer 102. The source contact structure 130 and the drain contact structure 140 cover at least a portion of the carbon nanotube 110, and are respectively located at two sides of the gate stack structure 120 and an outer side of the sidewall 103, and spaced from the gate stack structure 120 by a certain distance.
In some embodiments, the substrate 101 includes an insulating layer on a supporting substrate. The support substrate mainly plays a supporting role, the material can be silicon, sapphire substrate, quartz, glass, alumina and other hard insulating materials, and any substrate capable of bearing carbon nanotube materials, but the substrate has a very flat surface, and the uniformity also meets the requirement. In the present embodiment, a silicon material is used as a substrate, and is not particularly limited. The material of the insulating layer comprises silicon oxide, silicon nitride, and high-temperature resistant flexible insulating materials such as PET, PEN, polyimide and the like. Different insulating layer materials can be selected according to actual product requirements, and in the embodiment, a silicon oxide material is used as the insulating layer, which is not particularly limited. In another embodiment, instead of depositing the semiconductor layer on a flat surface, the substrate 101 can be grooved and then the carbon nanotubes 110 can be deposited in the grooves as the semiconductor layer.
The carbon nanotubes 110 of the semiconductor layer in this embodiment include a carbon nanotube array, a carbon nanotube self-assembled film, a carbon nanotube network array, and/or a carbon nanotube composite film formed by combining any of the above methods. Besides, the semiconductor layer can be strained silicon or germanium, quantum well, group III-V material, two-dimensional material such as graphene, molybdenum disulfide, black phosphorus, and the like.
In the present embodiment, the gate stack structure 120 includes a gate dielectric layer and a gate conductor stacked on the carbon nanotube 110, wherein the gate dielectric layer may be a conventional gate oxide layer such as silicon oxide and silicon oxynitride, or a high-k (high-k) dielectric material such as hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, aluminum oxide, lanthanum oxide, or lanthanum aluminum oxide, and the thickness of the gate dielectric layer is in the range of 1-10 nm. The gate conductor has the following two cases, as required: when the front grid process is adopted, the front grid structure is a composite structure consisting of one or more layers of metal; when the gate-last process is adopted, a dummy gate electrode is needed to be adopted firstly, and the material of the dummy gate electrode is amorphous silicon, polycrystalline silicon and the like. And then after a series of processing steps, removing the metal gate by adopting a dry etching technology or a wet etching technology, and filling materials such as a metal gate and the like to form a final gate metal conductor.
In the present embodiment, when the carbon nanotube transistor is an N-type MOSFET, the material of the source contact structure 130 and the drain contact structure 140 includes metals such as scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, etc., or alloy materials or composite materials thereof; when the carbon nanotube transistor is a P-type MOSFET, the material of the source contact structure 130 and the drain contact structure 140 includes palladium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy material or a composite material thereof.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements on the materials of the gate stack structure 120, the source contact structure 130, and the drain contact structure 140 as needed.
Fig. 2a to 2f show cross-sectional views of a method of manufacturing a transistor at various stages according to an embodiment of the invention.
The method of the embodiment of the invention starts with a substrate 101, and sequentially forms a carbon nanotube 110, a gate stack structure 120, a mask layer 102 and a sidewall 103 on the substrate 101, as shown in fig. 2a, wherein materials and structures of the substrate 101, the carbon nanotube 110, the gate stack structure 120, the mask layer 102 and the sidewall 103 may all refer to the related description of fig. 1, and are not repeated herein.
In this embodiment, the sidewall spacers 103 may be made of a multi-layer material of silicon oxide/silicon nitride, or a single material of silicon oxide or silicon nitride, which is determined according to different specific process requirements. And then, forming the sidewall morphology and width meeting the requirements by adopting a proper dry etching process. Since the morphology of the sidewall 1031 depends on the selection of a specific etching process and the integration process requirements of the gate structure, generally, the morphology of the sidewall 1031 often does not completely exhibit a steep shape.
Further, a sacrificial layer 104 is formed covering the carbon nanotubes 110, the mask layer 102 and the sidewalls 103, as shown in fig. 2 b.
In this step, the thickness of the sacrificial layer 104 is greater than the thickness of the metal film to be deposited later, and the sacrificial layer may be formed of a plurality of materials, which depends on the specific sidewall material, i.e., the film that is the same as the sidewall material cannot be used, but a higher etching selection ratio must exist between the two, so that the sacrificial layer can be removed in the subsequent process without affecting the sidewall material. For example, when the sidewall spacer is made of silicon oxide, the sacrificial layer may be made of silicon nitride, amorphous silicon, organic materials such as BARC or spin-on dielectrics with high fluidity such as sog (spin on glass), soc (spin on carbon), etc.; when the sidewall spacer is made of silicon nitride, the sacrificial layer may be made of silicon oxide, amorphous silicon, organic material such as BARC, or spin-on dielectric with high fluidity such as sog (spin on glass), soc (spin on carbon), etc. They may be formed using a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a spin-on process, or the like. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements for the material of the sacrificial layer 104 as needed.
Since the topography of the sidewall 1031 does not completely take on a steep shape, the topography of the sacrificial layer 104 formed by subsequent deposition thereon may also be affected, such that the topography of the sacrificial layer sidewall 1041 does not completely take on a steep shape. Further, a portion of sacrificial layer 104 is removed in the source and drain regions to form a plurality of patterns, as shown in FIG. 2 c.
In this step, for example, a suitable photolithography process is used to form a desired photolithography pattern on the sacrificial layer 104, to define the pattern and position of a plurality of openings, and then a dry etching process is used to remove a portion of the sacrificial layer 104 to form a plurality of openings 105, and the process parameters of the etching are adjusted, including: one or more of reaction pressure, reaction time, reaction temperature, radio frequency power, gas flow rate, etc., to control the etching to stop when the carbon nanotubes 110 are reached.
In the present embodiment, the openings 105 are located in the horizontal region of the device and located on two sides of the gate stack structure 120, respectively, and expose a portion of the carbon nanotubes 110, thereby defining the metal source/drain contact region.
Further, a metal layer 106 is formed to cover the sacrificial layer 104 and the carbon nanotubes 110, as shown in fig. 2 d.
In this step, the metal layer 106 is formed, for example, by an Atomic Layer Deposition (ALD) process or a Physical Vapor Deposition (PVD) process. Part of the metal layer is located in the opening and contacts the carbon nanotube 110, and the rest part is located on the sacrificial layer 104 and isolated from the side wall by the sacrificial layer 104.
In the present embodiment, when the fabricated carbon nanotube transistor is an N-type MOSFET, the deposited metal layer 104 is made of scandium, yttrium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy thereof, and when the fabricated carbon nanotube transistor is a P-type MOSFET, the deposited metal layer 104 is made of palladium, aluminum, titanium, gold, platinum, molybdenum, potassium, calcium, or an alloy thereof.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements for the material of the metal layer 106 as needed.
In this embodiment, since the profile of the sacrificial layer sidewall 1041 does not completely assume a steep shape, the profile of the metal layer 106 is affected, for example, when the PVD sputtering process is used, the thickness of the metal layer formed near the middle of the sacrificial layer sidewall 1041 (near the steep portion) is smaller, and the thickness of the metal layer formed on the horizontal surface of the device (e.g., the carbon nanotube 110) is larger. In this embodiment, the metal layer on the horizontal surfaces of the device has a thickness less than the thickness of the sacrificial layer.
Further, a portion of metal layer 106 is removed to expose at least a portion of sacrificial layer 104, as shown in fig. 2 e.
In this step, for example, a dry etching process or a wet etching process is used to remove a part of the metal layer 106, and the adjusting of the etching process parameters includes: one or more of reaction pressure, reaction time, reaction temperature, reaction rate, rf power, gas or liquid flow, etc., controls the etch to stop when portions of sacrificial layer 104 are exposed. Because the thickness of the metal layer formed near the middle of the sacrificial layer sidewall 1041 is smaller, the metal layer at the middle is removed first, so as to expose the surface of the sacrificial layer 104 near the middle of the sacrificial layer sidewall 1041, at this time, the etching or corrosion can be selectively stopped to continue, or the etching or corrosion process is stopped when the metal in the source/drain opening region is removed to a certain thickness according to the product requirement. Meanwhile, the metal layer formed on the horizontal surface of the device is partially removed, and the removed thickness is the same as the thickness of the metal layer formed near the middle of the sacrificial layer sidewall 1041. Because the metal layer formed on the horizontal surfaces of the device is thick, the metal layer on the horizontal surfaces remains when the etching or etching stops.
It should be noted that, in this step, by controlling the reaction time, reaction temperature, and the like, the metal layer 106 on the surface of the carbon nanotube 110 is completely removed to avoid over-etching or over-corrosion.
Further, the sacrificial layer 104 is removed to expose the sidewall spacers 103, as shown in fig. 2 f.
In this step, for example, a specific solution is used to dissolve the sacrificial layer, so that the rate of dissolving the sacrificial layer by the solution is much greater (e.g. 3: 1) than the rate of dissolving the metal layer, after the sacrificial layer is completely dissolved by the solution, the metal layer covering the sacrificial layer falls into the solution, and the metal layer on the carbon nanotube 110 is retained as the source contact structure 130 and the drain contact structure 140, respectively. In some embodiments, a dry etch technique may also be used to remove the sacrificial layer, but the sacrificial layer is required to be removed at a rate much greater (e.g., 3: 1) than the metal layer.
It should be noted that, both the wet etching process and the dry etching process require high selectivity (e.g. 3:1 or more) for the contact metal, the spacer material, the gate metal, and the like of the source and drain, otherwise, the related functional layers are greatly damaged in the process of removing the sacrificial layer 104.
According to the transistor and the manufacturing method thereof provided by the invention, the sacrificial layer covering the side wall is formed, when the metal layer is formed, the metal layer covers the sacrificial layer and the carbon nano tube, the side wall is prevented from being in direct contact with the metal layer through the isolation of the sacrificial layer, when the sacrificial layer is dissolved by adopting a solution, the metal layer covering the sacrificial layer enters the solution along with the metal layer, so that the metal layer covering the upper part of the sacrificial layer is separated from a device, and the source and drain contact structure is formed.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention.
Claims (11)
1. A method of manufacturing a transistor, comprising:
forming carbon nanotubes on a substrate;
forming a gate stack structure on the carbon nanotube;
forming a side wall covering the side wall of the gate stack structure;
forming a sacrificial layer at least covering the side wall;
forming a metal layer covering the carbon nanotubes and the sacrificial layer, wherein part of the metal layer on the carbon nanotubes is used as an electrical contact contacted with the carbon nanotubes;
removing a part of the metal layer by adopting a wet etching process or a dry etching process to expose the sacrificial layer; and
removing the sacrificial layer by wet or dry etching process to expose the side wall,
when the sacrificial layer is removed by adopting a wet etching process or a dry etching process, the sacrificial layer has a preset selection ratio compared with the carbon nano tube, the gate stack structure, the side wall and the electric contact.
2. The manufacturing method according to claim 1, wherein the step of removing the sacrifice layer includes: the sacrificial layer is dissolved by a solution,
wherein the metal layer covering the sacrificial layer enters the solution.
3. The manufacturing method according to claim 2, wherein a rate at which the solution dissolves the sacrificial layer is greater than a rate at which the metal layer is dissolved.
4. The manufacturing method according to claim 2, wherein the solution dissolves the sacrificial layer at a rate greater than a rate of dissolving the sidewall spacer and the gate stack structure.
5. The method of manufacturing of claim 1, wherein the step of removing the metal layer comprises etching or corroding the metal layer and stopping at the surface of the sacrificial layer.
6. The manufacturing method according to claim 5, wherein a thickness of the metal layer covering the carbon nanotubes is larger than a thickness of the metal layer at least partially covering the sacrificial layer, and reaction parameters are controlled such that etching or corrosion is stopped when the sacrificial layer is exposed.
7. The manufacturing method according to claim 1, wherein the sacrificial layer further covers the carbon nanotubes, and before the metal layer is formed, the manufacturing method further comprises removing a portion of the sacrificial layer to form at least two pattern regions,
the at least two graphic areas are respectively positioned at two sides of the gate stack structure, and at least part of the carbon nano tubes are exposed through the graphic areas.
8. The manufacturing method according to claim 7, wherein a thickness of the sacrificial layer is larger than a thickness of the metal layer at least at a surface of the carbon nanotube.
9. The manufacturing method according to any one of claims 1 to 8, wherein when the material of the sidewall spacers comprises silicon oxide, the material of the sacrificial layer comprises one or a combination of silicon nitride, amorphous silicon, an organic material and a spin-on medium with high fluidity;
when the material of the side wall comprises silicon nitride, the material of the sacrificial layer comprises one or a combination of silicon oxide, amorphous silicon, an organic material and a high-fluidity spin-on medium.
10. The manufacturing method according to any one of claims 1 to 8, wherein the predetermined selection ratio is not less than 3: 1.
11. A transistor formed by the manufacturing method according to any one of claims 1 to 10.
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| CN102569048A (en) * | 2010-12-21 | 2012-07-11 | 中国科学院微电子研究所 | Forming method of self-aligned metal silicide |
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