CN110783343A - Improved charge trapping memory - Google Patents
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- CN110783343A CN110783343A CN201911073823.6A CN201911073823A CN110783343A CN 110783343 A CN110783343 A CN 110783343A CN 201911073823 A CN201911073823 A CN 201911073823A CN 110783343 A CN110783343 A CN 110783343A
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- 230000015654 memory Effects 0.000 title claims abstract description 49
- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000005641 tunneling Effects 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 8
- 230000000903 blocking effect Effects 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 14
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 11
- 230000008569 process Effects 0.000 abstract description 8
- 230000000295 complement effect Effects 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
- 238000007667 floating Methods 0.000 description 11
- 238000012546 transfer Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005527 interface trap Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- Semiconductor Memories (AREA)
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Abstract
The present disclosure provides an improved charge trapping memory comprising, from top to bottom: a metal grid; a first blocking layer for preventing charge leakage from the gate electrode; a first trapping layer for storing charge; a tunneling layer; a second trapping layer for storing charge; a second blocking layer for preventing leakage of charges from the substrate; the edge of the substrate is provided with a source electrode and a drain electrode, and the substrate is grounded; the upper and lower barrier layers are arranged, so that the high-speed low-power-consumption high-reliability memory structure compatible with a CMOS (complementary metal oxide semiconductor) process is formed.
Description
Technical Field
The present disclosure relates to the field of memory technologies, and more particularly, to an improved charge trapping memory.
Background
Memory plays a very important role in the information society. Memory can be generally divided into two broad categories: volatile Memory (voltate Memory) and Non-Volatile Memory (NVM). Data stored in volatile memories, such as Dynamic Random Access Memories (DRAMs), Static Random Access Memories (SRAMs), is lost after power is removed; and the information of the non-volatile memory can still be kept after power failure, such as Flash memory (Flash). The basic unit of Flash is a floating gate field effect transistor (FG MOSFET). The earliest floating gate structures were proposed by Kahng and Sze in 1967, and their basic structures are shown in fig. 5: a layer of polysilicon (poly-Si) is wrapped in the middle of the silicon dioxide dielectric. This layer of polysilicon is called a Floating Gate (FG) because it does not have any electrical connection to it. When a higher voltage is applied to the FG-MOSFET gate, electrons in the channel or the substrate tunnel through a Tunneling Oxide (TOX) and are injected into the floating gate, so that the threshold voltage of the device becomes larger, and the state at this time is called a programmed state, i.e. a logic 0; conversely, when a large negative voltage is applied to the gate, electrons stored in the floating gate are pulled back to the substrate, and the device is at a low threshold, which is referred to as an erased state, i.e., a logic 1.
With the gradual reduction of the device size, the floating gate memory approaches the physical limit under the 20nm process, and the cross talk between memory cells and the leakage from the thin band of the tunneling oxide layer become important reliability problems for limiting the reduction of the floating gate memory size. The charge trapping memory adopts a charge trapping layer such as silicon nitride rich in charge traps to replace a floating gate layer in the floating gate memory, and overcomes the problems of the floating gate in scaling down by utilizing a discrete charge storage mechanism, so that the charge trapping memory is considered to be a possible alternative. In addition to small size, the charge trapping memory has the advantages of good endurance, simple process, compatibility with standard CMOS process, etc., but also has some problems, such as slow erase speed, power consumption not reaching practical application level, partial leakage of charges when the tunneling layer is thin, and in addition, the program erase operation may cause defects at the interface between the gate dielectric and the substrate, thereby causing degradation of device performance.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
Technical problem to be solved
In view of the above problems, the present disclosure provides an improved charge trapping memory to alleviate the technical problems in the prior art, such as slow erasing speed of the memory, power consumption that does not reach the practical application level, partial leakage of charges when the tunneling layer is thin, and degradation of device performance due to defects at the interface between the gate dielectric and the substrate caused by program erase operation.
(II) technical scheme
The present disclosure provides an improved charge trapping memory comprising, from top to bottom: a metal grid 1; a first blocking layer 2 for preventing leakage of charges from the gate electrode; a first trapping layer 3 for storing charge; a tunneling layer 4 for enabling charges to move between the first trapping layer and the second trapping layer by a tunneling effect; a second trapping layer 5 for storing charge; a second barrier layer 6 for preventing leakage of charge from the substrate; a substrate with a source 7 and a drain 8 at its edges, the substrate being grounded.
In the disclosed embodiment, the material for preparing the first trapping layer 3 includes: si
3N
4，HfO
2，ZrO
2At least one of them.
In the disclosed embodiment, the material for preparing the second trapping layer 5 includes: si
3N
4，HfO
2，ZrO
2At least one of them.
In the embodiment of the present disclosure, the preparation material of the tunneling layer 4 includes: HfO
2、Al
2O
3，SiO
2At least one of them.
In the embodiment of the present disclosure, the thickness of the tunneling layer 4 is 3 ± 1 nm.
In the disclosed embodiment, the preparation material of the first barrier layer 2 includes: al (Al)
2O
3，HfO
2，SiO
2At least one of them.
In the disclosed embodiment, the material for preparing the second barrier layer 6 includes: al (Al)
2O
3，HfO
2，SiO
2At least one of them.
In the disclosed embodiments, the first barrier layer 2 and/or the second barrier layer 6 have a thickness of 10-15 nm.
In the disclosed embodiment, the states include: a programmed state, and an erased state.
In the disclosed embodiments, the programmed state is in a high threshold state and the erased state is in a low threshold state.
(III) advantageous effects
As can be seen from the above technical solutions, the improved charge trap memory of the present disclosure has at least one or some of the following advantages:
(1) the device only needs to control electrons to pass through a thin tunneling layer, so that the working speed of the device is high;
(2) the device is extremely small in electronic operation and low in power consumption;
(3) the existence of the upper and lower barrier layers effectively blocks the leakage of charges, so that the charge leakage problem is well inhibited;
(4) the preparation process of the device is completely compatible with the traditional CMOS process, and has cost advantage;
(5) the charge transfer does not pass through the interface of the gate dielectric/the substrate and is not influenced by an interface trap, so that the device has better tolerance characteristics.
Drawings
FIG. 1 is a schematic diagram of an improved charge trapping memory according to an embodiment of the present disclosure.
FIG. 2 is a schematic diagram of the improved charge trapping memory of FIG. 1 in a programmed state.
FIG. 3 is a schematic diagram of the improved charge trapping memory of FIG. 1 in an erased state.
FIG. 4 is a graph showing Id-Vg transfer characteristics for different states of the improved charge trapping memory of FIG. 1.
Fig. 5 is a schematic diagram of a conventional floating gate structure.
[ description of main reference numerals in the drawings ] of the embodiments of the present disclosure
1-a metal gate; 2-a first barrier layer; 3-a first trapping layer; 4-a tunneling layer;
5-a second trapping layer; 6-a second barrier layer; a 7-source electrode; 8-drain electrode.
Detailed Description
The present disclosure provides an improved charge trapping memory, which is a high-speed, low-power consumption and high-reliability memory structure compatible with CMOS process by the arrangement of upper and lower barrier layers.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In an embodiment of the present disclosure, an improved charge trapping memory is provided, as shown in fig. 1, the improved charge trapping memory includes, from top to bottom:
a metal grid 1;
a first blocking layer 2 for preventing leakage of charges from the gate electrode;
a first trapping layer 3 for storing charge;
tunneling layer 4, the effect is: a. isolating the first trapping layer from the second trapping layer, b. charges are able to move between the first trapping layer and the second trapping layer by tunneling effects;
a second trapping layer 5 for storing charge;
a second barrier layer 6 for preventing leakage of charge from the substrate;
a substrate with a source 7 and a drain 8 at its edges, the substrate being grounded.
The first trapping layer 3 and/or the second trapping layer 5 are made of materials including: si
3N
4，HfO
2，ZrO
2；
The preparation material of the tunneling layer 4 comprises: HfO
2、Al
2O
3，SiO
2；
The thickness of the tunneling layer 4 is 3nm +/-1 nm;
the preparation materials of the first barrier layer 2 and/or the second barrier layer 6 comprise: al (Al)
2O
3，HfO
2，SiO
2；
The thickness of the first barrier layer 2 and/or the second barrier layer 6 is 10-15 nm;
the first trapping layer 3 and/or the second trapping layer 5 are/is made of oxide materials with more traps; the tunneling layer 4 is made of oxide with a relatively thin thickness; the first barrier layer 2 and/or the second barrier layer 6 are/is made of oxide with larger thickness;
in an embodiment of the present disclosure, the improved charge trapping memory comprises: a programmed state, and an erased state;
as shown in FIG. 2, during the programming operation, the source, the drain and the substrate of the device are grounded, a short pulse voltage with an amplitude of about 5V is applied to the metal gate, electrons move upwards and are collected in the first trapping layer, holes move downwards and are collected in the second trapping layer, and an internal electric field pointing from the second trapping layer to the first trapping layer is formed, which is called a programmed state;
as shown in FIG. 3, during the erase operation, the source, drain and substrate of the device are grounded, a short pulse voltage of about-5V is applied to the metal gate, electrons are collected in the second trapping layer, holes are collected in the first trapping layer, and an internal electric field is formed from the first trapping layer to the second trapping layer, which is referred to as the erased state.
The direction of the internal electric field affects the threshold voltage of the device, so that a smaller read voltage can be applied to distinguish whether the improved charge trapping memory device is in the programmed state (0) or the erased state (1).
Test I
d-V
gTransfer characteristic curve: at a fixed source-drain voltage (V)
DS) The relationship between the drain current and the gate-source voltage of the transistor saturation region.
The device substrate, the source is grounded, a bias of about 2V is applied to the metal gate, a bias of 0.5V is applied to the drain, and the source current is detected.
I
dIs the drain current, V
gIs the gate voltage, the threshold voltage is the gate voltage at which the improved charge trapping memory is turned on, the programmed (programmed) device is in the high threshold state with the transfer characteristic curve shown as line ① in fig. 4, and the erased (erased) device is in the low threshold state with the I
d-V
gThe transfer characteristic is shown as line ② in FIG. 4. by choosing a reasonable read voltage (between the high and low thresholds), the two states can be distinguished, achieving the function of 0 and 1 storage.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
From the above description, those skilled in the art should clearly recognize that the charge trapping memory improved by the present disclosure is provided.
In summary, the present disclosure provides an improved charge trapping memory, which is provided with two barrier layers, namely an upper barrier layer and a lower barrier layer, to effectively block charge leakage, so that the charge leakage problem is well suppressed; and the charge transfer does not pass through the interface of the gate dielectric/the substrate and is not influenced by an interface trap, so that the device has better tolerance characteristics.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. An improved charge trapping memory comprising, from top to bottom:
a metal grid (1);
a first blocking layer (2) for preventing leakage of charge from the gate;
a first trapping layer (3) for storing charge;
a tunneling layer (4) for enabling charges to move between the first trapping layer and the second trapping layer by a tunneling effect;
a second trapping layer (5) for storing charge;
a second barrier layer (6) for preventing leakage of charge from the substrate;
the substrate, its edge is provided with source (7), and drain-source resistance (8), and the substrate ground.
2. The improved charge trap memory of claim 1, the first trapping layer (3) being made of a material comprising: si
3N
4，HfO
2，ZrO
2At least one of them.
3. The improved charge trap memory of claim 1, the second trapping layer (5) being made of a material comprising: si
3N
4，HfO
2，ZrO
2At least one of them.
4. The improved charge trapping memory of claim 1, wherein said tunneling layer (4) is made of a material comprising: HfO
2、Al
2O
3，SiO
2At least one of them.
5. The improved charge trapping memory of claim 3, wherein said tunneling layer (4) has a thickness of 3 + 1 nm.
6. The improved charge trap memory of claim 1, the first blocking layer (2) being made of a material comprising: al (Al)
2O
3，HfO
2，SiO
2At least one of them.
7. The improved charge trap memory of claim 1, the second blocking layer (6) being made of a material comprising: al (Al)
2O
3，HfO
2，SiO
2At least one of them.
8. The improved charge trap memory according to claim 6 or 7, the first barrier layer (2) and/or the second barrier layer (6) having a thickness of 10-15 nm.
9. The improved charge trapping memory of claim 1, having states comprising: a programmed state, and an erased state.
10. The improved charge trapping memory of claim 9, having a high threshold state in a programmed state and a low threshold state in an erased state.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911073823.6A CN110783343A (en) | 2019-11-05 | 2019-11-05 | Improved charge trapping memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911073823.6A CN110783343A (en) | 2019-11-05 | 2019-11-05 | Improved charge trapping memory |
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| Publication Number | Publication Date |
|---|---|
| CN110783343A true CN110783343A (en) | 2020-02-11 |
Family
ID=69389415
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571161A (en) * | 2003-04-30 | 2005-01-26 | 三星电子株式会社 | Nonvolatile semiconductor memory device and method of manufacturing the same |
| US20080067577A1 (en) * | 2006-09-15 | 2008-03-20 | Ming-Tsong Wang | Multi-trapping layer flash memory cell |
| CN102655167A (en) * | 2011-03-02 | 2012-09-05 | 中国科学院微电子研究所 | Charge-trapping type gate stack and storage unit |
-
2019
- 2019-11-05 CN CN201911073823.6A patent/CN110783343A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1571161A (en) * | 2003-04-30 | 2005-01-26 | 三星电子株式会社 | Nonvolatile semiconductor memory device and method of manufacturing the same |
| US20080067577A1 (en) * | 2006-09-15 | 2008-03-20 | Ming-Tsong Wang | Multi-trapping layer flash memory cell |
| CN102655167A (en) * | 2011-03-02 | 2012-09-05 | 中国科学院微电子研究所 | Charge-trapping type gate stack and storage unit |
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Application publication date: 20200211 |