CN110783257B - 具有对称的导电互连图案的半导体器件 - Google Patents
具有对称的导电互连图案的半导体器件 Download PDFInfo
- Publication number
- CN110783257B CN110783257B CN201910385004.9A CN201910385004A CN110783257B CN 110783257 B CN110783257 B CN 110783257B CN 201910385004 A CN201910385004 A CN 201910385004A CN 110783257 B CN110783257 B CN 110783257B
- Authority
- CN
- China
- Prior art keywords
- pattern
- preliminary
- conductive interconnect
- patterns
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 142
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 113
- 239000000463 material Substances 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 29
- 230000000903 blocking effect Effects 0.000 claims description 28
- 239000004020 conductor Substances 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 239000011800 void material Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims 1
- 238000005137 deposition process Methods 0.000 description 18
- 238000000206 photolithography Methods 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开了具有对称的导电互连图案的半导体器件。半导体器件可以包括:下层间电介质层,在下层间电介质层之上的导电互连图案结构和填充图案,以及在导电互连图案结构和填充图案之上的上层间电介质层。每个导电互连图案结构可以包括在其中部的中间图案、在中间图案的第一侧表面上的第一导电互连图案以及在中间图案的第二侧表面上的第二导电互连图案。第一导电互连图案和第二导电互连图案可以具有彼此对称的结构。
Description
相关申请的交叉引用
本申请要求于2018年7月24日提交的第10-2018-0085972号韩国专利申请的优先权,其内容通过引用整体合并于此。
技术领域
本专利文件中公开的技术和实施方式涉及对称的导电互连图案及其形成方法,所述对称的导电互连图案的宽度和/或空隙小于在光刻工艺中形成的掩模图案的宽度和/或空隙。
背景技术
随着半导体器件的集成度增加,导电互连图案的水平宽度和间隔逐渐变小。为了形成细图案,要使用昂贵的光刻设备和复杂的光刻工艺。例如,要使用双重曝光工艺、双重图案化工艺、双重间隔件工艺等。因为类似的工艺被执行两次,所以这些双重工艺非常复杂并且失败概率高。
发明内容
示例性实施例提供了一种形成导电互连图案的方法,所述导电互连图案的宽度和空隙比光刻工艺中形成的掩模图案的线宽和间隔更细。
示例性实施例提供了一种形成导电互连图案的方法,所述导电互连图案的宽度和空隙比主要通过使用单重间隔件形成技术而形成的图案的线宽和间隔更细。
所公开的技术的具体实施方式中的各种目的可以被实现,并且所公开的技术的应用不限于本专利文件中公开的具体实施方式或示例。
根据一个实施例,一种半导体器件可以包括:下层间电介质层;在下层间电介质层之上的导电互连图案结构和填充图案;以及在导电互连图案结构和填充图案之上的上层间电介质层。每个导电互连图案结构可以包括在其中部的中间图案、在中间图案的第一侧表面上的第一导电互连图案、以及在中间图案的第二侧表面上的第二导电互连图案。第一导电互连图案和第二导电互连图案可以具有彼此对称的结构。
根据一个实施例,一种用于制造半导体器件的方法可以包括:形成阻止层;在阻止层之上形成中间图案材料层;通过将中间图案材料层图案化而形成多个第一初步中间图案;通过使第一初步中间图案收缩而形成多个第二初步中间图案;形成导电材料层以覆盖第二初步中间图案;通过将导电材料层图案化而形成多个初步导电互连图案;在初步导电互连图案之间形成填充层;以及通过去除填充层、初步导电互连图案和第二初步中间图案的顶部而形成多个中间图案、多个导电互连图案和多个填充图案。
根据一个实施例,一种用于制造半导体器件的方法可以包括:在衬底之上形成下层间电介质层;在下层间电介质层之上形成阻止层;在阻止层之上形成第一初步中间图案;通过使第一初步中间图案收缩而形成第二初步中间图案;形成初步导电互连图案以覆盖第二初步中间图案的顶表面和两个侧表面;在初步导电互连图案之间形成填充层;通过去除填充层、初步导电互连图案和第二初步中间图案中的每个的顶部,形成具有侧表面的中间图案、在中间图案的侧表面上的导电互连图案以及在导电互连图案之间的填充图案;在中间图案、导电互连图案和填充图案之上形成覆盖层;以及在覆盖层之上形成上层间电介质层。
其他实施例的细节包括在详细描述和附图中。
附图说明
图1至图9是示出根据本公开的实施例的形成半导体存储器件的导电互连图案的方法的截面图。
图10至图15是示出根据本公开的实施例的形成半导体存储器件的导电互连图案的方法的截面图。
具体实施方式
下面将参考附图来更详细地描述各种实施例。然而,本公开的实施例可以具有不同的形式,并且不应该被解释为限于本文阐述的实施例。相反,提供这些实施例是为了使本公开彻底和完整,并且将向本领域技术人员充分传达权利要求的范围。
在整个说明书中,相同的附图标记表示相同的元件。因此,尽管在对应的附图中没有提及或描述相同或相似的附图标记,但是可以参考其他附图来描述这些附图标记。此外,尽管没有通过附图标记来表示元件,但是可以参考其他附图来描述所述元件。
图1至图9是示出根据实施例的形成半导体器件的导电互连图案的方法的截面图。
参考图1,形成半导体器件的导电互连图案的方法可以包括:通过执行第一沉积工艺在衬底10上形成下层间电介质层20;通过执行第二沉积工艺在下层间电介质层20上形成阻止层30;通过执行第三沉积工艺在阻止层30上形成中间图案材料层40;以及通过执行光刻工艺在中间图案材料层40上形成掩模图案M。
衬底10可以包括单晶硅晶片、外延生长的单晶硅层和绝缘体上硅(SOI)层中的至少一种。在一些实施例中,衬底10可以是覆盖各种电路的电介质材料。
下层间电介质层20可以包括覆盖形成在衬底10上的各种电路(未示出)的电介质材料。例如,下层间电介质层20可以包括氧化硅(SiO2)、氮化硅(SiN)、氮氧化硅(SiON)、硅氢氧化物(SiOH)和硅碳氧化物(SiCO)中的至少一种,或其任意组合。第一沉积工艺可以包括化学气相沉积(CVD)工艺。
阻止层30可以包括比下层间电介质层20和中间图案材料层40更致密和更硬的电介质材料。阻止层30可以包括与下层间电介质层20不同或下层间电介质层20中不包括的材料,使得阻止层30的刻蚀选择性不同于下层间电介质层20和中间图案材料层40两者。例如,阻止层30可以包括氮化硅(SiN)、氮氧化硅(SiON)、诸如硅氢氧化物(SiOH)的含氢(H)材料、诸如硅碳氧化物(SiCO)的含碳(C)材料以及硅碳氮化物(SiCN)或硅碳氮氧化物(SiCON)中的至少一种,或其任意组合。因此,第二沉积工艺可以包括CVD工艺以形成氮化硅层。
中间图案材料层40可以包括氧化硅(SiO2)、氮化硅(SiN)、氮氧化硅(SiON)、诸如硅氢氧化物(SiOH)的含氢(H)材料、诸如硅碳氧化物(SiCO)的含碳(C)材料、硅碳氮化物(SiCN)以及硅碳氮氧化物(SiCON)中的至少一种,或其任意组合。例如,第三沉积工艺可以包括CVD工艺以形成氧化硅层。
掩模图案M可以包括包含有机聚合物材料(例如光致抗蚀剂)的有机图案,和/或诸如氧化硅(SiO2)、氮化硅(SiN)、氮氧化硅(SiON)、硅碳氮化物(SiCN)或硅碳氮氧化物(SiCON)的其他无机图案。
掩模图案M的水平宽度W1可以与掩模图案M之间的水平间隔W2基本相等或相近。掩模图案M的水平宽度W1和掩模图案M之间的水平间隔W2可以是处于或接近于光刻工艺的最小分辨率的尺寸。最小分辨率可以表示或指代在任何给定的光刻装置中可以形成的图案内的最小宽度和/或最小间隔。
参考图2,该方法可以包括通过使用掩模图案M作为刻蚀掩模而执行第一刻蚀工艺来将中间图案材料层40图案化。中间图案材料层40可以被图案化为第一初步中间图案41。每个第一初步中间图案41可以具有水平延伸的线形或条形形状。在第一初步中间图案41之间可以存在第一沟槽空隙TS1。在第一初步中间图案41之间可以暴露出阻止层30。在第一刻蚀工艺中,掩模图案M的垂直高度和水平宽度(如图2所示)可以减小。
参考图3,该方法可以包括例如通过执行灰化工艺或剥离工艺来去除掩模图案M。灰化工艺可以包括氧(O2)等离子体工艺。剥离工艺可以包括使用氢氟酸或磷酸的湿法去除工艺和硫酸沸腾工艺。第一初步中间图案41的第一水平宽度Wp1可以与第一沟槽空隙TS1的第一水平宽度Ws1基本相等或相近,即,Wp1=Ws1。再次参考图1,第一初步中间图案41的第一水平宽度Wp1可以基本上等于或者接近于或者小于掩模图案M的水平宽度W1。第一沟槽空隙TS1的第一水平宽度Ws1可以基本上等于或者接近于或者大于掩模图案M之间的水平间隔W2。
参考图4,该方法可以包括通过执行收缩工艺使第一初步中间图案41收缩来形成第二初步中间图案42。收缩工艺可以包括使用稀释的刻蚀剂的软刻蚀工艺,或使用浓缩的清洁液的强清洁工艺。例如,形成第二初步中间图案42可以包括:通过执行各向同性刻蚀工艺等来部分地去除第一初步中间图案41的上部和所有侧部、或上面部分和所有侧面部分。第一初步中间图案41的大小缩小到第二初步中间图案42。当材料从第一初步中间图案41的侧面区域或部位被去除时,第一沟槽空隙TS1可以变换为扩宽的第二沟槽空隙TS2。即,收缩工艺可以包括扩宽第一沟槽空隙TS1以形成第二沟槽空隙TS2。第二沟槽空隙TS2的水平宽度Ws2可以是第二初步中间图案42的水平宽度Wp2的大约三倍大。水平宽度Wp2与水平宽度Ws2的尺寸之比可以是1:3。垂直高度(即厚度)可以按照第一初步中间图案41的一半的比例来收缩。
参考图5,该方法还可以包括通过执行沉积工艺来完整地形成导电材料层60以覆盖第二初步中间图案42的暴露出的表面。这可以是该方法中的第四沉积工艺。例如,导电材料层60可以包括诸如金属的导体。导电材料层60可以完全覆盖第二初步中间图案42。导电材料层60可以沿着第二初步中间图案42的轮廓而半共形(semi-conformal)地形成。沉积工艺可以包括溅射工艺、物理气相沉积(PVD)工艺或CVD工艺以形成金属层。
参考图6,该方法还可以包括通过在第二刻蚀工艺中对导电材料层60进行毯式刻蚀(blanket-etching)来形成第一初步导电互连图案61。第二刻蚀工艺可以包括各向异性回蚀工艺。例如,第二刻蚀工艺可以包括物理溅射刻蚀工艺。随着导电材料层60在垂直和水平方向上均被收缩或缩小,通过使用用于形成间隔件形状的回蚀工艺可以形成具有丘形或鞘形形状的第一初步导电互连图案61,所述第一初步导电互连图案61覆盖或包围第二初步中间图案42。换言之,第一初步导电互连图案61可以完全覆盖第二初步中间图案42的顶表面和侧表面。在第一初步导电互连图案61之间可以暴露出阻止层30的表面。第一初步导电互连图案61可以被转换为或配置为用作彼此物理和电分隔的单独图案。
参考图7,该方法还可以包括通过执行沉积工艺来全部地或完整地形成覆盖第一初步导电互连图案61的填充层70。这可以是第五沉积工艺。填充层70可以填充第一初步导电互连图案61之间的空隙。填充层70可以包括氧化硅(SiO2)、氮化硅(SiN)和氮氧化硅(SiON)中的至少一种,或其任意组合。沉积工艺可以包括CVD工艺以形成氧化硅层。
参考图8,该方法还可以包括:通过执行化学机械抛光(CMP)工艺而部分地去除填充层70的、第一初步导电互连图案61的、以及第二初步中间图案42的上部或上面区域,来形成导电图案结构100A和填充图案71。每个得到的导电图案结构100A可以包括在导电互连图案62L和62R之间、或被导电互连图案62L和62R夹在中间的中间图案43。例如,导电图案结构100A包括位于中部的中间图案43、位于中间图案43的左侧的左导电互连图案62L、以及位于中间图案43的右侧的右导电互连图案62R。两个或更多个导电图案结构100A可以间隔开地形成在阻止层30上。填充图案71可以形成在导电图案结构100A之间的阻止层30上。例如,左导电互连图案62L可以形成在中间图案43的左侧表面上,右导电互连图案62R可以形成在中间图案43的右侧表面上。每个左导电互连图案62L可以具有基本上垂直且平坦的、与中间图案43靠近或接触的右侧表面,以及非平面的并且在垂直方向上从与阻止层30的表面靠近或接触的较宽的基部(较宽的下部)到较窄的上部而渐变的左侧表面。例如,导电互连图案62L的左侧表面的截面可以是弧形(rounded)且倾斜的,例如依循圆弧或椭圆弧,使得上部较窄而下部较宽。每个右导电互连图案62R可以具有基本上垂直且平坦的、与中间图案43靠近或接触的左侧表面,以及非平面的并且在垂直方向上从与阻止层30的表面靠近或接触的较宽的基部(较宽的下部)到较窄的上部而渐变的右侧表面。例如,导电互连图案62R的右侧表面的截面可以是弧形并且倾斜的,使得上部较窄而下部较宽,例如沿着圆弧或椭圆弧。左导电互连图案62L和右导电互连图案62R可以形成两侧对称结构,中间图案43位于该结构的中部。例如,左导电互连图案62L和右导电互连图案62R可以交替地设置在中间图案43的任一侧上以彼此面对或相对。左导电互连图案62L和右导电互连图案62R可以具有基本平坦或平面的底(或下)表面和顶(或上)表面。左导电互连图案62L和右导电互连图案62R的顶表面的水平宽度可以小于左导电互连图案62L和右导电互连图案62R的与阻止层30靠近或接触的底表面的水平宽度Wa。填充图案71可以设置在导电图案结构100A之间。例如,在一个导电图案结构100A的左导电图案62L与相邻导电图案结构100A的右导电图案62R之间的空隙或间隙中的阻止层30上可以形成填充图案71。填充图案71还可以设置在一个导电图案结构100A的右导电图案62R和另一个相邻导电图案结构100A的左导电图案62L之间。
每个中间图案43可以具有基本上垂直且平坦的两个侧表面,所述两个侧表面与左导电互连图案62L和右导电互连图案62R靠近或接触。每个填充图案71可以具有非平面的并且在垂直方向上从与阻止层30靠近或接触的较窄基部(较窄下部)到较宽上表面而渐变的侧表面。例如,填充图案71的两个侧表面可以是反弧形(negatively rounded)的,使得上部较宽而下部较窄。所述弧形的侧面可以具有依循圆弧或椭圆弧的截面形状。
CMP工艺可以包括第一CMP工艺、第二CMP工艺和第三CMP工艺。第一CMP工艺可以主要去除填充层70。第二CMP工艺可以去除填充层70和初步导电互连图案61。第三CMP工艺可以去除填充层70、初步导电互连图案61和第二初步中间图案42。中间图案43、导电互连图案62L和62R以及填充图案71可以基本上彼此共面。在第二CMP工艺和第三CMP工艺中,中间图案43可以用作CMP阻止层。
在本文公开的实施例中,左导电互连图案62L和右导电互连图案62R在与阻挡层30靠近或接触处可以具有水平宽度Wa和/或水平间隔Wb,该水平宽度Wa和/或水平间隔Wb小于光刻工艺的极限(临界)分辨率的最小水平宽度W1和/或最小水平间隔W2。作为示例,在左导电互连图案62L与右导电互连图案62R之间的水平间隔Wb可以等于或接近于中间图案43和/或填充图案71的水平宽度,它们中的每个都小于W1和/或W2。
在本文公开的实施例中,左导电互连图案62L或右导电互连图案62R的水平宽度Wa与左导电互连图案62L和右导电互连图案62R之间的水平间隔Wb的和可以等于或基本上等于极限分辨率的最小水平宽度W1和/或最小水平间隔W2。例如,Wa+Wb=W1=W2=Wp1=Ws1。
参考图9,该方法可以包括通过执行沉积工艺在导电图案结构100A和填充图案71上形成覆盖层80。这可以是第六沉积工艺。该方法还可以包括通过执行另一沉积工艺在覆盖层80上形成上层间电介质层90,其可以是第七沉积工艺。覆盖层80可以包括比用于形成中间图案43和填充图案71的材料更致密和更硬的材料。例如,覆盖层80可以包括氮化硅(SiN)、氮氧化硅(SiON)及其组合中的至少一种。因此,第六沉积工艺可以包括用于沉积氮化硅(SiN)的CVD工艺。上层间电介质层90可以包括氧化硅(SiO2)、氮化硅(SiN)、氮氧化硅(SiON)、硅氢氧化物(SiOH)和硅碳氧化物(SiCO)中的至少一种,或其任意组合。例如,第七沉积工艺可以包括CVD工艺以形成氧化硅(SiO2)。
在所公开的实施例中,通过仅在光刻工艺中使用掩模图案可以形成具有比极限(临界)分辨率更高的分辨率的图案。
图10至图15是示出根据实施例的形成半导体器件的导电互连图案的方法的截面图。
参考图10,形成半导体器件的导电互连图案的方法可以包括:通过执行参考图1至图4的上述一系列工艺,而在衬底10之上顺序地形成下层间电介质层20、阻止层30、中间图案材料层40和掩模图案M,通过图案化中间图案材料层40来形成第一初步中间图案41,去除掩模图案M,并且通过收缩第一初步中间图案41来形成第二初步中间图案42,然后形成阻挡材料层50以覆盖或包围阻止层30的暴露出的部分和第二初步中间图案42的暴露出的区域。
阻挡材料层50可以共形地形成在第二初步中间图案42的顶表面和侧表面以及阻止层30的暴露出的表面上。阻挡材料层50可以包括诸如氮化钛(TiN)、氮化钽(TaN)、或氮化钨(WN)的导电阻挡材料,或诸如氮化硅(SiN)或氮氧化硅(SiON)的电介质阻挡材料中的至少一种。可以通过执行PVD工艺或CVD工艺来形成阻挡材料层50。
参考图11,该方法还可以包括通过执行参考图5的上述工艺来形成全部地或完整地覆盖阻挡材料层50的暴露出的表面的导电材料层60。阻挡材料层50可以增强第二初步中间图案42与导电材料层60之间的粘附。
参考图12,该方法还可以包括:通过执行参考图6的上述工艺,通过毯式刻蚀导电材料层60来形成初步导电互连图案61,以及通过顺序地刻蚀导电材料层60和阻挡材料层50以在与阻止层30靠近或接触的阻挡材料层50和导电材料层60中产生间隙或空隙来形成初步阻挡图案51。结果,在初步导电互连图案61与初步阻挡图案51之间可以暴露出阻止层30的上表面的部分。
参考图13,该方法还可以包括通过执行参考图7的上述工艺在整个所得结构上形成填充层70。
参考图14,该方法还可以包括:通过执行CMP工艺来部分地去除填充层70、初步导电互连图案61、初步阻挡图案51和第二初步中间图案42的上面的部位而形成导电图案结构100B和填充图案71。导电图案结构100B可以包括中间图案43、左阻挡图案52L、右阻挡图案52R、左导电互连图案62L和右导电互连图案62R。填充图案71可以设置在导电图案结构100B之间。
每个中间图案43可以具有基本上垂直且平坦的两个侧表面,所述两个侧表面与左导电互连图案62L和右导电互连图案62R靠近或接触。每个填充图案71可以具有两个侧表面,所述两个侧表面非平面并且在垂直方向上从与阻止层30靠近或接触的较窄基部到较宽上表面而渐变。例如,填充图案71的两个侧表面可以是反弧形的,使得上部较宽而下部较窄。所述弧形的侧面可以具有依循圆弧或椭圆弧的截面形状。
每个左阻挡图案52L可以包括在中间图案43的左侧表面与左导电互连图案62L的右侧表面之间的垂直部分,以及在左导电互连图案62L的底(或下)表面与阻止层30的顶表面之间的水平部分。每个右阻挡图案52R可以包括在中间图案43的右侧表面与右导电互连图案62R的左侧表面之间的垂直部分,以及在右导电互连图案62R的底表面与阻止层30的顶表面之间的水平部分。换言之,每个左阻挡图案52L可以具有反L形截面,并且每个右阻挡图案52R可以具有L形截面。因此,左阻挡图案52L和右阻挡图案52R可以形成以中间图案43为中部的两侧对称结构。
每个左导电互连图案62L可以具有与左阻挡图案52L靠近或接触的基本上垂直且平坦的右侧表面,以及非平面的并且在垂直方向上从与阻止层30靠近或接触的较宽基部到较窄上部而渐变的左侧表面。例如,导电互连图案62L的左侧表面的截面可以是弧形的并且倾斜的,例如依循圆弧或椭圆弧,使得上部较窄而下部较宽。每个右导电互连图案62R可以具有与右阻挡图案52R靠近或接触的基本上垂直且平坦的左侧表面,以及非平面的并且在垂直方向上从与阻止层30靠近或接触的较宽基部到较窄上部而渐变的右侧表面。例如,导电互连图案62R的右侧表面的截面可以是弧形的并且倾斜的,使得上部较窄而下部较宽,例如沿着圆弧或椭圆弧。左导电互连图案62L与右导电互连图案62R可以形成两侧对称结构,在该结构的中部具有中间图案43。
每个填充图案71可以具有渐变的侧表面,所述侧表面具有反斜面(negativeslope)。例如,填充图案71的两个侧表面可以是反弧形的,使得上部较宽而下部较窄。所述弧形的侧面可以具有依循圆弧或椭圆弧的截面形状。
作为CMP工艺的结果,中间图案43、左阻挡图案52L和右阻挡图案52R、左导电互连图案62L和右导电互连图案62R以及填充图案71可以基本上彼此共面。中间图案43可以用作CMP阻止层。
参考图15,该方法还可以包括:通过执行参考图9的上述一系列工艺,在导电图案结构100B上形成覆盖层80并在覆盖层80上形成上层间电介质层90。
根据所公开的实施例,可以形成具有比光刻工艺中的掩模图案的宽度和间隔小的宽度和间隔的导电互连图案。
根据所公开的实施例,可以通过执行一次光刻工艺和用于形成丘形或鞘形形状的一次回蚀工艺来形成导电互连图案,所述导电互连图案的宽度和间隔小于在光刻工艺中形成的掩模图案的宽度和间隔。
虽然已经在特定实施例方面描述了本发明,但是应注意,本领域技术人员可以在不脱离由以下权利要求所限定的本发明的精神和/或范围的情况下通过执行替换、改变和修改而以各种方式来实现本发明。因此,应该注意实施例不是限制性的而是描述性的。
Claims (18)
1.一种用于制造半导体器件的方法,包括:
形成阻止层;
在所述阻止层之上形成中间图案材料层;
通过将所述中间图案材料层图案化而形成多个第一初步中间图案,以在所述多个第一初步中间图案之间形成多个第一沟槽空隙;
通过使所述第一初步中间图案收缩而扩宽所述多个第一沟槽空隙来形成多个第二沟槽空隙,以形成多个第二初步中间图案;
形成覆盖所述第二初步中间图案的导电材料层;
通过将所述导电材料层图案化而形成多个初步导电互连图案;
在所述初步导电互连图案之间形成填充层;和
通过去除所述填充层的顶部、所述初步导电互连图案的顶部和所述第二初步中间图案的顶部而形成多个中间图案、多个导电互连图案和多个填充图案,
其中,所述第一初步中间图案的垂直高度和水平宽度大于所述第二初步中间图案的垂直高度和水平宽度,
其中,所述多个第一初步中间图案的顶表面被降低成为所述多个第二初步中间图案的顶表面。
2.如权利要求1所述的方法,其中,所述导电互连图案包括形成在所述中间图案的左侧的左导电互连图案和形成在所述中间图案的右侧的右导电互连图案,
其中,所述左导电互连图案中的每个包括平坦的右侧表面和弧形的左侧表面,以及
所述右导电互连图案中的每个包括平坦的左侧表面和弧形的右侧表面。
3.如权利要求2所述的方法,其中,所述中间图案中的每个包括两个平坦的侧表面,以及
所述填充图案中的每个包括两个弧形以具有反斜面的侧表面,使得底部窄而顶部宽。
4.如权利要求2所述的方法,其中,每个左导电互连图案的水平宽度与每个中间图案的水平宽度之和等于每个第一初步中间图案的水平宽度。
5.如权利要求2所述的方法,其中,每个右导电互连图案的水平宽度与每个中间图案的水平宽度之和等于每个第一初步中间图案的水平宽度。
6.如权利要求2所述的方法,其中,每个左导电互连图案的水平宽度与每个右导电互连图案的水平宽度之和等于每个第一初步中间图案的水平宽度。
7.如权利要求1所述的方法,其中,所述中间图案材料层和所述填充层包括氧化硅、氮化硅以及氮氧化硅中的至少一种,或其任意组合。
8.如权利要求1所述的方法,其中,所述导电材料层包括金属。
9.如权利要求1所述的方法,其中,通过将所述导电材料层图案化而形成所述初步导电互连图案的步骤包括执行回蚀工艺,以及
所述多个初步导电互连图案是通过将所述导电材料层分隔开而形成的。
10.如权利要求1所述的方法,其中,去除所述填充层的顶部、所述初步导电互连图案的顶部和所述第二初步中间图案的顶部的步骤包括执行化学机械抛光工艺,以及
其中,所述中间图案、所述导电互连图案和所述填充图案中的每个的顶表面彼此共面。
11.如权利要求1所述的方法,还包括:
在所述第二初步中间图案与所述导电材料层之间形成阻挡材料层;以及
在形成所述初步导电互连图案之后,通过将所述阻挡材料层图案化而形成物理上分隔开的多个阻挡图案。
12.一种用于制造半导体器件的方法,包括:
在衬底之上形成下层间电介质层;
在所述下层间电介质层之上形成阻止层;
在所述阻止层之上形成第一初步中间图案,以在所述第一初步中间图案之间形成第一沟槽空隙;
通过使所述第一初步中间图案收缩而扩宽所述第一沟槽空隙来被形成为第二沟槽空隙,以形成第二初步中间图案,每个所述第二沟槽空隙的水平宽度大于每个所述第一沟槽空隙的水平宽度;
形成初步导电互连图案,所述初步导电互连图案覆盖所述第二初步中间图案的顶表面和两个侧表面;
在所述初步导电互连图案之间形成填充层;
通过去除所述填充层、所述初步导电互连图案和所述第二初步中间图案中的每个的顶部,形成具有侧表面的中间图案、在所述中间图案的所述侧表面上的导电互连图案以及在所述导电互连图案之间的填充图案;
在所述中间图案、所述导电互连图案和所述填充图案之上形成覆盖层;以及
在所述覆盖层之上形成上层间电介质层,
其中,形成所述第二初步中间图案的步骤包括:通过对所述第一初步中间图案执行各向同性刻蚀工艺而部分地去除所述第一初步中间图案的顶部的一部分和两侧各自的一部分,
其中,所述第一初步中间图案的顶表面被降低成为所述多个第二初步中间图案的顶表面。
13.如权利要求12所述的方法,其中,形成所述初步导电互连图案的步骤包括:
在所述阻止层之上形成导电材料层,所述导电材料层覆盖所述第二初步中间图案的顶表面和侧表面;以及
通过执行回蚀工艺而将所述导电材料层分隔成所述初步导电互连图案。
14.如权利要求12所述的方法,其中,所述填充图案、所述导电互连图案和所述中间图案的顶表面彼此共面。
15.如权利要求12所述的方法,其中,所述导电互连图案包括形成在所述中间图案的左侧的左导电互连图案和形成在所述中间图案的右侧的右导电互连图案,
其中,所述左导电互连图案中的每个包括平坦的右侧表面和弧形的左侧表面,以及
所述右导电互连图案中的每个包括平坦的左侧表面和弧形的右侧表面。
16.如权利要求15所述的方法,其中,所述中间图案中的每个包括两个平坦的侧表面,以及
所述填充图案中的每个包括两个弧形以具有反斜面的侧表面,使得底部窄而顶部宽。
17.如权利要求15所述的方法,每个左导电互连图案的水平宽度与每个中间图案的水平宽度之和等于每个第一初步中间图案的水平宽度。
18.如权利要求15所述的方法,其中,每个右导电互连图案的水平宽度与每个中间图案的水平宽度之和等于每个第一初步中间图案的水平宽度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2018-0085972 | 2018-07-24 | ||
KR1020180085972A KR20200011174A (ko) | 2018-07-24 | 2018-07-24 | 대칭형 구조를 갖는 전도성 패턴들을 갖는 반도체 소자 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110783257A CN110783257A (zh) | 2020-02-11 |
CN110783257B true CN110783257B (zh) | 2023-11-17 |
Family
ID=69178619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910385004.9A Active CN110783257B (zh) | 2018-07-24 | 2019-05-09 | 具有对称的导电互连图案的半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20200035601A1 (zh) |
KR (1) | KR20200011174A (zh) |
CN (1) | CN110783257B (zh) |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6476496B1 (en) * | 1999-06-28 | 2002-11-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
CN1649126A (zh) * | 2004-01-28 | 2005-08-03 | 三星电子株式会社 | 用于在半导体器件中形成互连线的方法及互连线结构 |
CN1674251A (zh) * | 2004-01-12 | 2005-09-28 | 三星电子株式会社 | 半导体器件的制造方法及由此制造的半导体器件 |
US7052932B2 (en) * | 2004-02-24 | 2006-05-30 | Chartered Semiconductor Manufacturing Ltd. | Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication |
KR20090074331A (ko) * | 2008-01-02 | 2009-07-07 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR20100081019A (ko) * | 2009-01-05 | 2010-07-14 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
CN103515193A (zh) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件精细图案的制作方法 |
JP2015138914A (ja) * | 2014-01-23 | 2015-07-30 | マイクロン テクノロジー, インク. | 半導体装置の製造方法 |
TW201545204A (zh) * | 2014-02-23 | 2015-12-01 | Tokyo Electron Ltd | 藉由交叉多重圖案化層以增加圖案密度的方法 |
KR20160084248A (ko) * | 2015-01-05 | 2016-07-13 | 에스케이하이닉스 주식회사 | 미세 패턴의 형성방법 |
WO2018111289A1 (en) * | 2016-12-16 | 2018-06-21 | Intel Corporation | Interconnects provided by subtractive metal spacer based deposition |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5994779A (en) | 1997-05-02 | 1999-11-30 | Advanced Micro Devices, Inc. | Semiconductor fabrication employing a spacer metallization technique |
US6140217A (en) | 1998-07-16 | 2000-10-31 | International Business Machines Corporation | Technique for extending the limits of photolithography |
US7799638B2 (en) * | 2008-10-31 | 2010-09-21 | Macronix International Co., Ltd | Method for forming a memory array |
US8836005B2 (en) | 2008-10-31 | 2014-09-16 | Macronix International Co., Ltd. | Memory array |
US8492282B2 (en) * | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
KR101573464B1 (ko) | 2009-07-28 | 2015-12-02 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
KR101756226B1 (ko) | 2010-09-01 | 2017-07-11 | 삼성전자 주식회사 | 반도체 소자 및 그 반도체 소자의 패턴 형성방법 |
US8778794B1 (en) * | 2012-12-21 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnection wires of semiconductor devices |
US9558999B2 (en) | 2013-09-12 | 2017-01-31 | Globalfoundries Inc. | Ultra-thin metal wires formed through selective deposition |
KR102486400B1 (ko) * | 2014-01-13 | 2023-01-09 | 어플라이드 머티어리얼스, 인코포레이티드 | 공간적인 원자 층 증착에 의한 자기-정렬 이중 패터닝 |
US9293343B2 (en) * | 2014-07-02 | 2016-03-22 | Samsung Electronics Co., Ltd. | Method of forming patterns of semiconductor device |
US10128188B2 (en) | 2016-03-28 | 2018-11-13 | International Business Machines Corporation | High aspect ratio contact metallization without seams |
WO2018125111A1 (en) | 2016-12-29 | 2018-07-05 | Intel Corporation | Self-aligned via |
WO2018125247A1 (en) | 2016-12-31 | 2018-07-05 | Intel Corporation | Hardened plug for improved shorting margin |
-
2018
- 2018-07-24 KR KR1020180085972A patent/KR20200011174A/ko not_active Application Discontinuation
-
2019
- 2019-03-19 US US16/358,661 patent/US20200035601A1/en not_active Abandoned
- 2019-05-09 CN CN201910385004.9A patent/CN110783257B/zh active Active
-
2021
- 2021-03-02 US US17/189,839 patent/US11456252B2/en active Active
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6476496B1 (en) * | 1999-06-28 | 2002-11-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
CN1674251A (zh) * | 2004-01-12 | 2005-09-28 | 三星电子株式会社 | 半导体器件的制造方法及由此制造的半导体器件 |
CN1649126A (zh) * | 2004-01-28 | 2005-08-03 | 三星电子株式会社 | 用于在半导体器件中形成互连线的方法及互连线结构 |
US7052932B2 (en) * | 2004-02-24 | 2006-05-30 | Chartered Semiconductor Manufacturing Ltd. | Oxygen doped SiC for Cu barrier and etch stop layer in dual damascene fabrication |
KR20090074331A (ko) * | 2008-01-02 | 2009-07-07 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR20100081019A (ko) * | 2009-01-05 | 2010-07-14 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
CN103515193A (zh) * | 2012-06-28 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件精细图案的制作方法 |
JP2015138914A (ja) * | 2014-01-23 | 2015-07-30 | マイクロン テクノロジー, インク. | 半導体装置の製造方法 |
TW201545204A (zh) * | 2014-02-23 | 2015-12-01 | Tokyo Electron Ltd | 藉由交叉多重圖案化層以增加圖案密度的方法 |
KR20160084248A (ko) * | 2015-01-05 | 2016-07-13 | 에스케이하이닉스 주식회사 | 미세 패턴의 형성방법 |
WO2018111289A1 (en) * | 2016-12-16 | 2018-06-21 | Intel Corporation | Interconnects provided by subtractive metal spacer based deposition |
Also Published As
Publication number | Publication date |
---|---|
US20200035601A1 (en) | 2020-01-30 |
US11456252B2 (en) | 2022-09-27 |
CN110783257A (zh) | 2020-02-11 |
US20210183769A1 (en) | 2021-06-17 |
KR20200011174A (ko) | 2020-02-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10347729B2 (en) | Device for improving performance through gate cut last process | |
US10002784B2 (en) | Via corner engineering in trench-first dual damascene process | |
CN109326521B (zh) | 多重图案化方法 | |
KR101486134B1 (ko) | 멀티 레벨 상호접속을 갖는 반도체 장치 및 멀티 레벨 상호접속을 갖는 반도체 장치를 형성하는 방법 | |
TW201810591A (zh) | 半導體裝置與其形成方法 | |
US8962432B2 (en) | Semiconductor device with self aligned end-to-end conductive line structure and method for forming the same | |
CN108122886B (zh) | 集成电路二维形成互连及形成半导体结构的方法及其装置 | |
US20130285246A1 (en) | Semiconductor Device With Self-Aligned Interconnects and Blocking Portions | |
US10651076B2 (en) | Method for defining patterns for conductive paths in dielectric layer | |
US10593549B2 (en) | Method for defining patterns for conductive paths in a dielectric layer | |
US9728456B2 (en) | Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer | |
KR102014197B1 (ko) | 반도체 장치 및 이의 형성 방법 | |
JP4615846B2 (ja) | 半導体装置 | |
CN110783257B (zh) | 具有对称的导电互连图案的半导体器件 | |
CN112750773B (zh) | 生产接触晶体管的栅极和源极/漏极通孔连接的方法 | |
US10395978B2 (en) | Method of patterning target layer | |
US11710637B2 (en) | Patterning method | |
US20240071906A1 (en) | Semiconductor structure and manufacturing method thereof | |
CN111480224B (zh) | 半导体产品和制造工艺 | |
KR20050046428A (ko) | 듀얼 다마신 공정을 이용한 반도체 소자의 형성 방법 | |
KR20230042963A (ko) | 카본 함유의 콘택-펜스를 포함한 반도체 소자 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |