CN110770160B - Flow passage structure device and manufacturing method thereof - Google Patents

Flow passage structure device and manufacturing method thereof Download PDF

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Publication number
CN110770160B
CN110770160B CN201780090943.XA CN201780090943A CN110770160B CN 110770160 B CN110770160 B CN 110770160B CN 201780090943 A CN201780090943 A CN 201780090943A CN 110770160 B CN110770160 B CN 110770160B
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layer
flow channel
substrate
material layer
sacrificial
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CN110770160A (en
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云全新
林建勋
董龙涛
汪天书
朱国丽
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BGI Shenzhen Co Ltd
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BGI Shenzhen Co Ltd
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    • B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01L—CHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
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    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate

Abstract

A flow channel structure device and method of making the same, the method comprising: providing a substrate (21) comprising a first portion (211) and a second portion (212) adjoining the first portion (211); forming a patterned first sacrificial layer (31) on the substrate (21), the first sacrificial layer (31) covering the second portion (212) and exposing the first portion (211); forming a first structural layer (41) on a first portion (211) of a substrate (21) and a first sacrificial layer (31); performing a first polishing process to expose the first sacrificial layer (31); removing the first sacrificial layer (31) to expose an upper surface of the second portion (212) of the substrate (21) and a side surface of the first structural layer (41); forming a second sacrificial layer (32) on a part of the upper surface of the second portion (212) of the substrate (21), wherein the second sacrificial layer (32) covers a side of the first structural layer (41); forming a second structural layer (42) on the second portion (212) of the substrate (21), the second sacrificial layer (32) and the first structural layer (41); performing a second polishing process to expose a second sacrificial layer (32); and removing the second sacrificial layer (32) by using a selective etching process to form a flow channel (50); the method can realize the flow channel structure device with the vertical flow channel.

Description

Flow channel structure device and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a flow channel structure device and a manufacturing method thereof.
Background
The micro-nanofluidic analysis technology based on micro-nanofluidic channels is increasingly researched and applied in the fields of biochemical analysis, gene sequencing and the like. The combination of the micro-nano flow channel device and an Integrated Circuit (IC for short) is also helpful to promote the automation and miniaturization of a micro-analysis system and better expand the application space of the micro-analysis system. In some applications, it is necessary to embed electrode materials in the micro-nano flow channel, and in some designs, it is necessary to have a nano flow channel with a high aspect ratio.
In the traditional method, electron beam lithography or laser lithography can be adopted, and an anisotropic etching process is combined to realize the nano flow channel. However, the direct electron beam or laser lithography method has low efficiency and poor size adjustability, and it is difficult to achieve high aspect ratios, usually only about 1, on metal materials.
In the prior art, the micro-nano flow channel structure can also be realized by a side wall method. However, the sidewall method must rely on a semiconductor material sidewall support structure to realize structural interconnection and signal extraction, which may cause more parasitic effects and may finally affect the quality of a detection signal, and the process thermal budget is high, which is not favorable for integration with a CMOS chip. For example, most prior art electrode leads require the formation of alloy structures with electrode materials relying on spliced metal interconnect lines (e.g., aluminum and copper are typical materials) or semiconductor interconnect lines (e.g., polysilicon is a typical material). However, the alloy structure has the following disadvantages: (1) The alloying process requires an additional thermal treatment process, which increases the thermal budget of the process, and is not favorable for implementing process integration on an IC chip, and for example, a typical polysilicon interconnection process requires a high thermal budget process technology such as a polysilicon deposition process (temperature usually higher than 600 ℃), ion implantation and activation (usually higher than 550 ℃), and a metal semiconductor alloy (usually higher than 400 ℃); (2) The alloy body will introduce additional contact resistance which will degrade device performance. In addition, there is a lateral flow channel structure of metal leads in the prior art, but in such a lateral flow channel structure, the metal electrodes are respectively distributed on the upper and lower sides of the flow channel, which may affect the application range, for example, it cannot be used for applications including light emission, because the light signal will be blocked by the upper and lower electrodes. Moreover, such lateral flow channel structures also limit the fabrication density on the chip.
In the prior art, the nanometer gap structure can be realized by adjusting the metal sputtering angle. In the sputtering process, a certain angle exists between the sputtering direction of particles and the surface of a substrate, and the bottom of a groove prepared in advance can generate a sputtering dead angle by adjusting the angle, so that a nanogap flow channel structure is obtained, but the process controllability and the size adjustability are poor.
Disclosure of Invention
The inventors of the present invention have found that there are problems in the above-mentioned prior art, and thus have proposed a new technical solution to at least one of the problems.
According to a first aspect of the present invention, there is provided a method of manufacturing a flow channel structure device, comprising: providing a substrate comprising a first portion and a second portion contiguous with the first portion; forming a patterned first sacrificial layer on the substrate, the first sacrificial layer covering the second portion and exposing the first portion; forming a first structural layer on a first portion of the substrate and the first sacrificial layer; after forming the first structural layer, performing a first polishing process to expose the first sacrificial layer; removing the first sacrificial layer to expose an upper surface of the second portion of the substrate and a side surface of the first structural layer; forming a second sacrificial layer on a portion of an upper surface of a second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer; forming a second structural layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer; after forming the second structural layer, performing a second polishing process to expose the second sacrificial layer; and removing the second sacrificial layer by using a selective etching process to form a flow channel.
In one embodiment, in the step of performing the second polishing process, the first structural layer and the second structural layer are also exposed; before removing the second sacrificial layer using a selective etch process, the method further comprises: forming a cap layer on the second sacrificial layer, the first structural layer and the second structural layer.
In one embodiment, the step of forming a first structural layer comprises: forming a first material layer on a first portion of the substrate and the first sacrificial layer, wherein the first material layer covers a side of the first sacrificial layer; and forming a first support layer on the first material layer; wherein the first structural layer comprises: the first material layer and the first support layer; the step of forming a second structural layer comprises: forming a second material layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer, the second material layer covering a side of the second sacrificial layer; and forming a second support layer on the second material layer; wherein the second structural layer comprises: the second material layer and the second support layer.
In one embodiment, in the step of removing the first sacrificial layer to expose the side surface of the first structural layer, the exposed side surface of the first structural layer is a side surface of the first material layer; in the step of forming a second sacrificial layer, the second sacrificial layer covers the exposed side surface of the first material layer.
In one embodiment, in the step of performing the second polishing process, the first material layer, the first support layer, the second material layer, and the second support layer are also exposed; before removing the second sacrificial layer using a selective etch process, the method further comprises: forming a cap layer on the second sacrificial layer, the first material layer, the first support layer, the second material layer, and the second support layer.
In one embodiment, the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
In one embodiment, in the step of removing the second sacrificial layer by using a selective etching process, a selective etching liquid is injected from an edge of the second sacrificial layer to remove the second sacrificial layer.
In one embodiment, before removing the second sacrificial layer using a selective etching process, the method further comprises: etching the cap layer to form a through hole which penetrates through the cap layer and exposes the second sacrificial layer; and injecting selective etching liquid from the through hole to remove the second sacrificial layer in the step of removing the second sacrificial layer by using a selective etching process.
In one embodiment, a portion of the first layer of material is between the first support layer and the flow channel and another portion of the first layer of material is between the first support layer and the first portion of the substrate; a portion of the second material layer is between the second support layer and the flow channel and another portion of the second material layer is between the second support layer and a second portion of the substrate.
In one embodiment, the material of the first material layer includes: a metallic material or a semiconductor material; the material of the second material layer comprises: a metal material or a semiconductor material; wherein a portion of the first material layer between the first support layer and the flow channel serves as a first electrode of the flow channel structure device; a portion of the first material layer between the first support layer and the first portion of the substrate serves as a first lead of the first electrode; the part of the second material layer between the second support layer and the flow channel is used as a second electrode of the flow channel structure device; a portion of the second material layer between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
In one embodiment, the material of the first material layer and the material of the second material layer respectively comprise: an insulating dielectric material.
In one embodiment, the thickness of the first sacrificial layer is determined according to the height of a required flow channel; the thickness of the first sacrificial layer ranges from 100 nanometers to 100 micrometers.
In one embodiment, the thickness of the second sacrificial layer is determined according to the width of a required flow channel; the thickness of the second sacrificial layer ranges from 0.1 nanometers to 1 micrometer.
In one embodiment, the first material layer has a thickness in a range of 1 to 500 nanometers; the thickness of the first support layer ranges from 100 nanometers to 100 micrometers; the thickness of the second material layer ranges from 1 nanometer to 500 nanometers; the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.
In the above manufacturing method, a patterned first sacrificial layer is formed on a substrate; forming a first structural layer on the first portion of the substrate and the first sacrificial layer; performing a first polishing process to expose the first sacrificial layer; removing the first sacrificial layer to expose the upper surface of the second portion of the substrate and the side surfaces of the first structural layer; forming a second sacrificial layer on a portion of an upper surface of the second portion of the substrate; forming a second structural layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer; after forming the second structural layer, performing a second polishing process to expose the second sacrificial layer; and removing the second sacrificial layer by using a selective etching process to form a flow channel. The manufacturing method can form the flow channel structure device with the vertical flow channel, and the manufacturing method can reduce the process thermal budget and is convenient for the integration of the flow channel structure device and the CMOS chip.
Further, in the manufacturing method, since the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, a high aspect ratio flow channel structure can be realized.
Further, in the case where the first material layer and the second material layer are made of a conductive material such as a metal or a semiconductor, the first material layer may include the first electrode and the first lead, and the second material layer may include the second electrode and the second lead, and since the first material layer and the second material layer are integrally formed, compared with the prior art, the contact resistance between the first electrode and the first lead and the contact resistance between the second electrode and the second lead may be reduced, so that the device performance may be improved.
According to a second aspect of the present invention, there is provided a flow channel structure device comprising: a substrate comprising a first portion and a second portion contiguous with the first portion; a first structural layer and a second structural layer on the substrate; wherein the first structural layer comprises: a first layer of material on a first portion of the substrate and a first support layer on the first layer of material, the second structural layer comprising: a second material layer on a second portion of the substrate and a second support layer on the second material layer; a flow channel between the first material layer and the second material layer; the first supporting layer and the second supporting layer are respectively arranged on two sides of the flow channel; wherein a portion of the first material layer is between the first support layer and the flow channel and another portion of the first material layer is between the first support layer and the first portion of the substrate; a portion of the second layer of material is between the second support layer and the flow channel and another portion of the second layer of material is between the second support layer and the second portion of the substrate.
In one embodiment, the flow channel structure device further comprises: a capping layer overlying the first material layer, the first support layer, the second material layer, and the second support layer; wherein the cap layer covers the flow channel.
In one embodiment, the material of the cap layer comprises: an insulating dielectric material or a semiconductor material; the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
In one embodiment, the flow channel structure device further comprises: and the through hole penetrates through the cap layer and is communicated with the flow channel.
In one embodiment, the material of the first material layer comprises: a metallic material or a semiconductor material; the material of the second material layer comprises: a metallic material or a semiconductor material; wherein a portion of the first material layer between the first support layer and the flow channel serves as a first electrode of the flow channel structure device; a portion of the first material layer between the first support layer and the first portion of the substrate serves as a first lead of the first electrode; the part of the second material layer between the second support layer and the flow channel is used as a second electrode of the flow channel structure device; a portion of the second material layer between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
In one embodiment, the material of the first material layer and the material of the second material layer respectively comprise: an insulating dielectric material.
In one embodiment, the height of the flow channel ranges from 100 nanometers to 100 micrometers; the width of the flow channel ranges from 0.1 nanometer to 1 micrometer.
In one embodiment, the first material layer has a thickness in a range of 1 to 500 nanometers; the thickness of the first support layer ranges from 100 nanometers to 100 micrometers; the thickness of the second material layer ranges from 1 nanometer to 500 nanometers; the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.
The flow channel structure device of the above embodiment of the present invention has a vertical flow channel, which can improve the manufacturing density of the flow channel on the chip, reduce the manufacturing and application costs, and the like.
Further, the flow channel structure device can realize a flow channel structure with a high depth-to-width ratio.
Further, in the case that the first material layer and the second material layer are made of a conductive material such as a metal or a semiconductor, the first material layer may include the first electrode and the first lead, and the second material layer may include the second electrode and the second lead.
According to a third aspect of the present invention, there is provided a flow channel sensor comprising: a flow channel structure device as hereinbefore described.
According to a fourth aspect of the present invention, there is provided a biochemical analysis apparatus comprising: a flow channel structure device as hereinbefore described.
According to a fifth aspect of the present invention, there is provided a chip for molecular detection, comprising: the flow channel structure device, the signal collecting unit and the signal processing unit are as described above; the method comprises the following steps that a sample to be detected is added into a flow channel of a flow channel structure device, and under the condition that an electrode of the flow channel structure device is subjected to electric excitation, a target molecule in the sample to be detected generates an electric signal or an optical signal under the action of electric excitation; the signal collecting unit is used for collecting the electric signal or the optical signal and transmitting the electric signal or the optical signal to the signal processing unit; the signal processing unit is used for carrying out signal processing on the electric signal or the optical signal to identify the information of the target molecule.
According to a sixth aspect of the present invention, there is provided a molecular detection method comprising: molecular detection was performed using the chip as described previously.
In one embodiment, the step of performing molecular detection using the chip comprises: processing a sample to be detected; adding the sample to be detected into the chip; applying electric excitation to electrodes in a flow channel structure device in the chip so that target molecules in the sample to be detected generate electric signals or optical signals under the action of the electric excitation; and the signal processing unit of the chip acquires the electric signal or the optical signal through the signal collecting unit, and performs signal processing on the electric signal or the optical signal to identify the information of the target molecule.
In the above embodiments, the application of molecular detection is realized by using a chip including the flow channel structure device of the embodiments of the present invention.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a flowchart illustrating a method of manufacturing a flow channel structure device according to an embodiment of the present invention.
Fig. 2 to 10 are cross-sectional views schematically showing the structure at several stages in the manufacturing process of a flow channel structure device according to an embodiment of the present invention.
Fig. 11 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 12 is a top view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the invention.
Fig. 13 is a cross-sectional view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 14 to 22 are cross-sectional views schematically showing the structure at several stages in the fabrication of a flow channel structure device according to another embodiment of the present invention.
Fig. 23 is a cross-sectional view schematically illustrating a structure at a stage in the manufacturing process of a flow channel structure device according to another embodiment of the present invention.
Fig. 24 is a cross-sectional view schematically illustrating the structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention.
FIG. 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention.
FIG. 26 is a flow chart illustrating a method of molecular detection according to one embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a flowchart illustrating a method of manufacturing a flow channel structure device according to an embodiment of the present invention. Fig. 2 to 10 are cross-sectional views schematically showing the structure at several stages in the manufacturing process of a flow channel structure device according to an embodiment of the present invention. A process of manufacturing a flow channel structure device according to an embodiment of the present invention is described in detail below with reference to fig. 1 and fig. 2 to 10.
As shown in fig. 1, in step S101, a substrate is provided, the substrate including a first portion and a second portion adjoining the first portion.
Fig. 2 is a cross-sectional view schematically showing the structure at step S101 in the manufacturing process of a flow channel structure device according to an embodiment of the present invention. As shown in fig. 2, a substrate 21 is provided, and the substrate 21 may include a first portion 211 and a second portion 212 adjacent to the first portion 211. For example, the substrate may include: a semiconductor substrate (e.g., silicon, germanium, etc.), an insulating substrate (e.g., quartz, silicon nitride, etc.), a wafer on which IC circuitry has been integrated, or any combination of these substrates.
Note that the broken line in fig. 2 is merely for convenience of illustrating the first portion and the second portion, and the line does not necessarily exist in reality, and the following drawings are similar.
Returning to fig. 1, in step S102, a patterned first sacrificial layer is formed on the substrate, covering the second portion and exposing the first portion.
Fig. 3 is a cross-sectional view schematically showing the structure at step S102 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 3, a patterned first sacrificial layer 31 is formed on the substrate 21, the first sacrificial layer 31 covering the second portion 212 and exposing the first portion 211. The first sacrificial layer may serve as a definition layer of the flow channel location. The thickness of the first sacrificial layer may be determined according to the height of the flow channel required. In one embodiment, the thickness of the first sacrificial layer may range from 100 nm to 100 μm. For example, the thickness of the first sacrificial layer may be 500 nanometers, 1 micron, 10 microns, 50 microns, or the like. In one embodiment, the material of the first sacrificial layer may include: a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or combinations of multiple semiconductor materials), an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations of multiple insulating dielectric materials), or a metal material (e.g., aluminum, copper, etc., or combinations of multiple metal materials).
Optionally, the step S102 may include: a first sacrificial layer is formed over the substrate, the first sacrificial layer covering the first and second portions of the substrate. Optionally, the step S102 may further include: the first sacrificial layer is patterned using a photolithography method, thereby removing a portion of the first sacrificial layer overlying the first portion to expose the first portion. For example, the photolithography method may include pattern exposure, pattern development, pattern etching, and the like. For example, the method of pattern exposure may include: optical exposure, electron beam exposure, or nanoimprint, and the like. For example, the method for pattern etching may include: wet etching or dry etching, etc.
Returning to fig. 1, in step S103, a first structural layer is formed on the first portion of the substrate and the first sacrificial layer.
Fig. 4 is a cross-sectional view schematically showing the structure at step S103 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 4, a first structural layer 41 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31, for example, by a deposition process. The first structural layer 41 covers the side surface of the first sacrificial layer 31. Preferably, the thickness of the first structural layer is greater than or equal to that of the first sacrificial layer, so that during the subsequent first polishing treatment, the part of the first sacrificial layer can be polished and removed as little as possible, which is beneficial to controlling the height of the subsequently obtained flow channel. Of course, the scope of the present invention is not limited thereto, and the thickness of the first structure layer may be smaller than that of the first sacrificial layer.
In one embodiment, the material of the first structural layer may include: a metal material (e.g., gold, platinum, silver, titanium nitride, etc., or a combination of multiple metal materials), a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), or an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials).
Returning to fig. 1, in step S104, after the first structural layer is formed, a first polishing process is performed to expose the first sacrificial layer.
Fig. 5 is a cross-sectional view schematically showing the structure at step S104 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 5, for example, a first Polishing process (e.g., CMP (Chemical Mechanical Polishing)) is performed on the semiconductor structure shown in fig. 4, thereby exposing the top surface of the first sacrificial layer 31. The polishing process may remove portions of the first structural layer that are located on the top surface of the first sacrificial layer.
Returning to fig. 1, in step S105, the first sacrificial layer is removed to expose the upper surface of the second portion of the substrate and the side surface of the first structural layer.
Fig. 6 is a cross-sectional view schematically showing the structure at step S105 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 6, first sacrificial layer 31 is removed, for example by a selective etching process, so as to expose the upper surface of second portion 212 of substrate 21 and the side surfaces of first structural layer 41. For example, the selective etching process may include: dry etching or wet etching, etc.
Returning to fig. 1, in step S106, a second sacrificial layer is formed on a portion of the upper surface of the second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer.
Fig. 7 is a cross-sectional view schematically showing the structure at step S106 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 7, a second sacrificial layer 32 is formed on a portion of the upper surface of the second portion 212 of the substrate 21 with the first structural layer 41 as a support, wherein the second sacrificial layer 32 covers the exposed side surface of the first structural layer 41. For example, the step S106 may include: depositing a second sacrificial layer over the semiconductor structure shown in FIG. 6; an etch back is then performed on the second sacrificial layer to form the structure shown in figure 7. The thickness of the second sacrificial layer may be determined according to the width of a desired flow channel. In one embodiment, the thickness of the second sacrificial layer may range from 0.1 nm to 1 μm. For example, the thickness of the second sacrificial layer may be 1 nm, 10nm, 100 nm, 500 nm, or the like.
In one embodiment, the material of the second sacrificial layer may include: a metal material (e.g., chromium, aluminum, titanium, etc., or a combination of multiple metal materials), a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), or an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials).
Returning to fig. 1, in step S107, a second structural layer is formed on the second portion of the substrate, the second sacrificial layer, and the first structural layer.
Fig. 8 is a cross-sectional view schematically showing the structure at step S107 in the manufacturing process of a flow channel structure device according to an embodiment of the present invention. As shown in fig. 8, a second structural layer 42 is formed on the second portion 212 of the substrate 21, the second sacrificial layer 32 and the first structural layer 41, for example by a deposition process. Preferably, the thickness of the second structure layer is greater than or equal to the height of the second sacrificial layer, so that in the process of performing the second polishing treatment subsequently, the part of the second sacrificial layer can be polished and removed as little as possible, which is beneficial to controlling the height of the subsequently obtained flow channel. Of course, the scope of the present invention is not limited thereto, and the thickness of the second structural layer may be smaller than the height of the second sacrificial layer.
In one embodiment, the material of the second structural layer may include: a metal material (e.g., gold, platinum, silver, titanium nitride, etc., or a combination of multiple metal materials), a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), or an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials).
Returning to fig. 1, in step S108, after the second structural layer is formed, a second polishing process is performed to expose the second sacrificial layer.
Fig. 9 is a cross-sectional view schematically showing the structure at step S108 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 9, a second polishing process (e.g., CMP) is performed on the semiconductor structure shown in fig. 8, for example, to expose the top surface of the second sacrificial layer 32. In this step of performing the second polishing process, the first structural layer 41 and the second structural layer 42 may also be exposed, for example, a top surface of the first structural layer 41 and a top surface of the second structural layer 42 are exposed. The second polishing process may remove portions of the second structural layer located on the top surfaces of the first structural layer and the second sacrificial layer.
Returning to fig. 1, in step S109, the second sacrificial layer is removed by using a selective etching process to form a flow channel.
Fig. 10 is a cross-sectional view schematically showing the structure at step S109 in the manufacturing process of the flow channel structure device according to one embodiment of the present invention. As shown in fig. 10, the second sacrificial layer 32 is removed using a selective etching process to form a flow channel 50. In one embodiment, the height of the flow channel may range from 100 nm to 100 μm. In one embodiment, the width of the flow channel may range from 0.1 nm to 1 μm.
Thus, a method of manufacturing a flow channel structure device according to an embodiment of the present invention is provided. In the manufacturing method, a patterned first sacrificial layer is formed on a substrate; forming a first structural layer on the first portion of the substrate and the first sacrificial layer; performing a first polishing process to expose the first sacrificial layer; removing the first sacrificial layer to expose the upper surface of the second portion of the substrate and the side surfaces of the first structural layer; forming a second sacrificial layer on a portion of an upper surface of the second portion of the substrate; forming a second structural layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer; after forming the second structural layer, performing a second polishing process to expose the second sacrificial layer; and removing the second sacrificial layer by using a selective etching process to form a flow channel. By the above manufacturing method, a flow channel structure device having a vertical flow channel (i.e., the flow channel is perpendicular to the surface of the substrate) can be formed. For example, the flow channel may be open space in a direction perpendicular to the substrate or may be provided with a transparent material, so that this does not affect the transmission of the optical signal. In addition, the vertical flow channel is adopted, so that the effective surface area of a single flow channel is the sectional area of the flow channel, the manufacturing density of the flow channel on the chip can be greatly improved, the manufacturing and application cost is reduced, and the like.
The manufacturing method of the embodiment of the invention can reduce the process thermal budget. For example, the method of the present invention involves a relatively low process temperature (ranging from room temperature to 350 ℃) and a short thermal processing time, thereby reducing the process thermal budget to facilitate the integration of the runner structure device with the CMOS chip.
Further, in the manufacturing method, since the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, a high aspect ratio flow channel structure can be realized. For example, a width of 10nm and an aspect ratio of 100:1, flow channel structure. The aspect ratio of the flow channel structure realized by the method of the embodiment of the invention can range from 1.
Through the manufacturing method, the flow channel structure device is formed. The flow channel structure device includes: the structure includes a substrate, a first structural layer and a second structural layer on the substrate, and a flow channel between the first structural layer and the second structural layer. In the case where the first structural layer and the second structural layer are respectively insulating dielectric materials, an insulating dielectric flow channel structure device can be formed, which can be applied to fluid formation and control, and the like. In case the first structural layer and the second structural layer are each an electrically conductive material, such as a metallic material or a semiconducting material (e.g. a doped semiconducting material), it may serve as an electrode on both sides of the flow channel, which may be used for fluid processing, biochemical detection, etc.
Fig. 11 and 13 are cross-sectional views schematically illustrating structures at several stages in the fabrication of a flow channel structure device according to another embodiment of the present invention. Fig. 12 is a top view schematically illustrating a structure at a stage in the fabrication of a flow channel structure device according to another embodiment of the present invention. The following describes in detail the manufacturing process of the flow channel structure device according to other embodiments of the present invention with reference to fig. 11 to 13.
In an embodiment of the present invention, before removing the second sacrificial layer by using the selective etching process, the manufacturing method may further include: as shown in fig. 11, a cap layer 60 is formed on the second sacrificial layer 32, the first structural layer 41, and the second structural layer 42. In the subsequent step of forming the flow channel, the cap layer 60 may implement a closed flow channel together with the first structural layer 41 and the second structural layer 42 (i.e., the top of the flow channel is closed), and may also avoid a parasitic reaction that may be caused by the contact between the upper surfaces of the first structural layer 41 and the second structural layer 42 and the fluid. In addition, for some applications where fluids (e.g., liquids) are required to flow in the flow channels, the capped flow channels of this embodiment are easier to control. In one embodiment, the material of the cap layer 60 may include: an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide, tantalum oxide, or the like) or a semiconductor material (e.g., polysilicon, amorphous silicon, or the like). In one embodiment, the cap layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers. For example, the cap layer may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micron, 5 microns, or the like.
In one embodiment, in the step of removing the second sacrificial layer by using a selective etching process, a selective etching liquid may be injected from an edge of the second sacrificial layer to remove the second sacrificial layer, thereby forming the flow channel structure device as shown in fig. 13. In a substantially planar structure, the second sacrificial layer, which extends in a plane, is bordered, and the edges of the second sacrificial layer may be exposed, so that a selective etching liquid is injected at the edges (i.e. at the borders) of the second sacrificial layer to remove the second sacrificial layer, thereby forming flow channels.
In another embodiment, before removing the second sacrificial layer using the selective etching process, the manufacturing method may further include: as shown in fig. 12, the cap layer 60 is etched to form a via hole 61 penetrating the cap layer and exposing the second sacrificial layer. In the step of removing the second sacrificial layer by using the selective etching process, a selective etching solution may be injected from the through hole 61 to remove the second sacrificial layer, thereby forming the flow channel structure device shown in fig. 13. It should be understood by those skilled in the art that the number, shape, size, etc. of the through holes can be determined according to the design requirements, and the scope of the present invention is not limited to the number, shape, size, etc. of the through holes shown in fig. 12. In this embodiment, the etching rate can be increased by forming a via hole in the cap layer 60, thereby facilitating the selective etching solution to pass through the via hole to remove the second sacrificial layer in the selective etching process.
In the flow channel structure device shown in fig. 13, in addition to having the same or similar structure as fig. 10, the flow channel structure device further includes: a cap layer 60 on the first and second structural layers 41, 42, the cap layer 60 covering the flow channels. The cap layer 60 can realize a closed flow channel (i.e., the flow channel is closed above) together with the first structural layer 41 and the second structural layer 42, and can also avoid parasitic reactions that may be caused by the contact between the upper surfaces of the first structural layer 41 and the second structural layer 42 and the fluid. In addition, for some applications where fluid (e.g., liquid) flow is desired in the flow channels, the capped flow channels of this embodiment are easier to control. Optionally, the flow channel structure device may further include: and the through hole penetrates through the cap layer and is communicated with the flow channel.
In one embodiment, the step of forming the first structural layer may comprise: forming a first material layer on a first portion of a substrate and a first sacrificial layer, wherein the first material layer covers a side of the first sacrificial layer; and forming a first support layer on the first material layer. Wherein the first structural layer may include: the first material layer and the first support layer.
In another embodiment, the step of forming the second structural layer may include: forming a second material layer on the second portion of the substrate, the second sacrificial layer and the first structural layer, the second material layer covering a side surface of the second sacrificial layer; and forming a second support layer on the second material layer. Wherein the second structural layer may include: the second material layer and the second support layer.
Fig. 14 to 22 are cross-sectional views schematically showing structures at several stages in the manufacturing process of a flow channel structure device according to another embodiment of the present invention. Taking the first structure layer including the first material layer and the first support layer, and the second structure layer including the second material layer and the second support layer as an example, the following describes in detail a manufacturing process of a flow channel structure device according to another embodiment of the present invention with reference to fig. 14 to 22.
First, a substrate is provided that includes a first portion and a second portion adjacent to the first portion. This step has been described in detail above in connection with fig. 2 and will not be described again here.
Next, a patterned first sacrificial layer is formed on the substrate, covering the second portion and exposing the first portion. This step has been described in detail above in connection with fig. 3 and will not be described again here.
Next, as shown in fig. 14, a first material layer 411 is formed on the first portion 211 of the substrate 21 and the first sacrificial layer 31, for example, by a deposition process, wherein the first material layer 411 covers the side of the first sacrificial layer 31.
In one embodiment, the material of the first material layer 411 may include: a metallic material (e.g., gold, platinum, silver, titanium nitride, etc., or a combination of multiple metallic materials) or a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials). In this embodiment, the first material layer may be made of a conductive material such as a metal material or a semiconductor material (e.g., a doped semiconductor material), so that the first material layer may serve as one of the embedded electrode layers of the subsequently formed flow channel, and may be applied to processing of a fluid or biochemical detection, etc.
In another embodiment, the material of the first material layer 411 may include: an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, the like or combinations of multiple insulating dielectric materials). Therefore, the flow channel formed by the insulating medium material can be formed in the subsequent step, and the method can be applied to the formation and control of the fluid.
In one embodiment, the thickness of the first material layer 411 may range from 1 nm to 500 nm. For example, the thickness of the first material layer 411 may be 10nm, 50 nm, 100 nm, 300 nm, or the like.
Next, as shown in fig. 15, a first support layer 412 is formed on the first material layer 411, for example, by a deposition process. The first support layer 412 may serve as a support layer for the first material layer 411. At this point, the first structural layer 41 is formed. The first structural layer 41 may include: a first material layer 411 on the first portion 211 of the substrate 21 and the first sacrificial layer 31, and a first support layer 412 on the first material layer 411.
In one embodiment, the material of the first support layer 412 may include: a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials), or a conductive metal material (e.g., aluminum, copper, titanium nitride, etc., or a combination of multiple metal materials).
In one embodiment, the first support layer has a thickness in a range of 100 nm to 100 μm. For example, the thickness of the first support layer may be 200 nanometers, 500 nanometers, 1 micron, 10 microns, 50 microns, or the like.
Next, as shown in fig. 16, a first polishing process (e.g., CMP) is performed on the first structural layer 41 (i.e., the first support layer 412 and the first material layer 411) to expose the first sacrificial layer 31. The first polishing process may remove portions of the first support layer 412 and the first material layer 411 located on the top surface of the first sacrificial layer 31. Of course, a portion of the first sacrificial layer may be further polished.
Next, as shown in fig. 17, the first sacrificial layer 31 is removed, for example, by a selective etching process to expose the upper surface of the second portion 212 of the substrate 21 and the side surface of the first structural layer 41. In this step, as shown in fig. 17, the side surface of the first structure layer 41 that is exposed is the side surface of the first material layer 411.
Next, as shown in fig. 18, with the first support layer 412 and the first material layer 411 as supports, a second sacrificial layer 32 is formed on a part of the upper surface of the second portion 212 of the substrate 21, wherein the second sacrificial layer 32 covers the exposed side surface of the first structural layer 41. In this step, the second sacrificial layer 32 covers the exposed side of the first material layer 411.
Next, as shown in fig. 19, a second material layer 421 is formed on the second portion 212 of the substrate 21, the second sacrificial layer 32, and the first structural layer 41 (i.e., the first material layer 411 and the first support layer 412), for example, by a deposition process, the second material layer 421 covering the side of the second sacrificial layer 32.
In one embodiment, the material of the second material layer 421 may include: a metallic material (e.g., gold, platinum, silver, titanium nitride, etc., or a combination of multiple metallic materials) or a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials). In this embodiment, the second material layer may be made of a conductive material such as a metal material or a semiconductor material (e.g., a doped semiconductor material), so that the second material layer may serve as one of the embedded electrode layers of the subsequently formed flow channel, and may be applied to fluid processing or biochemical detection, etc.
In another embodiment, the material of the second material layer 421 may include: an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, the like or combinations of multiple insulating dielectric materials). Therefore, the flow channel formed by the insulating medium material can be formed in the subsequent step, and the method can be applied to fluid formation, control and the like.
In one embodiment, the thickness of the second material layer 421 can be in a range from 1 nm to 500 nm. For example, the thickness of the second material layer 421 can be 10nm, 50 nm, 100 nm, 300 nm, or the like.
Next, as shown in fig. 20, a second support layer 422 is formed on the second material layer 421, for example, by a deposition process. The second support layer 422 may serve as a support layer for the second material layer 421. To this end, the second structural layer 42 is formed. The second structural layer 42 may include: a second material layer 421 on the second portion 212 of the substrate 21, the second sacrificial layer 32 and the first structural layer 41 (i.e., the first material layer 411 and the first support layer 412), and a second support layer 422 on the second material layer 421.
In one embodiment, the material of the second support layer 422 may include: a semiconductor material (e.g., polysilicon, amorphous silicon, indium tin oxide, etc., or a combination of multiple semiconductor materials), an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials), or a conductive metal material (e.g., aluminum, copper, titanium nitride, etc., or a combination of multiple metal materials).
In one embodiment, the thickness of the second support layer 422 may range from 100 nanometers to 100 micrometers. For example, the thickness of the second support layer may be 200 nanometers, 500 nanometers, 1 micron, 10 microns, 50 microns, or the like.
Next, as shown in fig. 21, a second polishing process (e.g., CMP) is performed on the second structural layer 42 (i.e., the second support layer 422 and the second material layer 421) to expose the second sacrificial layer 32. In addition, the second polishing process may also remove portions of the second material layer 421 and the second support layer 422 on the top surface of the first support layer 412. As shown in fig. 21, in the step of performing the second polishing process, the first material layer 411, the first support layer 412, the second material layer 421, and the second support layer 422 are also exposed.
Next, as shown in fig. 22, the second sacrificial layer 32 is removed by using a selective etching process to form a flow channel 50.
Thus, a method of manufacturing a flow channel structure device according to another embodiment of the present invention is provided. In the flow channel structure device formed by the above manufacturing method, the first structure layer may include: a first material layer and a first support layer, wherein a portion of the first material layer is between the first support layer and the flow channel and another portion of the first material layer is between the first support layer and the first portion of the substrate; the second structural layer may include: a second material layer and a second support layer, wherein a portion of the second material layer is between the second support layer and the flow channel and another portion of the second material layer is between the second support layer and a second portion of the substrate.
In the case where the material of the first material layer includes a conductive material such as a metal material or a semiconductor material (e.g., a doped semiconductor material), a portion of the first material layer between the first support layer and the flow channel may serve as a first electrode of the flow channel structure device, and a portion of the first material layer between the first support layer and the first portion of the substrate may serve as a first lead of the first electrode. In the case that the material of the second material layer includes a conductive material such as a metal material or a semiconductor material (e.g., a doped semiconductor material), a portion of the second material layer between the second support layer and the flow channel may serve as a second electrode of the flow channel structure device, and a portion of the second material layer between the second support layer and the second portion of the substrate may serve as a second lead of the second electrode. Since the first material layer and the second material layer are respectively integrally formed by, for example, a deposition process, contact resistance between the first electrode and the first wiring and contact resistance between the second electrode and the second wiring can be reduced as compared with the prior art, and device performance can be improved.
In addition, the manufacturing method of the embodiment of the invention can reduce the process thermal budget. For example, the method of the present invention involves a relatively low process temperature (ranging from room temperature to 350 ℃) and a short thermal processing time, thereby reducing the process thermal budget to facilitate the integration of the runner structure device with the CMOS chip.
Further, in the manufacturing method, the thickness of the first sacrificial layer and the thickness of the second sacrificial layer can be determined according to design requirements, so that a high-aspect-ratio flow channel structure can be realized.
By the manufacturing method, the flow channel structure device is also formed. As shown in fig. 22, the flow channel structure device may include a substrate 21, and the substrate 21 may include a first portion 211 and a second portion 212 adjacent to the first portion 211. The flow channel structure device may further include: a first structural layer 41 and a second structural layer 42 on the substrate 21. Wherein the first structural layer 41 may include: a first material layer 411 on the first portion 211 of the substrate 21 and a first support layer 412 on the first material layer 411, the second structural layer 42 may include: a second material layer 421 on the second portion 212 of the substrate 21 and a second support layer 422 on the second material layer 421. The flow channel structure device may further include: a flow channel 50 between the first material layer 411 and the second material layer 421. The first support layer 421 and the second support layer 422 are respectively on both sides of the flow channel 50. As shown in fig. 22, a portion of the first material layer 411 is between the first support layer 412 and the flow channel 50, and another portion of the first material layer 411 is between the first support layer 412 and the first portion 211 of the substrate 21; a portion of the second material layer 421 is between the second support layer 422 and the runner 50, and another portion of the second material layer 421 is between the second support layer 422 and the second portion 212 of the substrate 21.
The flow channel structure device of the above embodiments of the present invention has a vertical flow channel, for example, the flow channel may be an open space in a direction perpendicular to the substrate or a transparent material may be provided, so that it does not affect the transmission of optical signals. In addition, the vertical flow channel is adopted, so that the effective surface area of a single flow channel is the sectional area of the flow channel, the manufacturing density of the flow channel on a chip can be greatly improved, the application flux (namely the number of the flow channels in unit area) can be improved, the manufacturing and application cost is reduced, and the like.
In one embodiment, the height of the flow channel 50 may range from 100 nm to 100 μm. For example, the height of the flow channel can be 500 nm, 1 micron, 10 microns, 50 microns, or the like. In one embodiment, the width of the flow channel 50 may range from 0.1 nm to 1 μm. For example, the width of the flow channel can be 1 nm, 10nm, 14 nm, 100 nm, 500 nm, or the like. After selecting proper height and width of the flow channel, the flow channel structure device can realize the flow channel structure with high aspect ratio.
In one embodiment, the thickness of the first material layer 411 may range from 1 nm to 500 nm. In one embodiment, the thickness of the first support layer 412 may range from 100 nm to 100 μm. In one embodiment, the thickness of the second material layer 421 can be in a range from 1 nm to 500 nm. In one embodiment, the thickness of the second support layer 422 may range from 100 nanometers to 100 micrometers.
In one embodiment, the material of the first material layer 411 may include: a metallic material or a semiconductor material (e.g., a doped semiconductor material). Wherein, the portion of the first material layer 411 between the first support layer 412 and the flow channel 50 can be used as a first electrode of the flow channel structure device; a portion of the first material layer 411 between the first support layer 412 and the first portion 211 of the substrate 21 may serve as a first lead of the first electrode. In one embodiment, the material of the second material layer 412 may include: a metallic material or a semiconductor material (e.g., a doped semiconductor material). Wherein a portion of the second material layer 412 between the second support layer 422 and the flow channel 50 can serve as a second electrode of the flow channel structure device; a portion of the second material layer 421 between the second support layer 422 and the second portion 212 of the substrate 21 may serve as a second lead of the second electrode. In this embodiment, since the first material layer and the second material layer are respectively formed integrally, contact resistance between the first electrode and the first lead and contact resistance between the second electrode and the second lead can be reduced as compared with the prior art, so that device performance can be improved.
In the above embodiments, the flow channel structure device may have a damascene electrode structure, and may have different biochemical analysis and fluid processing functions. For example, electrical or electrochemical reactions can occur in the flow channel by applying electrical excitation through the electrodes, electrical or optical signals can be generated, and specific molecular species can be identified through the acquired electrical or optical signals; still further, by identifying a variety of different molecular species, functions such as gene sequencing can be achieved.
In another embodiment, the materials of the first material layer 411 and the second material layer 421 may respectively include: an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc., or a combination of multiple insulating dielectric materials). The flow channel formed by the insulating medium material can be applied to the formation and control of fluid. For example, using insulating dielectric materials as the first material layer and the second material layer, the flow channel structure device can be applied to some cases where it is not necessary to apply electrodes in the flow channel, for example, in some cases, it is necessary to modify the flow channel surface with a specific insulating dielectric material as the material layer to obtain certain specific effects, such as obtaining a hydrophobic surface or a hydrophilic surface, etc., thereby facilitating the formation and control of fluid.
Fig. 23 and 24 are cross-sectional views schematically illustrating structures at several stages in the fabrication of a flow channel structure device according to another embodiment of the present invention. A process of manufacturing a flow channel structure device according to another embodiment of the present invention is described in detail below with reference to fig. 23 and 24.
In one embodiment, before removing the second sacrificial layer using the selective etching process and after performing the second polishing process, the manufacturing method may further include: a capping layer 60 is formed on the second sacrificial layer 32, the first material layer 411, the first support layer 412, the second material layer 421, and the second support layer 422. In the subsequent step of forming the flow channel, the cap layer can realize a closed flow channel structure together with the first structural layer (which may include the first material layer and the first support layer) and the second structural layer (which may include the second material layer and the second support layer), and can also avoid parasitic reaction which may be brought by contact between the tops of the first material layer and the second material layer and the fluid. In addition, for some applications where fluid (e.g., liquid) flow is desired in the flow channels, the capped flow channels of this embodiment are easier to control.
In one embodiment, similar to the above, in the step of removing the second sacrificial layer by using the selective etching process, a selective etching solution may be injected from the edge of the second sacrificial layer to remove the second sacrificial layer, thereby forming the flow channel structure device as shown in fig. 24. In a substantially planar structure, the second sacrificial layer, which extends in a plane, is bordered, and the edges of the second sacrificial layer may be exposed, so that a selective etching liquid is injected at the edges (i.e. borders) of the second sacrificial layer to remove the second sacrificial layer, thereby forming flow channels.
In another embodiment, similar to the foregoing, before removing the second sacrificial layer by using the selective etching process, the manufacturing method may further include: the cap layer is etched to form a via hole (not shown in fig. 24, see via hole 61 in fig. 12) that penetrates the cap layer and exposes the second sacrificial layer. In the step of removing the second sacrificial layer by using a selective etching process, a selective etching solution may be injected from the through hole to remove the second sacrificial layer, thereby forming the flow channel structure device as shown in fig. 24. In this embodiment, the etching rate can be increased by forming the through hole on the cap layer, thereby facilitating the selective etching solution to pass through the through hole to remove the second sacrificial layer in the selective etching process.
From the above manufacturing method, a flow channel structure device according to another embodiment of the present invention is also formed. As shown in fig. 24, the flow channel structure device may include the same or similar structure as fig. 22, and may include, for example: the substrate 21, the first material layer 411, the first support layer 412, the second material layer 421, the second support layer 422, and the flow channel 50, which will not be described in detail herein.
In one embodiment, as shown in fig. 24, the flow channel structure device may further include: a capping layer 60 covering the first material layer 411, the first support layer 412, the second material layer 421 and the second support layer 422. Wherein the cap layer 60 covers the flow channel 50. The capping layer 60 can realize a closed flow channel (i.e., the flow channel is closed above) together with the first structural layer 41 (which may include the first material layer 411 and the first support layer 412) and the second structural layer 42 (which may include the second material layer 421 and the second support layer 422), and can also avoid parasitic reactions that may be caused by the contact between the upper surfaces of the first structural layer 41 and the second structural layer 42 and the fluid. In addition, for some applications where fluid (e.g., liquid) flow is desired in the flow channels, the capped flow channels of this embodiment are easier to control.
In one embodiment, the material of the cap layer 60 may include: an insulating dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass, aluminum oxide, titanium oxide, tantalum oxide, or the like) or a semiconductor material (e.g., polysilicon, amorphous silicon, or the like).
In one embodiment, the cap layer 60 may have a thickness ranging from 1 nanometer to 10 micrometers. For example, the cap layer may have a thickness of 10 nanometers, 100 nanometers, 500 nanometers, 1 micron, 5 microns, or the like.
In one embodiment, the flow channel structure device may further comprise: and the through hole penetrates through the cap layer and is communicated with the flow channel.
Thus, fabrication methods and flow channel structure devices formed by these fabrication methods are provided according to some embodiments of the present invention. The flow channels of embodiments of the invention may be nanochannels. The invention has the following advantages: (1) The nano flow channel structure with high depth-width ratio can be realized, and the size controllability is good; (2) a full metal conductive electrode mosaic structure can be realized; (3) The manufacturability of the nano flow channel structure can be effectively improved, and the manufacturing cost of the nano flow channel structure is reduced; (4) Has a relatively low thermal budget and is compatible with integrated circuit processes. In addition, the flow channel structure device provided by the embodiment of the invention can be applied to the aspects of molecular detection, liquid formation or fluid transportation control and the like.
In one embodiment of the present invention, a flow channel sensor may also be provided. The flow channel sensor may include: a flow channel structure device as previously described (e.g. as shown in figure 22 or as shown in figure 24).
In one embodiment of the present invention, there may also be provided a biochemical analysis apparatus. The biochemical analysis apparatus may include: a flow channel structure device as hereinbefore described (e.g. as shown in figure 22 or as shown in figure 24).
FIG. 25 is a structural diagram schematically showing a chip for molecular detection according to an embodiment of the present invention. As shown in fig. 25, the chip 250 may include: a flow channel structure device 2501, a signal collection unit 2502, and a signal processing unit 2503. The flow channel structure device 2501 includes electrodes (e.g., a first electrode and a second electrode). The flow channel structure device may be, for example, a flow channel structure device as shown in fig. 22 or as shown in fig. 24. Wherein, a sample to be detected is added into a flow channel of the flow channel structure device, and under the condition that electrodes (such as a first electrode and a second electrode) of the flow channel structure device are applied with electric excitation, a target molecule in the sample to be detected generates an electric signal or an optical signal under the action of the electric excitation.
The signal collection unit 2502 may be used to collect the electrical signal or the optical signal and transmit the electrical signal or the optical signal to the signal processing unit 2503.
The signal processing unit 2503 can be used to perform signal processing on the electrical signal or the optical signal to identify information of the target molecule.
In the embodiment of the invention, the invention also provides a molecular detection method. The method can comprise the following steps: the molecular assay is performed using a chip as described previously (e.g., the chip shown in FIG. 25).
FIG. 26 is a flow chart illustrating a method of molecular detection according to one embodiment of the present invention. The procedure of molecular detection using the chip is described below with reference to FIG. 26.
In step S2601, a sample to be tested is processed. For example, the sample to be tested may be subjected to chemical or other treatment.
In step S2602, a sample to be tested is added to the chip. For example, a sample to be tested is added to the flow channel of the flow channel structure device of the chip.
In step S2603, electrical excitation is applied to electrodes (e.g., a first electrode and a second electrode) in the flow channel structure device in the chip, so that the target molecules in the sample to be detected generate electrical signals or optical signals under the action of the electrical excitation.
In step S2604, the signal processing unit of the chip obtains the electrical signal or the optical signal through the signal collection unit, and performs signal processing on the electrical signal or the optical signal to identify the information of the target molecule.
In the above embodiments, the application of molecular detection is realized by using a chip including the flow channel structure device of the embodiments of the present invention.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. Those skilled in the art can now fully appreciate how to implement the teachings disclosed herein, in view of the foregoing description.
Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (27)

1. A method of fabricating a flow channel structure device, comprising:
providing a substrate comprising a first portion and a second portion contiguous with the first portion;
forming a patterned first sacrificial layer on the substrate, the first sacrificial layer covering the second portion and exposing the first portion;
forming a first structural layer on a first portion of the substrate and the first sacrificial layer;
after forming the first structural layer, performing a first polishing process to expose the first sacrificial layer;
removing the first sacrificial layer to expose an upper surface of the second portion of the substrate and a side surface of the first structural layer;
forming a second sacrificial layer on a portion of an upper surface of a second portion of the substrate, wherein the second sacrificial layer covers the exposed side of the first structural layer;
forming a second structural layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer;
after forming the second structural layer, performing a second polishing process to expose the second sacrificial layer; and
and removing the second sacrificial layer by using a selective etching process to form a flow channel.
2. The manufacturing method according to claim 1,
in the step of performing the second polishing process, the first structural layer and the second structural layer are also exposed;
before removing the second sacrificial layer using a selective etch process, the method further comprises: forming a capping layer on the second sacrificial layer, the first structural layer and the second structural layer.
3. The manufacturing method according to claim 1,
the step of forming a first structural layer comprises: forming a first material layer on a first portion of the substrate and the first sacrificial layer, wherein the first material layer covers a side of the first sacrificial layer; and forming a first support layer on the first material layer; wherein the first structural layer comprises: the first material layer and the first support layer;
the step of forming a second structural layer comprises: forming a second material layer on the second portion of the substrate, the second sacrificial layer, and the first structural layer, the second material layer covering a side of the second sacrificial layer; and forming a second support layer on the second material layer; wherein the second structural layer comprises: the second material layer and the second support layer.
4. The manufacturing method according to claim 3,
in the step of removing the first sacrificial layer to expose the side surface of the first structural layer, the exposed side surface of the first structural layer is a side surface of the first material layer;
in the step of forming a second sacrificial layer, the second sacrificial layer covers the exposed side surface of the first material layer.
5. The manufacturing method according to claim 3,
in the step of performing the second polishing process, the first material layer, the first support layer, the second material layer, and the second support layer are also exposed;
before removing the second sacrificial layer using a selective etch process, the method further comprises: forming a cap layer on the second sacrificial layer, the first material layer, the first support layer, the second material layer, and the second support layer.
6. The manufacturing method according to claim 2 or 5,
the material of the cap layer comprises: an insulating dielectric material or a semiconductor material;
the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
7. The manufacturing method according to claim 2 or 5,
and in the step of removing the second sacrificial layer by using a selective etching process, injecting selective etching liquid from the edge of the second sacrificial layer to remove the second sacrificial layer.
8. The manufacturing method according to claim 2 or 5,
before removing the second sacrificial layer using a selective etch process, the method further comprises: etching the cap layer to form a through hole which penetrates through the cap layer and exposes the second sacrificial layer;
and injecting selective etching liquid from the through hole to remove the second sacrificial layer in the step of removing the second sacrificial layer by using a selective etching process.
9. The manufacturing method according to claim 3,
a portion of the first layer of material is between the first support layer and the flow channel and another portion of the first layer of material is between the first support layer and the first portion of the substrate;
a portion of the second material layer is between the second support layer and the flow channel and another portion of the second material layer is between the second support layer and a second portion of the substrate.
10. The manufacturing method according to claim 9,
the material of the first material layer comprises: a metal material or a semiconductor material;
the material of the second material layer comprises: a metallic material or a semiconductor material;
wherein a portion of the first material layer between the first support layer and the flow channel serves as a first electrode of the flow channel structure device; a portion of the first material layer between the first support layer and the first portion of the substrate serves as a first lead of the first electrode; a portion of the second material layer between the second support layer and the flow channel serves as a second electrode of the flow channel structure device; a portion of the second material layer between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
11. The manufacturing method according to claim 3,
the material of the first material layer and the material of the second material layer respectively include: an insulating dielectric material.
12. The manufacturing method according to claim 1,
the thickness of the first sacrificial layer is determined according to the height of a required flow channel;
the thickness of the first sacrificial layer ranges from 100 nanometers to 100 micrometers.
13. The manufacturing method according to claim 1,
the thickness of the second sacrificial layer is determined according to the width of a required flow channel;
the thickness of the second sacrificial layer ranges from 0.1 nanometers to 1 micrometer.
14. The manufacturing method according to claim 3,
the thickness of the first material layer ranges from 1 nanometer to 500 nanometers;
the thickness of the first support layer ranges from 100 nanometers to 100 micrometers;
the thickness of the second material layer ranges from 1 nanometer to 500 nanometers;
the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.
15. A flow channel structure device formed by the manufacturing method according to claim 9, comprising:
a substrate comprising a first portion and a second portion contiguous with the first portion;
a first structural layer and a second structural layer on the substrate; wherein the first structural layer comprises: a first layer of material on a first portion of the substrate and a first support layer on the first layer of material, the second structural layer comprising: a second material layer on a second portion of the substrate and a second support layer on the second material layer;
a flow channel between the first material layer and the second material layer; the first supporting layer and the second supporting layer are respectively arranged on two sides of the flow channel;
wherein a portion of the first material layer is between the first support layer and the flow channel and another portion of the first material layer is between the first support layer and the first portion of the substrate; a portion of the second material layer is between the second support layer and the flow channel and another portion of the second material layer is between the second support layer and a second portion of the substrate.
16. The flow channel structure device according to claim 15, further comprising:
a capping layer overlying the first material layer, the first support layer, the second material layer, and the second support layer; wherein the cap layer covers the flow channel.
17. The flow channel structure device according to claim 16,
the material of the cap layer comprises: an insulating dielectric material or a semiconductor material;
the cap layer has a thickness in a range from 1 nanometer to 10 micrometers.
18. The flow channel structure device according to claim 16, further comprising:
and the through hole penetrates through the cap layer and is communicated with the flow channel.
19. The flow channel structure device according to claim 15,
the material of the first material layer comprises: a metallic material or a semiconductor material;
the material of the second material layer comprises: a metal material or a semiconductor material;
wherein a portion of the first material layer between the first support layer and the flow channel serves as a first electrode of the flow channel structure device; a portion of the first material layer between the first support layer and the first portion of the substrate serves as a first lead of the first electrode; the part of the second material layer between the second support layer and the flow channel is used as a second electrode of the flow channel structure device; a portion of the second material layer between the second support layer and the second portion of the substrate serves as a second lead of the second electrode.
20. Flow channel structure device according to claim 15,
the material of the first material layer and the material of the second material layer respectively include: an insulating dielectric material.
21. The flow channel structure device according to claim 15,
the height range of the flow channel is 100 nanometers to 100 micrometers;
the width of the flow channel ranges from 0.1 nanometer to 1 micrometer.
22. Flow channel structure device according to claim 15,
the thickness of the first material layer ranges from 1 nanometer to 500 nanometers;
the thickness of the first support layer ranges from 100 nanometers to 100 micrometers;
the thickness of the second material layer ranges from 1 nanometer to 500 nanometers;
the thickness of the second support layer ranges from 100 nanometers to 100 micrometers.
23. A flow channel sensor, comprising: a flow-channel structure device according to any of claims 15 to 22.
24. A biochemical analysis apparatus, characterized by comprising: a flow-channel structure device according to any of claims 15 to 22.
25. A chip for molecular detection, comprising: a flow channel structure device according to claim 19, a signal collection unit and a signal processing unit;
the method comprises the following steps that a sample to be detected is added into a flow channel of a flow channel structure device, and under the condition that an electrode of the flow channel structure device is applied with electric excitation, target molecules in the sample to be detected generate electric signals or optical signals under the action of the electric excitation;
the signal collecting unit is used for collecting the electric signal or the optical signal and transmitting the electric signal or the optical signal to the signal processing unit;
the signal processing unit is used for carrying out signal processing on the electric signal or the optical signal and identifying the information of the target molecule.
26. A method of molecular detection, comprising: molecular detection using the chip of claim 25.
27. The method of claim 26, wherein the step of performing molecular detection using the chip comprises:
processing a sample to be detected;
adding the sample to be detected into the chip;
applying electric excitation to electrodes in a flow channel structure device in the chip so that target molecules in the sample to be detected generate electric signals or optical signals under the action of the electric excitation; and
the signal processing unit of the chip obtains the electric signal or the optical signal through the signal collecting unit, and performs signal processing on the electric signal or the optical signal to identify the information of the target molecule.
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