CN110768676A - Encoding method, encoding device, computer equipment and storage medium - Google Patents
Encoding method, encoding device, computer equipment and storage medium Download PDFInfo
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Abstract
The invention is suitable for the field of computers, and provides an encoding method, an encoding device, computer equipment and a storage medium thereof, wherein the encoding method comprises the following steps: receiving a channel source code to be coded, and generating a first check chart; expanding the check nodes in the first check graph by adopting an error correcting code to obtain a second check graph; merging the two second check graphs to obtain a third check graph; mapping the third check chart to the first check matrix to obtain a supervision matrix; according to the formula G.HTAnd calculating to obtain a generator matrix, and encoding the channel source code to obtain a channel code. The check graph is designed, and the check nodes of the check graph are expanded by using a high-efficiency linear grouping or convolutional code check matrix to eliminate multiple edges, so that the check graph meets the requirement that the variables correspond to the check nodes, a required check matrix is obtained, the coded channel code has decoding performance similar to the Shannon limit, the decoding speed is high, the decoding is easy to realize, the lower error code flat bottom is realized, and the method is more suitable for the fields of wireless communication, emergency communication and the like.
Description
Technical Field
The present invention relates to the field of computers, and in particular, to an encoding method, an encoding apparatus, a computer device, and a storage medium.
Background
Coal is one of the main energy sources in China and is the basis of national economy and social development. However, the underground operation of coal mines in China is far away from the ground, the terrain is complex, the environment is severe, personnel and equipment are scattered, mine safety accidents and natural disasters frequently happen in recent years, huge economic losses and adverse social effects are caused, and remote multimedia communication service becomes necessary. Ground monitoring personnel need to directly communicate information with underground personnel, need to directly issue commands to the underground personnel, need to comprehensively and visually monitor actual production conditions of underground working sites, find accident head-of-seedling prevention in time, and also can provide relevant first-hand site data for experience and training in the process of analyzing accidents afterwards and total rescue. Therefore, the quality of video and voice communication is a major consideration of mining multimedia communication systems.
At present, in the existing domestic mining multimedia communication system, the problems of poor voice communication and sound collection quality, limited configuration, information transmission by means of cables and the like exist, a video monitoring and transmission system based on WiFi wireless communication transmission is adopted, the transmission of real-time video monitoring data of a disaster site can be effectively completed on such occasions, ground rescue workers can be effectively guided to carry out more targeted rescue work, the largest possible rescue guarantee is provided for saving lives of the disaster workers, however, in WIFI wireless transmission, the video monitoring and transmission system is an important technical means for information compression and reliable transmission, the existing coding technology is low in decoding speed, difficult to achieve, high in error code flat bottom and not mature in application of wireless transmission, and cannot be used in the field of wireless emergency communication.
Therefore, the technical problems that the decoding speed is low, the realization is difficult, the error code level is high, and the existing coding technology cannot be applied to the field of wireless emergency communication are urgently needed to be solved.
Disclosure of Invention
The embodiment of the invention aims to provide an encoding method, an encoding device, computer equipment and a storage medium, and aims to solve the technical problems that the existing encoding technology is low in decoding speed, difficult to realize, high in error code flat base and incapable of being applied to the field of wireless emergency communication.
The embodiment of the present invention is implemented as follows, in which an encoding method includes:
receiving a channel source code to be coded, and generating a first check chart of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between variable nodes and check nodes in the eIRA code;
expanding the check nodes in the first check graph by adopting an error correcting code to obtain a second check graph;
copying the second check graph, and merging the two second check graphs to obtain a third check graph; wherein, there is at most one connecting line between variable node and check node in the third check graph;
mapping the third check chart to a first check matrix to obtain a supervision matrix;
according to the formula G.HTCalculating to obtain a generator matrix, wherein the generator matrix is used for encoding the channel source code to obtain a channel code; wherein G represents the supervision matrix, H represents the generation matrix, T represents transposing the matrix, and O represents a 0 matrix.
Another object of an embodiment of the present invention is to provide an encoding designing apparatus, including:
the verification graph generating unit is used for receiving a channel source code to be coded and generating a first verification graph of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between the variable nodes and the check nodes in the eIRA code;
the check map processing unit is used for expanding the check nodes in the first check map by adopting an error correcting code to obtain a second check map; copying the second check graph, and merging the two second check graphs to obtain a third check graph; wherein, there is at most one connecting line between variable node and check node in the third check graph; mapping the third check graph to a first check matrix to obtain a supervision matrix;
a calculation output unit for outputting the calculated G.HTCalculating to obtain a generator matrix and outputting the generator matrix, wherein the generator matrix is used for encoding a channel source code to obtain a channel code; wherein G represents the supervision matrix, H represents the generation matrix, T represents transposing the matrix, and O represents a 0 matrix.
Another object of an embodiment of the present invention is a computer device, including a memory and a processor, where the memory stores a computer program, and the computer program, when executed by the processor, causes the processor to execute the steps of the code design method in the above embodiment.
Another object of an embodiment of the present invention is a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, causes the processor to execute the steps of the code design method described in the above embodiment.
In the encoding method, the encoding device, the computer equipment and the storage medium provided by the embodiment of the invention, the existing heuristic optimization algorithm is utilized to design the check graph, and the check nodes of the check graph are expanded by using the check matrix of the efficient linear grouping or convolutional code; the method comprises the steps of eliminating multiple edges through copying and repeated processing, obtaining a newly expanded check chart, enabling the check chart to meet the requirement that variables correspond to check nodes, obtaining a required check matrix through sub-matrix offset optimization search in a quasi-cyclic matrix, and encoding channel source codes, so that the encoded channel codes have decoding performance similar to the Shannon limit, the decoding speed is high, the method is easy to achieve, the channel codes have low error code flat bottoms, and the method is more suitable for the fields of wireless communication, emergency communication and the like.
Drawings
Fig. 1 is an application environment diagram of an encoding method according to an embodiment of the present invention;
FIG. 2 is a flow chart of an encoding method according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating steps of an encoding method according to an embodiment of the present invention;
FIG. 4 is a first verification diagram provided in accordance with an embodiment of the present invention;
FIG. 5 is a second calibration graph provided by an embodiment of the present invention;
FIG. 6 is a third verification diagram and a schematic diagram of a third verification diagram according to an embodiment of the invention;
fig. 7 is a detailed flowchart of generating a first check chart according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating a method for obtaining a second verification graph according to an embodiment of the present invention;
fig. 9 is a specific flowchart for obtaining a third verification diagram according to an embodiment of the present invention;
fig. 10 is a specific flowchart for obtaining a supervision matrix according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present invention;
fig. 12 is a schematic internal structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms unless otherwise specified. These terms are only used to distinguish one element from another. For example, a first xx script may be referred to as a second xx script, and similarly, a second xx script may be referred to as a first xx script, without departing from the scope of the present application.
Fig. 1 is a diagram of an application environment of an encoding method according to an embodiment of the present invention, as shown in fig. 1, in the application environment, a computer device 110, an input channel 120, and an output channel 130 are included.
The computer device 110 may be, but is not limited to, a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and the like.
The input channel 120 and the output channel 130 may be a wired communication connection or a wireless communication connection, which is not limited in this application.
As shown in fig. 2, in an embodiment, an encoding method is provided, which is mainly illustrated by applying the method to the computer device in fig. 1, where fig. 3 shows a schematic diagram of steps of the encoding method provided in the embodiment of the present invention, and an encoding method specifically includes the following steps:
step S202, receiving a channel source code to be coded, and generating a first check chart of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between the variable nodes and the check nodes in the eIRA code.
In the embodiment of the invention, the channel source code is a signal code which needs to be transmitted, can represent character information, picture information, sound information, video information or other information, and can form a code suitable for long-distance stable transmission through coding; heuristic algorithms (heuristic algorithms) are proposed relative to optimization algorithms, which can be defined as an algorithm based on intuitive or empirical construction, which gives a feasible solution for each instance of the combined optimization problem to be solved at an acceptable cost (referring to computation time and space), and the deviation degree of the feasible solution from the optimal solution can not be expected in general, and the first check chart is the check chart obtained initially in the application, wherein the first check chart is used for distinguishing the check chart from the check chart obtained subsequently. The preset code rate refers to a preset code rate, and can be freely set according to requirements.
In the embodiment of the present invention, fig. 4 shows a first check graph provided in the embodiment of the present invention, and a first check graph of an eIRA code with a preset code rate is generated according to a heuristic optimization algorithm, which means that a check node and a variable node are exhausted to obtain a relationship graph of the check node and the variable node, as shown in fig. 4, a square in the graph represents the check node, a circle represents the variable node, and for a most basic check node, one check node and two variable nodes, the check node is used for checking whether communication between the two variable nodes is normal, a heuristic optimization algorithm is adopted to simulate a connection relationship between the check node and the variable node, and then the check node and the two variable nodes are connected to form the first check graph.
Step S204, expanding the check nodes in the first check graph by adopting an error correcting code to obtain a second check graph.
In the embodiment of the present invention, an error correcting code (error correcting code) refers to a code that can be found or corrected at a receiving end after an error occurs in a transmission process, and a basic idea of the error correcting code is to select only a part of sequences composed of transmission symbols as a representative of information to be transmitted to a channel, and to make the selected sequences have as many differences as possible, and the code word can be extended by using the error correcting code.
In the embodiment of the present invention, fig. 5 illustrates a second check graph provided in the embodiment of the present invention, as shown in fig. 5, the check nodes 0 and 1 and the variable nodes 0, 1 and 2 extend the connection relationship between the check nodes and the variable nodes by using an error correction code, that is, adding one codeword between the variable nodes, changing two variable nodes in the first check graph into three variable nodes, and changing the detection nodes into two, and then rearranging the connection relationship between the detection nodes and the variable nodes to obtain a second check graph as shown in fig. three, where there are repeated connecting lines between the detection node 0 and the variable node 0.
Step S206, copying the second check chart, and merging the two second check charts to obtain a third check chart; and at most one connecting line is arranged between the variable node and the check node in the third check graph.
In the embodiment of the present invention, fig. 6 shows a schematic diagram for forming a third check graph provided in the embodiment of the present invention, and as shown in fig. 6, the second check graph is copied to obtain two second check graphs, and then the two second check graphs are merged to obtain a third check graph, but at most one connection line can exist between one check node and one variable node in the third check graph.
And step S208, mapping the third check chart to the first check matrix to obtain a supervision matrix.
In the embodiment of the present invention, the first check matrix is generated according to the codeword, the number of rows and columns of the check matrix is consistent with the number of information symbols and total symbols in the codeword, for example, there are 7 symbols in one codeword, where 4 information symbols and three parity symbols, then the first check matrix is a matrix with 4 rows and 7 columns, and elements of the first check matrix are supplemented according to the relationship between the parity check nodes and the variable nodes, and a connection line between the variable nodes and the parity check nodes is represented by 1, otherwise, it is represented by 0.
Step S2010, according to the formula G.HTCalculating to obtain a generator matrix, wherein the generator matrix is used for encoding the channel source code to obtain a channel code; wherein G represents the supervision matrix, H represents the generator matrix, T represents transposing the matrix, and 0 represents a 0 matrix.
The embodiment of the invention designs a check graph by using the existing heuristic optimization algorithm, and the check nodes of the check graph are expanded by using a high-efficiency linear grouping or convolution code check matrix; the method comprises the steps of eliminating multiple edges through copying and repeated processing, obtaining a newly expanded check chart, enabling the check chart to meet the requirement that variables correspond to check nodes, obtaining a required check matrix through sub-matrix offset optimization search in a quasi-cyclic matrix, and encoding channel source codes, so that the encoded channel codes have decoding performance similar to the Shannon limit, the decoding speed is high, the method is easy to achieve, the channel codes have low error code flat bottoms, and the method is more suitable for fields such as wireless communication and emergency communication.
In an embodiment, as shown in fig. 7, step S202 may specifically include the following steps:
step S702, generating a check node and two variable nodes, obtaining a connection relation between the check node and the two variable nodes through an exhaustion method, and obtaining the first check graph through line representation; and 0, 1 or a plurality of connecting lines are arranged between one check node and one variable node.
In the embodiment of the present invention, fig. 4 shows a first check graph provided in the embodiment of the present invention, where a preset code rate is one half bit, as shown in fig. 4, a square in the graph represents a check node, a circle represents a variable node, and for a most basic check structure, one check node and two variable nodes, the check node is used to check whether communication between the two variable nodes is normal, a heuristic optimization algorithm is used to simulate a connection relationship between the check node and the variable node, and then the check node and the two variable nodes have a connection line to form the first check graph, the connection relationship between the one check node and the two variable nodes is obtained by an exhaustive method, and the first check graph is obtained by representing the connection line; and 0, 1 or a plurality of connecting lines are arranged between one check node and one variable node.
According to the embodiment of the invention, the connection relation between one check node and two variable nodes is obtained through an exhaustion method to form the first check graph.
In an embodiment, as shown in fig. 8, step S204 may specifically include the following steps:
step S802, a packet interleaver is constructed through the parity check relation of the high-efficiency linear block code or the convolutional code.
In the embodiment of the present invention, the error correcting code is an efficient linear block code or a convolutional code, and M code words in the linear block code have a certain linear constraint relationship, that is, the code words collectively form a k-dimensional subspace of an n-dimensional linear space. This k-dimensional subspace is called the (n, k) linear block code. The linear system code is characterized in that the first k bits of each code word are composed of information bits corresponding to the code word, the following n-k bits are obtained through linear operation of the k information bits, n-tuple elements generated by convolutional code encoding are not only related to the currently input k tuple, but also related to the first m-1 input k tuples, and the number of the symbols correlated with each other in the encoding process is n m. The error correction performance of convolutional codes increases with increasing m, while the error rate decreases exponentially with increasing N. The embodiment of the invention can construct the packet interleaver by the parity check relation of the linear block code or the convolutional code.
Step S804, randomly distributing the packet interleaver between the check nodes and the variable nodes of the first check graph to form the second check graph.
In the embodiment of the present invention, as shown in fig. 5, interleavers are distributed between check nodes and variable nodes, the check nodes 0 and 1 and the variable nodes 0, 1 and 2, a connection relationship between the check nodes and the variable nodes is expanded by an error correction code, that is, a codeword is added between the variable nodes, two variable nodes in a first check map are changed into three variable nodes, and then two detection nodes are changed, and then the connection relationship between the detection nodes and the variable nodes is rearranged to obtain a second check map as shown in fig. three, where there are repeated connecting lines between the detection node 0 and the variable node 0.
According to the embodiment of the invention, the second inspection chart is obtained by expanding the first inspection chart.
In an embodiment, as shown in fig. 9, step S206 may specifically include the following steps:
step S902, when a plurality of connection lines exist between a first check node and a first variable node in the second check graph, copying the second check graph to obtain a second check graph replica graph, where a second check node and a second variable node of the second check graph replica graph correspond to the first check node and the second check node in the second check graph.
In the embodiment of the present invention, as shown in fig. 6, repeated connecting lines exist between the first check node and the first variable node of the second check graph, and the second check graph is copied to obtain the second check graph copy graph.
Step S904, connecting the repeated connection line of the first check node and the first variable node to the space between the first check node and the second variable node, and connecting the repeated connection line of the second check node and the second variable node to the space between the second check node and the first variable node, so as to form the third check graph.
In the embodiment of the present invention, as shown in fig. 6, the second check graph and the second check graph replica graph are merged, the repeated connection lines in the first check node and the first variable node are connected between the first check node and the second variable node, and the repeated connection lines in the second check node and the second variable node are connected between the second check node and the first variable node, so as to form the third check graph.
In the embodiment of the invention, the repeated connecting lines between the check nodes and the variable nodes are removed by copying the second check graph and merging the second check graph and the second check graph copy graph to form the third check graph.
In an embodiment, as shown in fig. 10, step S208 may specifically include the following steps:
step S1002, mapping the third check map into the first check matrix according to the generation rule of the check matrix.
In the embodiment of the present invention, the first check matrix is generated according to the codeword, the number of rows and columns of the check matrix is consistent with the number of information symbols and total symbols in the codeword, for example, there are 7 symbols in one codeword, where 4 information symbols and three parity symbols, then the first check matrix is a matrix with 4 rows and 7 columns, and elements of the first check matrix are supplemented according to the relationship between the parity check nodes and the variable nodes, and a connection line between the variable nodes and the parity check nodes is represented by 1, otherwise, it is represented by 0. As an embodiment of the present invention, the example of (7, 4) is given as an example, and 7 symbols C are included in one code word C of the (7, 4) linear block code6c5c4c3c2c1c0Wherein c is6c5c4c3As information symbols, c2c1c0Is a parity symbol. The relationship between the parity symbols and the information symbols may be represented by the following relationship:
where "+" is modulo-2 plus, the relationship between the 7 symbols of the (7, 4) code and the information code can be expressed as a matrix equation.
Step S1004, replacing the element "0" and the element "1" in the first check matrix with a zero matrix and a unit cyclic matrix of a preset dimension, respectively, to obtain the supervision matrix.
In the embodiment of the present invention, the relationship between the 7 symbols of the (7, 4) code and the information code can be expressed as a matrix equation, that is:
therefore, the temperature of the molten metal is controlled,
g is formed into a supervision matrix of the code (7, 4).
According to the formula G.HTCalculating to obtain a generating matrix; wherein G represents the supervision matrix, H represents the generator matrix, T represents transposing the matrix, and 0 represents a 0 matrix. And multiplying the generated matrix by a channel source code to obtain the channel code, and finishing the coding of the channel source code.
In the embodiment of the invention, more than one of the generation matrices satisfies G.HTAnd a plurality of generation matrixes H are provided, the channel source codes are coded for a plurality of times, the coded channel codes are selected to have decoding performance similar to the Shannon limit, the decoding speed is high, the realization is easy, and the generation matrix with a lower error code flat bottom is used as the optimal generation matrix to code the coded channel source codes.
As shown in fig. 11, in an embodiment, an encoding apparatus is provided, which may be integrated in the computer device 110, and specifically may include a verification graph generating unit 1210, a verification graph processing unit 1220, and a calculation output unit 1230.
The verification graph generating unit 1210 is configured to receive a channel source code to be coded, and generate a first verification graph of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between the variable nodes and the check nodes in the eIRA code;
the check map processing unit 1220 is configured to extend the check nodes in the first check map by using an error correction code to obtain a second check map; copying the second check graph, and merging the two second check graphs to obtain a third check graph; wherein, there is at most one connection between variable node and check node in the third check graph; mapping the third check chart to a first check matrix to obtain a supervision matrix;
a calculation output unit 1230 for outputting the formula G.HTCalculating to obtain a generator matrix and outputting the generator matrix, wherein the generator matrix is used for encoding a channel source code to obtain a channel code; wherein G denotes the supervision matrix, H denotes the generator matrix, T denotes transposing the matrix, and 0 denotes a 0 matrix.
FIG. 12 is a diagram illustrating an internal structure of a computer device in one embodiment. The computer device may be the computer device 110 of fig. 1. As shown in fig. 12, the computer apparatus includes a processor, a memory, a network interface, an input device, and a display screen connected through a system bus. Wherein the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program which, when executed by the processor, causes the processor to implement the encoding method. The internal memory may also have stored therein a computer program that, when executed by the processor, causes the processor to perform the encoding method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 12 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects may be applied, and that a particular computing device may include more or less components than those shown, or some components may be combined, or have a different arrangement of components.
In one embodiment, a computer device is proposed, the computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
receiving a channel source code to be coded, and generating a first check chart of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between variable nodes and check nodes in the eIRA code;
expanding the check nodes in the first check graph by adopting an error correcting code to obtain a second check graph;
copying the second check graph, and merging the two second check graphs to obtain a third check graph; wherein, there is at most one connecting line between variable node and check node in the third check graph;
mapping the third check chart to a first check matrix to obtain a supervision matrix;
according to the formula G.HTCalculating to obtain a generator matrix, wherein the generator matrix is used for encoding the channel source code to obtain a channel code; wherein G represents the supervision matrix, H represents the generator matrix, T represents transposing the matrix, and 0 represents a 0 matrix.
In one embodiment, a computer readable storage medium is provided, having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the steps of:
receiving a channel source code to be coded, and generating a first check chart of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between variable nodes and check nodes in the eIRA code;
expanding the check nodes in the first check graph by adopting an error correcting code to obtain a second check graph;
copying the second check graph, and merging the two second check graphs to obtain a third check graph; wherein, there is at most one connecting line between variable node and check node in the third check graph;
mapping the third check chart to a first check matrix to obtain a supervision matrix;
according to the formula G.HTCalculating to obtain a generator matrix, wherein the generator matrix is used for encoding the channel source code to obtain a channel code; wherein G represents the supervision matrix, H represents the generator matrix, T represents transposing the matrix, and 0 represents a 0 matrix.
In the storage medium provided by the embodiment of the invention, the computer program is stored on the computer readable storage medium, when the computer program is executed by the processor, the existing heuristic optimization algorithm is utilized to design the check graph, and the check nodes of the check graph are expanded by using the high-efficiency linear grouping or convolutional code check matrix; the method comprises the steps of eliminating multiple edges through copying and repeated processing, obtaining a newly expanded check chart, enabling the check chart to meet the requirement that variables correspond to check nodes, obtaining a required check matrix through sub-matrix offset optimization search in a quasi-cyclic matrix, and encoding channel source codes, so that the encoded channel codes have decoding performance similar to the Shannon limit, and are high in decoding speed, easy to achieve, low in error code flat bottom, and more suitable for the fields of wireless communication, emergency communication and the like.
It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in the embodiments may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least some of the sub-steps or stages of other steps.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a non-volatile computer readable storage medium, and can include the processes of the embodiments of the methods described above when executed. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bused dynamic RAM (DRDRAM), and bused dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. An encoding method, characterized in that the encoding method comprises:
receiving a channel source code to be coded, and generating a first check chart of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between the variable nodes and the check nodes in the eIRA code;
expanding the check nodes in the first check graph by adopting an error correcting code to obtain a second check graph;
copying the second check graph, and merging the two second check graphs to obtain a third check graph; wherein, there is at most one connecting line between variable node and check node in the third check graph;
mapping the third check chart to a first check matrix to obtain a supervision matrix;
according to the formula G.HTCalculating to obtain a generator matrix, wherein the generator matrix is used for encoding the channel source code to obtain a channel code; wherein G represents the supervision matrix, H represents the generation matrix, T represents transposing the matrix, and O represents a 0 matrix.
2. The method of claim 1, wherein the predetermined code rate is one-half bit;
the generating of the first check chart of the eIRA code with the preset code rate according to the heuristic optimization algorithm comprises the following steps:
generating a check node and two variable nodes, obtaining a connection relation between the check node and the two variable nodes through an exhaustion method, and representing the connection relation through a connecting line to obtain the first check graph; and 0 or 1 or more connecting lines are arranged between one check node and one variable node.
3. The method of claim 1, wherein the error correction code is a high efficiency linear block code or a convolutional code;
the expanding the check nodes in the first check graph by adopting the error correcting code to obtain a second check graph comprises the following steps:
constructing a packet interleaver through the parity check relation of the high-efficiency linear block code or the convolutional code;
and randomly distributing the packet interleavers between check nodes and variable nodes of the first check graph to form the second check graph.
4. The method of claim 1, wherein the copying the second parity graph and merging the two second parity graphs to obtain a third parity graph comprises:
when a plurality of connecting lines exist between a first check node and a first variable node in the second check graph, copying the second check graph to obtain a second check graph copy graph, wherein a second check node and a second variable node of the second check graph copy graph correspond to the first check node and the second check node in the second check graph;
connecting repeated connecting lines in the first check node and the first variable node to the position between the first check node and the second variable node, and connecting repeated connecting lines in the second check node and the second variable node to the position between the second check node and the first variable node to form the third check graph.
5. The method of claim 1, wherein mapping the third check map into the first check matrix, and wherein obtaining the supervisory matrix comprises:
mapping the third check chart into a first check matrix according to a generating rule of the check matrix;
and replacing an element '0' and an element '1' in the first check matrix with a zero matrix and a unit cyclic matrix of preset dimensions respectively to obtain the supervision matrix.
6. The method of claim 5, wherein the identity cyclic matrix is a matrix obtained by circularly right-shifting element "1" in the identity matrix;
the replacing the element "0" and the element "1" in the first check matrix with a zero matrix and a unit cyclic matrix of a preset dimension respectively to obtain the supervision matrix, further comprising:
and replacing an element '0' in the first check matrix with a zero matrix of a preset dimension, and replacing an element '1' in the first check matrix with the unit cyclic matrix to obtain the supervision matrix.
7. The method according to claim 1, wherein the method is according to the formula G-HTCalculating to obtain a generator matrix, where the generator matrix is used to encode a channel source code, and obtaining a channel code includes:
according to the formula G.HTCalculating to obtain a generating matrix;
and multiplying the generated matrix by a channel source code to obtain the channel code, and finishing the coding of the channel source code.
8. An encoding design apparatus, characterized in that the encoding apparatus comprises:
the verification graph generating unit is used for receiving a channel source code to be coded and generating a first verification graph of an eIRA code with a preset code rate according to a heuristic optimization algorithm; the first check graph is used for representing the connection relation between the variable nodes and the check nodes in the eIRA code;
the check map processing unit is used for expanding the check nodes in the first check map by adopting an error correcting code to obtain a second check map; copying the second check graph, and merging the two second check graphs to obtain a third check graph; wherein, there is at most one connecting line between variable node and check node in the third check graph; mapping the third check chart to a first check matrix to obtain a supervision matrix;
a calculation output unit for outputting the calculated G.HTCalculating to obtain a generator matrix and outputting the generator matrix, wherein the generator matrix is used for encoding a channel source code to obtain a channel code; wherein G represents the supervision matrix, H represents the generation matrix, T represents transposing the matrix, and O represents a 0 matrix.
9. A computer device comprising a memory and a processor, the memory having stored therein a computer program that, when executed by the processor, causes the processor to perform the steps of the code design method of any one of claims 1 to 7.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, causes the processor to carry out the steps of the code design method according to any one of claims 1 to 7.
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