CN110768645B - Anti-hyperbolic tangent predistortion circuit, transconductor and GM-C low-pass filter - Google Patents

Anti-hyperbolic tangent predistortion circuit, transconductor and GM-C low-pass filter Download PDF

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CN110768645B
CN110768645B CN201910828917.3A CN201910828917A CN110768645B CN 110768645 B CN110768645 B CN 110768645B CN 201910828917 A CN201910828917 A CN 201910828917A CN 110768645 B CN110768645 B CN 110768645B
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transconductor
pmos tube
electrode
source
voltage
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CN110768645A (en
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李娅妮
张腾飞
朱樟明
杨银堂
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/0422—Frequency selective two-port networks using transconductance amplifiers, e.g. gmC filters
    • H03H11/0466—Filters combining transconductance amplifiers with other active elements, e.g. operational amplifiers, transistors, voltage conveyors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/0422—Frequency selective two-port networks using transconductance amplifiers, e.g. gmC filters
    • H03H11/0472—Current or voltage controlled filters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention relates to an anti-hyperbolic tangent predistortion circuit, a transconductor and a GM-C low-pass filter. The anti-hyperbolic tangent predistortion circuit includes: the first bias current unit (1), the second bias current unit (2), the first resistor (Rx 1), the first PMOS tube (PM 1), the second PMOS tube (PM 2), the first current-voltage conversion unit (3) and the second current-voltage conversion unit (4). The anti-hyperbolic tangent predistortion circuit enables the voltage difference of the input end and the voltage difference of the output end to meet the anti-hyperbolic tangent relation through the adjustment mode of converting the voltage into the current and converting the current into the voltage, can be connected to expand the input linear range of the transconductor before the input differential pair works in the transconductor in the subthreshold region, and reduces the power consumption of the transconductor unit, thereby being beneficial to the design of the low voltage and the low power consumption of the GM-C low-pass filter.

Description

Anti-hyperbolic tangent predistortion circuit, transconductor and GM-C low-pass filter
Technical Field
The invention belongs to the technical field of biomedical electronics, and particularly relates to an anti-hyperbolic tangent predistortion circuit, a transconductor and a GM-C low-pass filter.
Background
The low-pass filter is an indispensable module in the biological signal acquisition analog front-end circuit and is mainly used for filtering high-frequency noise and interference in the output noise of the low-noise instrument amplifier.
In order to ensure the quality of the output signal, the filter should have a low cut-off frequency, a large input linear range, and at the same time a small power consumption.
Since the input GM cell in the GM-C filter operates in an open loop state, it is necessary to extend its input linear range. However, the conventional input linear range expansion measures are all aimed at transistors in the GM unit, which operate in the saturation region, but the transistors have larger power consumption when operating in the saturation region, and a filter typically reaches tens of microwatts or even hundreds of microwatts, which is not beneficial to the design of low power consumption.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an anti-hyperbolic tangent predistortion circuit, a transconductor and a GM-C low-pass filter. The technical problems to be solved by the invention are realized by the following technical scheme:
the embodiment of the invention provides an anti-hyperbolic tangent predistortion circuit, which comprises: the first bias current unit, the second bias current unit, the first resistor, the first PMOS tube, the second PMOS tube, the first current-voltage conversion unit and the second current-voltage conversion unit,
the first bias current unit is connected between a voltage source and a source electrode of the first PMOS tube, a grid electrode of the first PMOS tube is connected to a first electrode of a voltage input end, and the first current-voltage conversion unit is connected between a drain electrode of the first PMOS tube and a grounding end;
the second bias current unit is connected between a voltage source and a source electrode of the second PMOS tube, a grid electrode of the second PMOS tube is connected to a second electrode of the voltage input end, and the second current-voltage conversion unit is connected between a drain electrode of the second PMOS tube and a grounding end;
the first resistor is connected between the source electrode of the first PMOS tube and the source electrode of the second PMOS tube;
the substrate of the first PMOS tube is connected with the substrate of the second PMOS tube and is commonly connected with a voltage source;
a first voltage output end is connected between the first current-voltage conversion unit and the drain electrode of the first PMOS tube, and a second voltage output end is connected between the second current-voltage conversion unit and the drain electrode of the second PMOS tube.
In one embodiment of the invention, the first bias current unit comprises a first current source, the second bias current unit comprises a second current source, wherein,
the cathode of the first current source is connected with a voltage source, and the anode of the first current source is connected with the source electrode of the first PMOS tube;
and the cathode of the second current source is connected with a voltage source, and the anode of the second current source is connected with the source electrode of the second PMOS tube.
In one embodiment of the present invention, the first bias current unit includes a third PMOS transistor, the second bias current unit includes a fourth PMOS transistor, wherein,
the source electrode and the substrate of the third PMOS tube are connected with a voltage source, the drain electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube, and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and commonly inputs a first bias voltage;
the source electrode and the substrate of the fourth PMOS tube are both connected with a voltage source, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube.
In one embodiment of the invention, the first current-to-voltage conversion unit comprises a first diode, the second current-to-voltage conversion unit comprises a second diode, wherein,
the anode of the first diode is connected with the drain electrode of the first PMOS tube, and the cathode of the first diode is connected with the grounding end;
and the positive electrode of the second diode is connected with the drain electrode of the second PMOS tube, and the negative electrode of the second diode is connected with the grounding end.
In one embodiment of the invention, the first current-to-voltage conversion unit comprises a first transistor, the second current-to-voltage conversion unit comprises a second transistor, wherein,
the emitter of the first triode is connected with the drain electrode of the first PMOS tube, and the collector of the first triode is connected with the grounding end;
the emitter of the second triode is connected with the drain electrode of the second PMOS tube, and the collector of the second triode is connected with the grounding end;
the base electrode of the first triode is connected with the base electrode of the second triode, and the base electrode of the second triode are connected with the grounding end together.
Another embodiment of the present invention provides a transconductor comprising a predistortion circuit and a transconductance unit, wherein,
the predistortion circuit comprises the anti-hyperbolic tangent predistortion circuit disclosed by the embodiment of the invention;
a first electrode of a voltage input end of the predistortion circuit is connected with a non-inverting input end of the transconductor, and a second electrode of the voltage input end of the predistortion circuit is connected with an inverting input end of the transconductor;
the first voltage output end of the predistortion circuit is connected with the inverting input end of the transconductance unit, and the second voltage output end of the predistortion circuit is connected with the non-inverting input end of the transconductance unit;
the in-phase output end of the transconductance unit is connected with the in-phase output end of the transconductor, and the anti-phase output end of the transconductance unit is connected with the anti-phase output end of the transconductor.
In one embodiment of the present invention, the transconductance unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor, wherein,
the substrate of the fifth PMOS tube, the substrate of the sixth PMOS tube, the substrate of the seventh PMOS tube, the substrate of the eighth PMOS tube and the substrate of the ninth PMOS tube are all connected to a voltage source, the source of the fifth PMOS tube, the source of the eighth PMOS tube and the source of the ninth PMOS tube are all connected to the voltage source, the grid electrode of the fifth PMOS tube inputs a second bias voltage, and the source of the sixth PMOS tube is connected to the source of the seventh PMOS tube and the drain electrode of the fifth PMOS tube;
the grid electrode of the sixth PMOS tube is connected with the first voltage output end of the predistortion circuit, the grid electrode of the seventh PMOS tube is connected with the second voltage output end of the predistortion circuit, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the second NMOS tube; the substrate and the source electrode of the first NMOS tube are both connected with the grounding end, the substrate and the source electrode of the second NMOS tube are both connected with the grounding end, the substrate and the source electrode of the third NMOS tube are both connected with the grounding end, and the substrate and the source electrode of the fourth NMOS tube are both connected with the grounding end; the drain electrode of the third NMOS tube is connected to the drain electrode of the eighth PMOS tube and the inverting output end of the transconductor, and the drain electrode of the fourth NMOS tube is connected to the drain electrode of the ninth PMOS tube and the non-inverting output end of the transconductor; and the grid electrode of the eighth PMOS tube is connected with the grid electrode of the ninth PMOS tube and commonly inputs a first common mode feedback voltage.
Yet another embodiment of the present invention provides a GM-C low pass filter comprising a first transconductor, a second transconductor, a third transconductor, a fourth transconductor, a first capacitor, a second capacitor, wherein,
at least one of the first transconductor, the second transconductor, the third transconductor, and the fourth transconductor adopts a transconductor as described in the embodiments of the present invention;
the non-inverting input end of the first transconductor is connected with the first input end of the filter, the inverting input end of the first transconductor is connected with the second input end of the filter, the non-inverting output end of the first transconductor is connected with the non-inverting output end of the second transconductor, and the inverting output end of the first transconductor is connected with the inverting output end of the second transconductor;
the non-inverting output end of the second transconductor is connected with the non-inverting input end of the third transconductor, and the inverting output end of the second transconductor is connected with the inverting input end of the third transconductor;
the first capacitor is connected between the non-inverting output end and the inverting output end of the second transconductor in a bridging way;
the non-inverting output end of the third transconductor is connected with the inverting input end of the fourth transconductor, and the inverting output end of the third transconductor is connected with the non-inverting input end of the fourth transconductor;
the in-phase output end of the fourth transconductor is connected with the inverting input end of the fourth transconductor and the inverting input end of the second transconductor, and the in-phase output end of the fourth transconductor is connected with the first output end of the filter; the inverting output end of the fourth transconductor is connected with the non-inverting input end of the fourth transconductor and the non-inverting input end of the second transconductor, and the non-inverting output end of the fourth transconductor is connected with the second output end of the filter;
the second capacitor is connected across the non-inverting output terminal and the inverting output terminal of the fourth transconductor.
In one embodiment of the present invention, the first capacitor is an adjustable capacitor, and the second capacitor is an adjustable capacitor.
Compared with the prior art, the invention has the beneficial effects that:
the predistortion circuit of the invention adopts the adjustment mode that the PMOS tube is adopted to convert the voltage into the current, and then the current-voltage conversion unit is utilized to convert the current into the voltage, so that the voltage difference of the input end and the voltage difference of the output end meet the inverse hyperbolic tangent relation, and the predistortion circuit can be connected before the transconductor working in a subthreshold region to expand the input linear range of the transconductor, reduce the power consumption of the transconductor unit, thereby being beneficial to the design of the low voltage and the low power consumption of the GM-C low-pass filter.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of an input differential structure of a transistor operating in a subthreshold region according to the prior art;
fig. 2 is a schematic structural diagram of an anti-hyperbolic tangent predistortion circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another anti-hyperbolic tangent predistortion circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure of an anti-hyperbolic tangent predistortion circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a transconductor according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another transconductor according to an embodiment of the present invention;
FIG. 7 is a simulation diagram of the relationship between the equivalent transconductance and the input differential mode voltage of the transconductance unit before and after adding the anti-hyperbolic tangent predistortion circuit in a standard 180nm CMOS process according to the embodiment of the present invention;
FIG. 8 is a schematic diagram of a GM-C low-pass filter according to an embodiment of the present invention;
FIG. 9 is a schematic signal flow diagram of a GM-C low-pass filter according to an embodiment of the present invention;
FIG. 10 is a simulation diagram of the transmission characteristics of a GM-C low-pass filter in a standard 180nm CMOS process according to an embodiment of the present invention;
FIG. 11 is a graph showing the relationship between the total harmonic distortion of a GM-C low-pass filter and the input voltage at a cut-off frequency of 180.6Hz in a standard 180nm CMOS process according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of an input differential structure of a transistor operating in a subthreshold region according to the prior art. In fig. 1, assuming that the transistors PM10 and PM11 are both operating in the sub-threshold region, there is a relationship between the drain current and the gate-source voltage according to the sub-threshold region:
in the formula (1), mu is carrier mobility, W is the gate width of the MOS tube, L is the gate length of the MOS tube, and C ox In order to form the capacitance of the oxide layer,k is Boltzmann constant, q is unit charge, T is Kelvin temperature, η is subthreshold slope, V GS And V TH The gate source voltage and the threshold voltage of the MOS tube are respectively.
Order theThen->
Thus, the first and second substrates are bonded together,
so thatAnd due to I 1 +I 2 ＝I SS (7) Wherein I 1 、I 2 、I SS Leakage currents of PM10, PM11, and PM12, respectively, V GS10 ，V GS11 Gate-source voltages of PM10 and PM11, respectively.
So that
Output current difference:
therefore, when the MOS tube works in the subthreshold region, the output current and the input differential voltage meet the hyperbolic tangent relation.
In order to realize low power consumption of the transconductor, the transistor of the transconductor needs to be made to work in a subthreshold region, so that the input linear range of the transconductor is limited. Based on the fact that the MOS transistor operates in the subthreshold region and the output current and the input differential voltage satisfy the hyperbolic tangent relationship, the present embodiment proposes an anti-hyperbolic tangent predistortion circuit to expand the input linear range of the transconductor whose input differential pair operates in the subthreshold region, please refer to fig. 2, fig. 2 is a schematic structural diagram of the anti-hyperbolic tangent predistortion circuit provided in the embodiment of the present invention, and the anti-hyperbolic tangent predistortion circuit includes a first bias current unit 1, a second bias current unit 2, a first resistor Rx1, a first PMOS transistor PM1, a second PMOS transistor PM2, a first current-voltage conversion unit 3, and a second current-voltage conversion unit 4.
The first bias current unit 1 is connected between a voltage source Vdd and a source of the first PMOS tube PM1, a gate of the first PMOS tube PM1 is connected to a first electrode of the voltage input terminal Vin, and the first current-voltage conversion unit 3 is connected between a drain of the first PMOS tube PM1 and a ground terminal; the second bias current unit 2 is connected between the voltage source Vdd and the source of the second PMOS tube PM2, the gate of the second PMOS tube PM2 is connected to the second electrode of the voltage input terminal Vin, and the second current-voltage conversion unit 4 is connected between the drain of the second PMOS tube PM2 and the ground terminal; the first resistor Rx1 is connected between the source electrode of the first PMOS tube PM1 and the source electrode of the second PMOS tube PM 2; the substrate of the first PMOS tube PM1 is connected with the substrate of the second PMOS tube PM2 and is commonly connected with a voltage source Vdd; a first voltage output end V is connected between the first current-voltage conversion unit 3 and the drain electrode of the first PMOS tube PM1 D1 A second voltage output end V is connected between the second current-voltage conversion unit 4 and the drain electrode of the second PMOS tube PM2 D2 。
In a specific embodiment, please refer to fig. 3, fig. 3 is a schematic diagram of another anti-hyperbolic tangent predistortion circuit according to an embodiment of the present invention. In the predistortion circuit, the first bias current unit 1 may be a first current source IDC1, the second bias current unit 2 may be a second current source IDC2, the first current-voltage conversion unit 3 may be a first diode D1, and the second current-voltage conversion unit 4 may be a second diode D2. In fig. 3, a negative electrode of the first current source IDC1 is connected to the voltage source Vdd, and a positive electrode is connected to the source of the first PMOS tube PM 1; the negative electrode of the second current source IDC2 is connected with a voltage source Vdd, and the positive electrode is connected with the source electrode of the second PMOS tube PM 2; the anode of the first diode D1 is connected with the drain electrode of the first PMOS tube PM1, and the cathode is connected with the grounding end; the positive pole of the second diode D2 is connected with the drain electrode of the second PMOS tube PM2, and the negative pole is connected with the grounding end.
Specifically, the principle of the predistortion circuit in fig. 3 is: the first current source IDC1 and the second current source IDC2 are used for providing stable bias current, the first PMOS tube PM1, the second PMOS tube PM2 and the first resistor Rx1 convert the input voltage of the voltage input terminal Vin into current, i.e. I1 and I2 in fig. 3, and the first diode D1 and the second diode D2 convert the current I1 and I2 into voltage, so that the output voltage difference Vd of the first diode D1 and the second diode D2 and the input voltage Vin are in an inverse hyperbolic tangent relationship.
Further, the voltage at the voltage input terminal Vin is: v (V) in ＝V GS1 -V GS2 +I X R X1 (11) If meeting I X R X1 ＞＞V GS1 -V GS2 Then:
I X R X1 ≈V in (12)
if I o1 ＝I o2 ＝I o (16) Then
Wherein V is GS1 Is the gate-source voltage, V, of the first PMOS tube PM1 GS2 Is the gate-source voltage of the second PMOS tube PM2, I X For the current of the first resistor Rx1, I o1 Is the bias current of the first current source IDC1, I o2 Is the bias current of the second current source IDC 2. I 1 ，I 2 The currents flowing through the first diode D1 and the second diode D2, respectively.
As can be seen from equation (17), the output voltage difference V of the first diode D1 and the second diode D2 d And the input voltage Vin is in an inverse hyperbolic tangent relationship.
In another embodiment, please refer to fig. 4, fig. 4 is a schematic diagram illustrating a structure of another anti-hyperbolic tangent predistortion circuit according to an embodiment of the present invention. In the predistortion circuit, the first bias current unit 1 can be a third PMOS tube PM3, the second bias current unit 2 can be a fourth PMOS tube PM4, and the functions of the PM3 and the PM4 are to provide stable bias current; the first current-voltage converting unit 3 may be a first triode Q1, and the second current-voltage converting unit 4 may be a second triode Q2, where the second transistors Q1 and Q2 are configured to convert current into voltage such that the output voltage difference Vd of the first transistors Q1 and Q2 and the input voltage Vin are in an inverse hyperbolic tangent relationship. In fig. 4, the source and the substrate of the third PMOS tube PM3 are both connected to the voltage source Vdd, the drain of the third PMOS tube PM3 is connected to the source of the first PMOS tube PM1, and the gate of the third PMOS tube PM3 is connected to the gate of the fourth PMOS tube PM4 and commonly inputs the first bias voltage Vb1; the source electrode and the substrate of the fourth PMOS tube PM4 are both connected with a voltage source Vdd, and the drain electrode of the fourth PMOS tube PM4 is connected with the source electrode of the second PMOS tube PM 2; an emitter of the first triode Q1 is connected with a drain electrode of the first PMOS tube PM1, and a collector of the first triode Q1 is connected with a grounding end; an emitter of the second triode Q2 is connected with a drain electrode of the second PMOS tube PM2, and a collector of the second triode Q2 is connected with a grounding end; the base electrode of the first triode Q1 is connected with the base electrode of the second triode Q2, and the base electrode are connected with the grounding end together.
The predistortion circuit converts input differential voltage into current through the PMOS tube and the resistor, and then the voltage difference between the input end and the output end meets the inverse hyperbolic tangent relation through the adjustment of the current-voltage conversion unit, so that the predistortion circuit with the inverse hyperbolic tangent relation can play a predistortion role before a post-stage circuit such as a transconductor with the input differential pair working in a subthreshold region, and the input linear range of the post-stage circuit is expanded.
Example two
On the basis of the first embodiment, the present embodiment provides a transconductor with an extended linear range.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a transconductor according to an embodiment of the present invention. The transconductor in fig. 5 is formed by a predistortion circuit 5 and a transconductance unit 6; please refer to the first embodiment for the circuit structure of the predistortion circuit; pre-preparationA first electrode of the voltage input end Vin of the distortion circuit 5 is connected with a non-inverting input end of the transconductor, and a second electrode of the voltage input end Vin of the predistortion circuit 5 is connected with an inverting input end of the transconductor; a first voltage output terminal V of the predistortion circuit 5 D1 An inverting input terminal of the transconductance unit 6 is connected, and a second voltage output terminal V of the predistortion circuit 5 D2 The non-inverting input end of the transconductance unit 6 is connected; the in-phase output end of the transconductance unit 6 is connected with the in-phase output end of the transconductor, and the anti-phase output end of the transconductance unit 6 is connected with the anti-phase output end of the transconductor.
In one embodiment, please refer to fig. 6, fig. 6 is a schematic structural diagram of another transconductor according to an embodiment of the present invention.
In fig. 6, the predistortion circuit of fig. 4 is employed as the predistortion circuit.
The transconductance unit 6 in fig. 6 includes a fifth PMOS pipe PM5, a sixth PMOS pipe PM6, a seventh PMOS pipe PM7, an eighth PMOS pipe PM8, a ninth PMOS pipe PM9, a first NMOS pipe NM1, a second NMOS pipe NM2, a third NMOS pipe NM3, and a fourth NMOS pipe NM4; the substrate of the fifth PMOS transistor PM5, the substrate of the sixth PMOS transistor PM6, the substrate of the seventh PMOS transistor PM7, the substrate of the eighth PMOS transistor PM8, and the substrate of the ninth PMOS transistor PM9 are all connected to the voltage source Vdd, the source of the fifth PMOS transistor PM5, the source of the eighth PMOS transistor PM8, and the source of the ninth PMOS transistor PM9 are all connected to the voltage source Vdd, the gate of the fifth PMOS transistor PM5 inputs the second bias voltage Vb2, and the source of the sixth PMOS transistor PM6 is connected to the source of the seventh PMOS transistor PM7 and the drain of the fifth PMOS transistor PM 5; the grid electrode of the sixth PMOS tube PM6 is connected with the first voltage output end V of the predistortion circuit 5 D1 The grid electrode of the seventh PMOS tube PM7 is connected with the second voltage output end V of the predistortion circuit 5 D2 The drain electrode of the sixth PMOS tube PM6 is connected to the drain electrode of the first NMOS tube NM1, the drain electrode of the first NMOS tube NM1 is connected to the grid electrode thereof, the drain electrode of the seventh PMOS tube PM7 is connected to the drain electrode of the second NMOS tube NM2, the drain electrode of the second NMOS tube NM2 is connected to the grid electrode thereof, the grid electrode of the third NMOS tube NM3 is connected to the grid electrode of the first NMOS tube NM1, and the grid electrode of the fourth NMOS tube NM4 is connected to the grid electrode of the second NMOS tube NM 2; the substrate and the source of the first NMOS tube NM1 are connected with the grounding end, the substrate and the source of the second NMOS tube NM2 are connected with the grounding end, and the third NMOS tube NM3The substrate and the source electrode are both connected with a grounding end, and the substrate and the source electrode of the fourth NMOS tube NM4 are both connected with the grounding end; the drain electrode of the third NMOS tube NM3 is connected to the drain electrode of the eighth PMOS tube PM8 and the inverting output end of the transconductor, and the drain electrode of the fourth NMOS tube NM4 is connected to the drain electrode of the ninth PMOS tube PM9 and the non-inverting output end of the transconductor; the gate of the eighth PMOS transistor PM8 is connected to the gate of the ninth PMOS transistor PM9 and commonly inputs the first common mode feedback voltage VCMFB1.
Referring to fig. 7, fig. 7 is a simulation diagram of a relationship between equivalent transconductance and input differential mode voltage before and after adding an anti-hyperbolic tangent predistortion circuit to a transconductance unit in a standard 180nm CMOS process according to an embodiment of the present invention. As can be seen from fig. 7, the linear range of the input of the post-consumer with the anti-hyperbolic tangent predistortion circuit added before the transconductance unit is significantly extended.
In this embodiment, the inverse hyperbolic tangent predistortion circuit before the transconductance unit expands the input linear range of the transconductor in which the input differential pair works in the subthreshold region, so as to reduce the power consumption of the transconductor.
Example III
On the basis of the first embodiment and the second embodiment, the present embodiment provides a GM-C low-pass filter with low power consumption.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a GM-C low-pass filter according to an embodiment of the present invention. The GM-C low-pass filter includes a first transconductor GM1, a second transconductor GM2, a third transconductor GM3, a fourth transconductor GM4, a first capacitor C1, and a second capacitor C2. At least one of the first transconductor GM1, the second transconductor GM2, the third transconductor GM3 and the fourth transconductor GM4 adopts the transconductor according to the second embodiment, preferably, the four transconductors have the same structure, and all the transconductors in the second embodiment are adopted to reduce the power consumption of the filter to the greatest extent.
Further, the non-inverting input end of the first transconductor GM1 is connected to the first input end of the filter, the inverting input end of the first transconductor GM1 is connected to the second input end of the filter, the non-inverting output end of the first transconductor GM1 is connected to the non-inverting output end of the second transconductor GM2, and the inverting output end of the first transconductor GM1 is connected to the inverting output end of the second transconductor GM 2; the in-phase output end of the second transconductor GM2 is connected with the in-phase input end of the third transconductor GM3, and the inverting output end of the second transconductor GM2 is connected with the inverting input end of the third transconductor GM 3; the first capacitor C1 is connected between the non-inverting output end and the inverting output end of the second transconductor GM2 in a bridging way; the in-phase output end of the third transconductor GM3 is connected with the inverting input end of the fourth transconductor GM4, and the inverting output end of the third transconductor GM3 is connected with the in-phase input end of the fourth transconductor GM 4; the in-phase output end of the fourth transconductor GM4 is connected to the inverting input end thereof and the inverting input end of the second transconductor GM2 and is connected to the first output end of the filter, and the inverting output end of the fourth transconductor GM4 is connected to the in-phase input end thereof and the in-phase input end of the second transconductor GM2 and is connected to the second output end of the filter; the second capacitor C2 is connected across the non-inverting output terminal and the inverting output terminal of the fourth transconductance GM 4.
Preferably, the first capacitor C1 and the second capacitor C2 are adjustable capacitors, and the cut-off frequency of the filter can be changed by adjusting the capacitance value of the adjustable capacitors, so that the filter is used for detecting bioelectric signals of different types.
In a specific embodiment, when the structures of the four transconductors are all transconductors in the second embodiment and the two capacitors are all adjustable capacitors, the signal flow of the filter is shown in fig. 9, and fig. 9 is a signal flow schematic diagram of a GM-C low-pass filter according to the embodiment of the present invention. From the signal flow in fig. 9, the transfer function of the filter can be written in conjunction with the mersen formula:
thereby obtaining the cut-off frequency of the filter as follows:
since the frequency ranges of different types of bio-signals are different, the capacitance is set to be an adjustable capacitance in order to detect the cut-off frequency of various bio-signal filters. Referring to fig. 10, fig. 10 is a simulation diagram of transmission characteristics of a GM-C low pass filter in a standard 180nm CMOS process according to an embodiment of the present invention. In fig. 10, different types of biological signals are detected by changing the cut-off frequency of the filter by changing different capacitance values; the four cut-off frequencies are 180.6Hz, 231.4Hz, 349.5Hz and 676.2Hz in sequence from low to high. Fig. 10 shows that the filter of the present embodiment can realize detection of various biological signals under the condition of low power consumption.
Referring to fig. 11, fig. 11 is a simulation diagram of a relationship between GM-C low pass filter total harmonic distortion and input voltage when the cut-off frequency is 180.6Hz in a standard 180nm CMOS process according to an embodiment of the present invention. In FIG. 11, the input signal is a sine wave with amplitude variation and frequency of 50Hz, shown as V pp The input voltage peak-to-peak value is 220mV when =220 mv@1%thd, i.e. the total harmonic distortion is one percent, it is seen that the addition of the predistortion circuit expands the input linear range of the filter.
In the embodiment, the transconductor with the expanded input linear range added into the predistortion circuit is applied to the GM-C low-pass filter, so that the input linear range of the GM-C low-pass filter is expanded, and the implementation of low voltage and low power consumption of the filter is facilitated.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (5)

1. An anti-hyperbolic tangent predistortion circuit, comprising: the first bias current unit (1), the second bias current unit (2), the first resistor (Rx 1), the first PMOS tube (PM 1), the second PMOS tube (PM 2), the first current-voltage conversion unit (3) and the second current-voltage conversion unit (4),
the first bias current unit (1) is connected between a voltage source (Vdd) and a source electrode of the first PMOS transistor (PM 1), a gate electrode of the first PMOS transistor (PM 1) is connected to a first electrode of the voltage input terminal (Vin), and the first current-voltage conversion unit (3) is connected between a drain electrode of the first PMOS transistor (PM 1) and a ground terminal;
the second bias current unit (2) is connected between a voltage source (Vdd) and a source electrode of the second PMOS transistor (PM 2), a gate electrode of the second PMOS transistor (PM 2) is connected to a second electrode of the voltage input terminal (Vin), and the second current-voltage conversion unit (4) is connected between a drain electrode of the second PMOS transistor (PM 2) and a ground terminal;
the first resistor (Rx 1) is connected between the source electrode of the first PMOS tube (PM 1) and the source electrode of the second PMOS tube (PM 2);
the substrate of the first PMOS tube (PM 1) is connected with the substrate of the second PMOS tube (PM 2) and is commonly connected with a voltage source (Vdd);
a first voltage output end (V) is connected between the first current-voltage conversion unit (3) and the drain electrode of the first PMOS tube (PM 1) D1 ) A second voltage output end (V) is connected between the second current-voltage conversion unit (4) and the drain electrode of the second PMOS tube (PM 2) D2 )；
The first bias current unit (1) comprises a first current source (IDC 1), the second bias current unit (2) comprises a second current source (IDC 2), the first current-voltage conversion unit (3) comprises a first diode (D1), and the second current-voltage conversion unit (4) comprises a second diode (D2), wherein a negative electrode of the first current source (IDC 1) is connected with a voltage source (Vdd), and a positive electrode of the first current source (IDC 1) is connected with a source of the first PMOS tube (PM 1); the cathode of the second current source (IDC 2) is connected with a voltage source (Vdd), the anode of the second current source (IDC 2) is connected with the source electrode of the second PMOS tube (PM 2), the anode of the first diode (D1) is connected with the drain electrode of the first PMOS tube (PM 1), and the cathode is connected with the grounding end; the anode of the second diode (D2) is connected with the drain electrode of the second PMOS tube (PM 2), and the cathode of the second diode is connected with the grounding end;
or, the first bias current unit (1) comprises a third PMOS tube (PM 3), the second bias current unit (2) comprises a fourth PMOS tube (PM 4), the first current-voltage conversion unit (3) comprises a first triode (Q1), the second current-voltage conversion unit (4) comprises a second triode (Q2), wherein a source electrode and a substrate of the third PMOS tube (PM 3) are both connected with a voltage source (Vdd), a drain electrode of the third PMOS tube (PM 3) is connected with a source electrode of the first PMOS tube (PM 1), a gate electrode of the third PMOS tube (PM 3) is connected with a gate electrode of the fourth PMOS tube (PM 4), and a first bias voltage (Vb 1) is commonly input; the source electrode and the substrate of the fourth PMOS tube (PM 4) are connected with a voltage source (Vdd), and the drain electrode of the fourth PMOS tube (PM 4) is connected with the source electrode of the second PMOS tube (PM 2); an emitter of the first triode (Q1) is connected with a drain electrode of the first PMOS tube (PM 1), and a collector of the first triode (Q1) is connected with a grounding end; an emitter of the second triode (Q2) is connected with a drain electrode of the second PMOS tube (PM 2), and a collector of the second triode (Q2) is connected with a grounding end; the base electrode of the first triode (Q1) is connected with the base electrode of the second triode (Q2), and the base electrode are connected with the grounding end together.
2. Transconductor, characterized by comprising a predistortion circuit (5) and a transconductance unit (6), wherein,
-said predistortion circuit (5) comprises an anti-hyperbolic tangent predistortion circuit as claimed in claim 1;
a first electrode of a voltage input end (Vin) of the predistortion circuit (5) is connected with a non-inverting input end of the transconductor, and a second electrode of the voltage input end (Vin) of the predistortion circuit (5) is connected with an inverting input end of the transconductor;
a first voltage output (V) of the predistortion circuit (5) D1 ) Is connected to the inverting input of the transconductance cell (6), and the second voltage output (V) of the predistortion circuit (5) D2 ) -connecting the non-inverting input of the transconductance unit (6);
the non-inverting output end of the transconductance unit (6) is connected with the non-inverting output end of the transconductor, and the inverting output end of the transconductance unit (6) is connected with the inverting output end of the transconductor.
3. Transconductor according to claim 2, characterized in that said transconductance unit (6) comprises a fifth PMOS transistor (PM 5), a sixth PMOS transistor (PM 6), a seventh PMOS transistor (PM 7), an eighth PMOS transistor (PM 8), a ninth PMOS transistor (PM 9), a first NMOS transistor (NM 1), a second NMOS transistor (NM 2), a third NMOS transistor (NM 3) and a fourth NMOS transistor (NM 4), wherein,
the substrate of the fifth PMOS tube (PM 5), the substrate of the sixth PMOS tube (PM 6), the substrate of the seventh PMOS tube (PM 7), the substrate of the eighth PMOS tube (PM 8) and the substrate of the ninth PMOS tube (PM 9) are all connected to a voltage source (Vdd), the source of the fifth PMOS tube (PM 5), the source of the eighth PMOS tube (PM 8) and the source of the ninth PMOS tube (PM 9) are all connected to the voltage source (Vdd), the grid of the fifth PMOS tube (PM 5) inputs a second bias voltage (Vb 2), and the source of the sixth PMOS tube (PM 6) is connected to the source of the seventh PMOS tube (PM 7) and the drain of the fifth PMOS tube (PM 5);
the grid electrode of the sixth PMOS tube (PM 6) is connected with the first voltage output end (V) of the predistortion circuit (5) D1 ) The grid electrode of the seventh PMOS tube (PM 7) is connected with the second voltage output end (V) of the predistortion circuit (5) D2 ) The drain electrode of the sixth PMOS tube (PM 6) is connected to the drain electrode of the first NMOS tube (NM 1), the drain electrode of the first NMOS tube (NM 1) is connected to the grid electrode thereof, the drain electrode of the seventh PMOS tube (PM 7) is connected to the drain electrode of the second NMOS tube (NM 2), the drain electrode of the second NMOS tube (NM 2) is connected to the grid electrode thereof, the grid electrode of the third NMOS tube (NM 3) is connected to the grid electrode of the first NMOS tube (NM 1), and the grid electrode of the fourth NMOS tube (NM 4) is connected to the grid electrode of the second NMOS tube (NM 2); the substrate and the source of the first NMOS tube (NM 1) are both connected with a grounding end, the substrate and the source of the second NMOS tube (NM 2) are both connected with the grounding end, the substrate and the source of the third NMOS tube (NM 3) are both connected with the grounding end, and the substrate and the source of the fourth NMOS tube (NM 4) are both connected with the grounding end; the drain electrode of the third NMOS tube (NM 3) is connected to the drain electrode of the eighth PMOS tube (PM 8) and the inverting output end of the transconductor, and the drain electrode of the fourth NMOS tube (NM 4) is connected to the drain electrode of the ninth PMOS tube (PM 9) and the inverting output end of the transconductor; the grid electrode of the eighth PMOS tube (PM 8) is connected with the grid electrode of the ninth PMOS tube (PM 9) and commonly inputs a first common mode feedback voltage (VCMFB 1).
4. A GM-C low-pass filter, comprising a first transconductor (GM 1), a second transconductor (GM 2), a third transconductor (GM 3), a fourth transconductor (GM 4), a first capacitor (C1), a second capacitor (C2), wherein,
-at least one of the first transconductor (GM 1), the second transconductor (GM 2), the third transconductor (GM 3), the fourth transconductor (GM 4) employing a transconductor according to any one of claims 2 to 3;
the non-inverting input end of the first transconductor (GM 1) is connected with the first input end of the filter, the inverting input end of the first transconductor (GM 1) is connected with the second input end of the filter, the non-inverting output end of the first transconductor (GM 1) is connected with the non-inverting output end of the second transconductor (GM 2), and the inverting output end of the first transconductor (GM 1) is connected with the inverting output end of the second transconductor (GM 2);
the non-inverting output end of the second transconductor (GM 2) is connected with the non-inverting input end of the third transconductor (GM 3), and the inverting output end of the second transconductor (GM 2) is connected with the inverting input end of the third transconductor (GM 3);
the first capacitor (C1) is connected across the non-inverting output terminal and the inverting output terminal of the second transconductor (GM 2);
the non-inverting output end of the third transconductor (GM 3) is connected with the inverting input end of the fourth transconductor (GM 4), and the inverting output end of the third transconductor (GM 3) is connected with the non-inverting input end of the fourth transconductor (GM 4);
the in-phase output end of the fourth transconductor (GM 4) is connected with the inverting input end of the fourth transconductor (GM 4) and the inverting input end of the second transconductor (GM 2), and the in-phase output end of the fourth transconductor (GM 4) is connected with the first output end of the filter; the inverting output end of the fourth transconductor (GM 4) is connected to the non-inverting input end thereof and the non-inverting input end of the second transconductor (GM 2), and the inverting output end of the fourth transconductor (GM 4) is connected to the second output end of the filter;
the second capacitor (C2) is connected across the non-inverting output and the inverting output of the fourth transconductor (GM 4).
5. GM-C low-pass filter according to claim 4, wherein said first capacitance (C1) is a tunable capacitance and said second capacitance (C2) is a tunable capacitance.
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