CN110768554A - Cascaded multi-level inverter and control method thereof - Google Patents
Cascaded multi-level inverter and control method thereof Download PDFInfo
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- CN110768554A CN110768554A CN201911086193.6A CN201911086193A CN110768554A CN 110768554 A CN110768554 A CN 110768554A CN 201911086193 A CN201911086193 A CN 201911086193A CN 110768554 A CN110768554 A CN 110768554A
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- 238000003379 elimination reaction Methods 0.000 claims description 3
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- 238000005457 optimization Methods 0.000 description 3
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
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Abstract
The invention discloses a cascade multilevel inverter and a control method thereof, for the cascade multilevel inverter, each cascade unit usually needs an independent direct current voltage source for power supply, the cost is higher, the volume is larger, and the invention only adopts one direct current voltage source to simultaneously supply power for a plurality of cascade units. The direct-current voltage is converted into direct-current voltage pulses with adjustable pulse width through a power electronic switching device, then the multiple paths of direct-current voltage pulses are output by a high-frequency transformer to supply power to the cascade unit, and the effect same as that of the power supply of a plurality of independent direct-current voltage sources can be achieved. The invention can realize that one direct current voltage source is used for supplying power to a plurality of cascade units simultaneously, thereby reducing the cost of the system, and the volume of the system is greatly reduced by adopting the high-frequency transformer; and because the pulse width of the direct current voltage is adjustable, the front-stage voltage and speed regulation can be realized in the motor speed regulation system, the modulation ratio is fixed at the rear stage, and the control is flexible.
Description
Technical Field
The invention relates to the technical field of power electronics and power transmission, in particular to a cascade multilevel inverter and a control method thereof.
Background
The cascaded multi-level inverter is formed by cascading a plurality of identical power units, and usually, an independent direct-current power supply exists in each unit. For the cascade multilevel inverter, in the main circuit of the cascade multilevel inverter, the problem of capacitor voltage sharing in a diode clamp type inverter circuit can not exist, so the control is much simpler. Compared with a flying capacitor type inverter, the flying capacitor type inverter has no intermediate direct current voltage deviation problem because the main circuit does not use a capacitor as a clamper as the flying capacitor type inverter. When a certain cascade unit is damaged, the unit bypass can be degraded and used, and the normal operation of the whole inverter is not influenced, so that the stability and fault tolerance of the inverter are improved. And the control of the inverter can be achieved by modulating and controlling each basic power unit, so that the control is simpler and the expansion is easier.
However, each cascaded module of the cascaded multi-level inverter generally needs an independent dc power supply, and the system is large in size and high in cost, which also limits the number of cascaded multi-level.
Disclosure of Invention
The invention aims to solve the technical problem of the background technology and provides a cascade multilevel inverter and a control method thereof.
The invention adopts the following technologies to solve the technical problems:
a cascade multilevel inverter comprises a first preceding stage switch tube, a second preceding stage switch tube, a preceding stage capacitor, a high-frequency transformer, 3n following stage capacitors and 3n cascade units, wherein n is an integer greater than or equal to 1;
the cascade unit adopts an H-bridge structure or a half-bridge structure and comprises a first output end and a second output end;
one end of the primary side of the high-frequency transformer is connected with one end of the preceding-stage capacitor, and the other end of the primary side of the high-frequency transformer is respectively connected with one end of the second preceding-stage switching tube and one end of an external direct-current voltage source;
the other end of the second pre-stage switch tube is respectively connected with the other end of the pre-stage capacitor and one end of the first pre-stage switch tube;
the other end of the first pre-stage switching tube is connected with the other end of an external direct-current voltage source;
the high-frequency transformer comprises 3n output secondary sides, wherein one end of the ith output secondary side is connected with the positive electrode of the bus voltage of the ith cascade unit through an ith rear-stage capacitor, the negative electrode of the bus voltage of the ith cascade unit is connected with the other end of the ith output secondary side, and i is an integer which is greater than or equal to 1 and less than or equal to n;
when n is 1, the second output ends of the three cascade units are connected with each other, and the first output ends of the three cascade units are respectively the output ends of the A phase, the B phase and the C phase of the cascade multilevel inverter;
when n is an integer greater than or equal to 2, the second output end of the jth cascade unit is connected with the first output end of the j +1 th cascade unit, the second output end of the jth + n cascade unit is connected with the first output end of the j +1+ n cascade unit, the second output end of the j +2n cascade unit is connected with the first output end of the j +1+2n cascade unit, and j is an integer greater than or equal to 1 and less than or equal to n-1; and the second output end of the nth cascade unit is respectively connected with the second output ends of the 2 nth and 3 nth cascade units, and the first output ends of the 1 st, n +1 th and 2n +1 th cascade units are respectively the A-phase, B-phase and C-phase output ends of the cascade multilevel inverter.
The invention also discloses a control method of the cascade multilevel inverter, wherein the three-phase output end of the cascade multilevel inverter is respectively and correspondingly connected with the three-phase input end of the alternating current motor, and the control method comprises the following specific steps:
step 1), obtaining phase current of an alternating current motor;
step 2), obtaining a position signal of the alternating current motor and calculating the rotating speed of the alternating current motor;
step 3), phase current, rotating speed, position signals and a preset modulation ratio of the alternating current motor are modulated to generate first PWM signals so as to control switch tubes in the 3n cascade units;
and 4) modulating phase current, rotating speed and position signals of the alternating current motor to generate a second PWM signal, and controlling the first pre-stage switching tube and the second pre-stage switching tube.
As a further optimization scheme of the control method of the cascade multi-level inverter, in the step 2), a position sensor is arranged in the alternating current motor to calculate a real-time position angle of the alternating current motor.
As a further optimization scheme of the control method of the cascade multi-level inverter, in the step 2), a position-free algorithm is adopted to calculate the real-time position angle of the alternating current motor according to the input current and the input voltage of the alternating current motor.
As a further optimization scheme of the control method of the cascade multi-level inverter, any one of an SPWM asynchronous modulation strategy, an SVPWM asynchronous modulation strategy, a synchronous SVPWM and a specific harmonic elimination PWM synchronous modulation strategy is adopted during modulation in the step 3) and the step 4).
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
1. the direct-current power supply can supply power to a plurality of cascade unit modules at the same time, so that the volume and the cost of the system are reduced;
2. a high-frequency transformer with multi-path output is adopted, so that the size is small;
3. the pulse width output by the high-frequency transformer is adjustable, the algorithm of the front-stage voltage regulation and speed regulation and the rear-stage fixed modulation ratio can be realized, and the control is flexible.
Drawings
FIG. 1 is a schematic view of the present invention;
FIG. 2 is a diagram of the transformation of voltage pulses according to the present invention (the turns ratio of the high frequency transformer is 1 as an example);
FIG. 3 is a logic diagram of the algorithm of the present invention.
Detailed Description
The technical scheme of the invention is further explained in detail by combining the attached drawings:
the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, components are exaggerated for clarity.
As shown in fig. 1, a cascaded multi-level inverter includes a first pre-stage switching tube, a second pre-stage switching tube, a pre-stage capacitor, a high-frequency transformer, 3n post-stage capacitors, and 3n cascaded units, where n is an integer greater than or equal to 1;
the cascade unit adopts an H-bridge structure or a half-bridge structure and comprises a first output end and a second output end;
one end of the primary side of the high-frequency transformer is connected with one end of the preceding-stage capacitor, and the other end of the primary side of the high-frequency transformer is respectively connected with one end of the second preceding-stage switching tube and one end of an external direct-current voltage source;
the other end of the second pre-stage switch tube is respectively connected with the other end of the pre-stage capacitor and one end of the first pre-stage switch tube;
the other end of the first pre-stage switching tube is connected with the other end of an external direct-current voltage source;
the high-frequency transformer comprises 3n output secondary sides, wherein one end of the ith output secondary side is connected with the positive electrode of the bus voltage of the ith cascade unit through an ith rear-stage capacitor, the negative electrode of the bus voltage of the ith cascade unit is connected with the other end of the ith output secondary side, and i is an integer which is greater than or equal to 1 and less than or equal to n;
when n is 1, the second output ends of the three cascade units are connected with each other, and the first output ends of the three cascade units are respectively the output ends of the A phase, the B phase and the C phase of the cascade multilevel inverter;
when n is an integer greater than or equal to 2, the second output end of the jth cascade unit is connected with the first output end of the j +1 th cascade unit, the second output end of the jth + n cascade unit is connected with the first output end of the j +1+ n cascade unit, the second output end of the j +2n cascade unit is connected with the first output end of the j +1+2n cascade unit, and j is an integer greater than or equal to 1 and less than or equal to n-1;
and the second output end of the nth cascade unit is respectively connected with the second output ends of the 2 nth and 3 nth cascade units, and the first output ends of the 1 st, n +1 th and 2n +1 th cascade units are respectively the A-phase, B-phase and C-phase output ends of the cascade multilevel inverter.
Fig. 2 shows the transformation of voltage pulses at various nodes of the circuit topology.
As shown in fig. 3, the present invention also discloses a control method of the cascade multilevel inverter, wherein three-phase output ends of the cascade multilevel inverter are respectively and correspondingly connected with three-phase input ends of an alternating current motor, the preceding stage regulates voltage and speed, and the subsequent stage fixes the modulation ratio, the control method comprises the following specific steps:
step 1), obtaining phase current of an alternating current motor;
step 2), obtaining a position signal of the alternating current motor and calculating the rotating speed of the alternating current motor;
step 3), phase current, rotating speed, position signals and a preset modulation ratio of the alternating current motor are modulated to generate first PWM signals so as to control switch tubes in the 3n cascade units;
and 4) modulating phase current, rotating speed and position signals of the alternating current motor to generate a second PWM signal, and controlling the first pre-stage switching tube and the second pre-stage switching tube.
In the step 2), the real-time position angle of the alternating current motor can be calculated by arranging a position sensor in the alternating current motor, or the real-time position angle of the alternating current motor can be calculated by adopting a position-free algorithm according to the input current and the input voltage of the alternating current motor.
When modulation is performed in the step 3) and the step 4), any one of an SPWM asynchronous modulation strategy, an SVPWM asynchronous modulation strategy, a synchronous SVPWM and a specific harmonic elimination PWM synchronous modulation strategy can be adopted.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only illustrative of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A cascade multilevel inverter is characterized by comprising a first preceding stage switch tube, a second preceding stage switch tube, a preceding stage capacitor, a high-frequency transformer, 3n following stage capacitors and 3n cascade units, wherein n is an integer greater than or equal to 1;
the cascade unit adopts an H-bridge structure or a half-bridge structure and comprises a first output end and a second output end;
one end of the primary side of the high-frequency transformer is connected with one end of the preceding-stage capacitor, and the other end of the primary side of the high-frequency transformer is respectively connected with one end of the second preceding-stage switching tube and one end of an external direct-current voltage source;
the other end of the second pre-stage switch tube is respectively connected with the other end of the pre-stage capacitor and one end of the first pre-stage switch tube;
the other end of the first pre-stage switching tube is connected with the other end of an external direct-current voltage source;
the high-frequency transformer comprises 3n output secondary sides, wherein one end of the ith output secondary side is connected with the positive electrode of the bus voltage of the ith cascade unit through an ith rear-stage capacitor, the negative electrode of the bus voltage of the ith cascade unit is connected with the other end of the ith output secondary side, and i is an integer which is greater than or equal to 1 and less than or equal to n;
when n is 1, the second output ends of the three cascade units are connected with each other, and the first output ends of the three cascade units are respectively the output ends of the A phase, the B phase and the C phase of the cascade multilevel inverter;
when n is an integer greater than or equal to 2, the second output end of the jth cascade unit is connected with the first output end of the j +1 th cascade unit, the second output end of the jth + n cascade unit is connected with the first output end of the j +1+ n cascade unit, the second output end of the j +2n cascade unit is connected with the first output end of the j +1+2n cascade unit, and j is an integer greater than or equal to 1 and less than or equal to n-1; and the second output end of the nth cascade unit is respectively connected with the second output ends of the 2 nth and 3 nth cascade units, and the first output ends of the 1 st, n +1 th and 2n +1 th cascade units are respectively the A-phase, B-phase and C-phase output ends of the cascade multilevel inverter.
2. The method for controlling the cascaded multi-level inverter according to claim 1, wherein three-phase output terminals of the cascaded multi-level inverter are respectively and correspondingly connected with three-phase input terminals of an alternating current motor, and the method comprises the following specific steps:
step 1), obtaining phase current of an alternating current motor;
step 2), obtaining a position signal of the alternating current motor and calculating the rotating speed of the alternating current motor;
step 3), phase current, rotating speed, position signals and a preset modulation ratio of the alternating current motor are modulated to generate first PWM signals so as to control switch tubes in the 3n cascade units;
and 4) modulating phase current, rotating speed and position signals of the alternating current motor to generate a second PWM signal, and controlling the first pre-stage switching tube and the second pre-stage switching tube.
3. The method of claim 1, wherein the step 2) is performed by calculating a real-time position angle of the ac motor by providing a position sensor in the ac motor.
4. The method as claimed in claim 1, wherein the step 2) calculates the real-time position angle of the ac motor by using a position-free algorithm according to the input current and the input voltage of the ac motor.
5. The method for controlling a cascaded multi-level inverter according to claim 1, wherein any one of an SPWM asynchronous modulation strategy, an SVPWM asynchronous modulation strategy, a synchronous SVPWM and a specific harmonic elimination PWM synchronous modulation strategy is adopted when modulation is performed in step 3) and step 4).
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