CN110767738B

CN110767738B - Display device, display panel and manufacturing method thereof

Info

Publication number: CN110767738B
Application number: CN201911153855.7A
Authority: CN
Inventors: 胡迎宾; 赵策; 王明; 丁远奎; 宋威; 闫梁臣
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2019-11-22
Filing date: 2019-11-22
Publication date: 2021-12-03
Anticipated expiration: 2039-11-22
Also published as: US10916615B1; CN110767738A

Abstract

The present disclosure relates to a display device, a display panel and a manufacturing method thereof, the display panel comprises a substrate, a conductive layer, a grid insulating layer, a grid layer, an interlayer dielectric layer and a routing layer, wherein the conductive layer is arranged on one side of the substrate; the grid insulating layer is arranged on one side of the conducting layer far away from the substrate; the grid layer is arranged on one side of the grid insulating layer, which is far away from the substrate, and the thickness of the grid layer is greater than that of the conducting layer; the grid electrode layer comprises a plurality of grid lines, the grid lines are provided with grooves which extend towards the substrate and cut off the grid lines, the grooves are opposite to the conducting layer, and the grid lines disconnected at the two sides of the grooves respectively penetrate through the grid insulating layer and are connected with the conducting layer; the interlayer dielectric layer is arranged on one side of the gate layer away from the substrate, covers the conductive layer and fills the groove; the wiring layer is arranged on one side, far away from the substrate, of the interlayer dielectric layer and comprises a plurality of auxiliary electrode wires, the orthographic projections of the auxiliary electrode wires on the grid electrode layer are intersected with the grid electrode wires in the grooves, and the orthographic projections of the intersected parts on the grid electrode layer are completely positioned in the grooves.

Description

Display device, display panel and manufacturing method thereof

Technical Field

The disclosure relates to the technical field of display, in particular to a display panel, a manufacturing method of the display panel and a display device.

Background

An Organic Light Emitting Diode (OLED) display panel has been classified as a next generation display technology with great development prospects due to its advantages of being thin, light, wide in viewing angle, active in light emission, continuously adjustable in light emission color, fast in response speed, small in energy consumption, simple in production process, high in light emission efficiency, capable of flexible display, and the like, and is widely applied to various electronic products.

At present, an OLED display panel is divided into a top emission structure and a bottom emission structure, in the top emission structure, light emitted by the OLED display panel is transmitted from a cathode direction, so that a cathode of the top emission OLED panel needs to use a transparent conductive material, but since an OLED cathode material itself has a certain resistance value, when the size of the OLED panel is large, the resistance of the OLED cathode material itself can cause voltage drop, resulting in the reduction of display brightness of the panel.

In the prior art, an auxiliary cathode is usually adopted to reduce the resistance value of a cathode, auxiliary cathode wiring is completed on a source-drain wiring layer of a thin film transistor, a passivation layer and a flat layer are usually arranged on the source-drain wiring layer, and the passivation layer and the flat layer need to be subjected to hole opening etching to complete auxiliary cathode wiring lap joint. However, at the position of the auxiliary cathode hole, which is close to the upper side of the gate trace, the thickness of the planarization layer in the conductive hole is different.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a display panel, a method for manufacturing the same, and a display device including the same, which can improve the uniformity of the thickness of a planarization layer, thereby effectively avoiding the occurrence of poor etching on a routing layer.

According to an aspect of the present disclosure, there is provided a display panel including:

a substrate;

the conducting layer is arranged on one side of the substrate;

the grid insulating layer is arranged on one side, far away from the substrate, of the conducting layer;

the grid electrode layer is arranged on one side, far away from the substrate, of the grid electrode insulating layer, and the thickness of the grid electrode layer is larger than that of the conducting layer; the grid electrode layer comprises a plurality of grid lines, grooves which extend towards the substrate and cut off the grid lines are formed in the grid lines, the grooves are opposite to the conducting layer, and the grid lines disconnected at two sides of the grooves respectively penetrate through the grid insulating layer and are connected with the conducting layer;

the interlayer dielectric layer is arranged on one side of the gate layer, which is far away from the substrate, covers the conductive layer and fills the groove;

the wiring layer is arranged on one side, far away from the substrate, of the interlayer dielectric layer and comprises a plurality of auxiliary electrode wires; the orthographic projection of the auxiliary electrode line on the gate layer intersects with the orthographic projection of the gate line on the groove, and the intersecting part is completely positioned in the groove.

In an exemplary embodiment of the present disclosure, the conductive layer is a light-shielding conductive material.

In an exemplary embodiment of the present disclosure, the display panel further includes:

the passivation layer is arranged on one side of the interlayer dielectric layer, which is far away from the substrate, and covers the conducting layer;

and the flat layer is arranged on one side of the passivation layer, which is far away from the substrate, and the passivation layer and the flat layer are provided with via holes communicated with the auxiliary electrode wires.

the buffer layer is arranged between the substrate and the grid electrode insulating layer and covers the conducting layer, and the groove penetrates through the grid electrode insulating layer and is communicated with the buffer layer.

In one exemplary embodiment of the present disclosure, the conductive layer has a thickness of 0.1 μm to 0.2 μm.

According to another aspect of the present disclosure, there is provided a manufacturing method of a display panel, the manufacturing method including:

providing a substrate;

forming a conductive layer on one side of the substrate;

forming a gate insulating layer on one side of the conductive layer, which is far away from the substrate;

forming a gate electrode layer on one side of the gate insulating layer, which is far away from the substrate, and enabling the thickness of the gate electrode layer to be larger than that of the conductive layer, wherein the gate electrode layer comprises a plurality of gate lines;

forming a groove which extends towards the substrate and cuts off the gate line on the gate line, enabling the groove to be opposite to the conductive layer, and enabling the gate line disconnected at two sides of the groove to penetrate through the gate insulating layer and be connected with the conductive layer respectively;

forming an interlayer dielectric layer on one side of the gate layer, which is far away from the substrate, wherein the interlayer dielectric layer covers the conductive layer and fills the groove;

and forming a routing layer on one side of the interlayer dielectric layer, which is far away from the substrate, wherein the routing layer comprises a plurality of auxiliary electrode wires, so that the orthographic projections of the auxiliary electrode wires on the gate electrode layer are intersected with the orthographic projections of the gate electrode wires in the groove, and the intersected parts of the auxiliary electrode wires on the gate electrode layer are completely positioned in the groove.

In an exemplary embodiment of the present disclosure, after forming the conductive layer on the side of the substrate, before forming the gate insulating layer on the side of the conductive layer away from the substrate, the manufacturing method further includes:

and forming a buffer layer covering the conductive layer on one side of the substrate provided with the conductive layer.

In an exemplary embodiment of the present disclosure, forming a groove extending toward the substrate and intercepting the gate line at the gate line includes:

and forming a groove which extends towards the substrate and cuts off the gate line on the gate line, wherein the groove penetrates through the gate insulating layer and is communicated with the buffer layer.

In an exemplary embodiment of the present disclosure, the manufacturing method further includes:

forming a passivation layer covering the conducting layer on one side of the interlayer dielectric layer far away from the substrate;

forming a flat layer on one side of the passivation layer far away from the substrate;

and forming a via hole communicated with the auxiliary electrode wire on the passivation layer and the flat layer.

According to still another aspect of the present disclosure, there is provided a display device including the display panel described above.

According to the display panel provided by the disclosure, the crossed part of the gate line and the auxiliary electrode line is disconnected, and the two disconnected ends of the gate line are respectively and electrically connected through the conducting layer; after the grid line disconnection, the below that auxiliary electrode line corresponds does not have the grid line, and because the thickness of conducting layer and grid insulating layer is less, consequently, the auxiliary electrode line can reduce with the relative substrate's of crossing position of grid line extending direction height, thereby make the difference in height between each position of auxiliary electrode line reduce, and then, when the grid layer forms the flat bed, can effectively alleviate the problem that auxiliary electrode line leads to the uneven thickness of flat bed, thereby when forming the via hole of overlap joint auxiliary electrode line through the sculpture on the flat bed, can effectively fall and avoid appearing causing the phenomenon of sculpture badly to the routing layer.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a top view of a display panel provided in an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view taken along plane A-A of FIG. 1;

FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1;

fig. 4 is a flowchart of a method for manufacturing a display panel according to an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, steps, etc. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

The applicant finds that an auxiliary cathode array process is adopted for 8K top emission printing of an OLED product, auxiliary cathode wiring is completed on a source and drain wiring layer of a thin film transistor, a passivation layer and a flat layer are usually arranged on the source and drain wiring layer, and the passivation layer and the flat layer need to be subjected to hole opening etching to complete auxiliary cathode wiring lap joint. At the position of the auxiliary cathode hole, the position of the auxiliary cathode hole is close to the upper part of the grid wire, the thicknesses of the flat layers in the auxiliary cathode hole are different, the thickness difference of the flat layers is about 1 mu m which is the total thickness of the grid wire and the grid insulating layer, so that the over-etching amount of the dry etching process on the grid is too large, the over-etching of the auxiliary cathode wire is caused, and if the auxiliary cathode wire is formed by adopting a copper process, the oxidation is easily generated; if the auxiliary cathode wire is formed by adopting an aluminum process, the auxiliary cathode wire is easy to be etched and broken, and a Gate line and Data line Short circuit (DGS) type defect is easy to be generated in an overlapped area of the Gate wire and the auxiliary cathode wire.

First, in the present exemplary embodiment, there is provided a display panel, as shown in fig. 1 to 3, including: the semiconductor device comprises a substrate 10, a conducting layer 20, a gate insulating layer 40, a gate layer 50, an interlayer dielectric layer 60 and a wiring layer 70, wherein the conducting layer 20 is arranged on one side of the substrate 10, and the gate insulating layer 40 is arranged on one side, far away from the substrate 10, of the conducting layer 20; the gate layer 50 is arranged on one side of the gate insulating layer 40 far away from the substrate 10, and the thickness of the gate layer 50 is greater than that of the conductive layer 20; the gate layer 50 includes a plurality of gate lines, the gate lines are formed with a groove 510 extending toward the substrate 10 and cutting off the gate line 50, the groove 510 is opposite to the conductive layer, that is, the orthographic projection of the groove 510 is located on the conductive layer 20, and the gate lines disconnected at two sides of the groove 510 respectively penetrate through the gate insulating layer 40 and are connected with the conductive layer 20; the interlayer dielectric layer 60 is arranged on one side of the gate layer 50 far away from the substrate 10, covers the conductive layer 20 and fills the groove 510; the routing layer 70 is arranged on one side of the interlayer dielectric layer 60 far away from the substrate 10, and the routing layer 70 comprises a plurality of auxiliary electrode wires; the orthographic projection of the auxiliary electrode line on the gate layer 50 intersects the gate line on the groove 510, and the orthographic projection of the intersecting part is completely positioned in the groove 510, i.e. the orthographic projection of the gate line and the auxiliary electrode line on the substrate 10 is completely staggered.

In the display panel provided by the present disclosure, the intersecting portion of the gate line and the auxiliary electrode line is disconnected, and the two disconnected ends of the gate line are electrically connected through the conductive layer 20, respectively; after the gate line disconnection, the below that the auxiliary electrode line corresponds does not have the gate line, and because conducting layer 20 is less with the thickness of grid insulating layer 40, consequently, the height of the relative substrate 10 in the crossing position of auxiliary electrode line and gate line extending direction can reduce, thereby make the difference in height between each position of auxiliary electrode line reduce, and then, when gate layer 50 forms flat layer 90, can effectively alleviate the problem that the auxiliary electrode line leads to flat layer 90 uneven thickness, thereby when forming via hole 910 of overlap joint auxiliary electrode line through the sculpture on flat layer 90, can effectively fall and avoid appearing causing the phenomenon of bad etching to walking layer 70.

In addition, two insulating layers, namely the gate insulating layer 40 and the interlayer dielectric layer 60, exist between the auxiliary electrode line and the conductive layer 20, so that the risk of short circuit between the auxiliary electrode line and the conductive layer 20 can be reduced, namely the DGS risk is basically solved.

The material of the substrate 10 may be an inorganic material, such as a glass material, e.g., soda-lime glass, quartz glass, sapphire glass, or a metal material of various metals, e.g., stainless steel, aluminum, nickel, or an alloy thereof; and may also be an organic material such as polymethylmethacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, or a combination thereof; the material of the gate insulating layer 40 may be silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymer compounds), or a combination thereof; the material of the gate layer 50 may be metal, conductive metal oxide, conductive polymer, conductive composite material, or a combination thereof. For example, the metal can be platinum, gold, silver, aluminum, chromium, nickel, titanium, magnesium, iron, manganese, or combinations thereof; the conductive metal oxide may be Indium Tin Oxide (ITO), fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), or a combination thereof; the material of the interlayer dielectric layer 60 may be silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymer compounds) or a combination thereof; the routing layer 70 includes a plurality of auxiliary electrode lines, each of the auxiliary electrode lines is connected to a plurality of auxiliary electrodes, the auxiliary electrode lines may be auxiliary cathode lines or auxiliary anode lines, the routing layer 70 may further include source/drain electrode routing lines, the routing layer 70 may be made of metal, conductive oxide or a combination thereof, for example, the metal may be titanium, platinum, gold, silver, aluminum, tungsten, copper, or an alloy thereof or a combination thereof, and the conductive oxide may be IZO, AZO, ITO, GZO, ZTO or a combination thereof. The present disclosure is only illustrative of the materials of the above layers, and the materials of the above layers are not limited, and it is a matter of course that those skilled in the art can select materials other than the above listed materials to form the above layers, and the present disclosure is not limited thereto.

Specifically, the conductive layer 20 is a light-shielding conductive material, i.e., the conductive layer 20 can also serve as a light-shielding layer. The material of the conductive layer 20 may be at least one of copper, aluminum, molybdenum, titanium, chromium, and tungsten.

Specifically, as shown in fig. 2, the display panel further includes a buffer layer 30, and the buffer layer 30 is disposed between the substrate 10 and the gate insulating layer 40 and covers the conductive layer 20. The sum of the thicknesses of the buffer layer 30 and the interlayer dielectric layer 60 between the auxiliary electrode line and the conductive layer 20 is 1 μm-1.5 μm, so that two insulating layers of the interlayer dielectric layer 60 and the buffer layer 30 exist between the auxiliary electrode line and the conductive layer 20, the risk of short circuit between the auxiliary electrode line and the conductive layer 20 can be reduced, and the DGS risk is basically solved. The material of the buffer layer 30 may be an insulating material such as silicon oxide, silicon nitride, etc., which is not limited in this disclosure.

Specifically, the groove 510 extends into the gate insulating layer 40 toward the substrate 10, so that the height of the auxiliary electrode line relative to the substrate 10 at the position corresponding to the groove 510 can be further reduced, the thickness of the flat layer 90 on the auxiliary electrode line is more uniform, and the phenomenon of poor etching caused by the wiring layer 70 is further effectively avoided.

Further, the groove 510 penetrates the gate insulating layer 40, and when the buffer layer 30 is disposed on the substrate 10, the groove 510 communicates with the buffer layer 30. The penetration of the groove 510 through the gate insulating layer 40 can further reduce the height of the auxiliary electrode line corresponding to the groove 510 relative to the substrate 10, and the difference h1-h2 of the uneven thickness of the planarization layer 90 caused by the auxiliary electrode line is equal to the thickness of the conductive layer 20. Wherein, the thickness of conducting layer 20 is 0.1 μm-0.2 μm, and it can be seen that, through the arrangement of the present disclosure, the thickness difference of the flat layer 90 can be reduced by one order of magnitude, thereby greatly improving the thickness uniformity of the flat layer 90, more effectively avoiding the occurrence of poor etching on the routing layer 70, and ensuring the reliability of the display panel.

Specifically, the passivation layer 80 and the planarization layer 90 are not shown in fig. 1, and as shown in fig. 2, the display panel further includes the passivation layer 80 and the planarization layer 90, the passivation layer 80 is disposed on a side of the interlayer dielectric layer 60 away from the substrate 10 and covers the conductive layer 70; the planarization layer 90 is disposed on a side of the passivation layer 80 away from the substrate 10, and the passivation layer 80 and the planarization layer 90 are provided with via holes 910 communicating with the auxiliary electrode lines. The passivation layer 80 may be made of silicon oxide, silicon oxynitride, silicon nitride, an organic material, or a combination thereof, and the planarization layer may be made of one of butadiene rubber, polyurethane, polyvinyl chloride, and polyamide, or one of polycarbonate, polyimide, polyether alum, and epoxy resin, which is not limited in this disclosure.

By disconnecting the intersecting positions of the gate lines and the auxiliary electrode lines and conducting the intersecting positions through the conductive layer 20, the height difference of the auxiliary electrode lines relative to the substrate 10 can be reduced, so that the thickness of the flat layer 90 is more uniform, the thickness difference of different positions is reduced, and the phenomenon of poor etching of the routing layer 70 caused by the fact that the flat layer 90 forms the through holes 910 is avoided.

The following are examples of methods of the present invention that may be used to make embodiments of the apparatus of the present invention. For details which are not disclosed in the method embodiments of the present invention, reference is made to the apparatus embodiments of the present invention.

The present exemplary embodiment provides a manufacturing method of a display panel, as shown in fig. 4, the manufacturing method including:

step S100, providing a substrate;

step S200, forming a conductive layer on one side of a substrate;

step S300, forming a gate insulating layer on one side of the conducting layer, which is far away from the substrate;

step S400, forming a gate layer on one side of the gate insulating layer, which is far away from the substrate, wherein the thickness of the gate layer is larger than that of the conductive layer, and the gate layer comprises a plurality of gate lines;

step S500, forming a groove which extends towards the substrate and cuts off the grid line on the grid line, enabling the groove to be opposite to the conductive layer, and enabling the grid line disconnected at the two sides of the groove to respectively penetrate through the grid insulating layer and be connected with the conductive layer;

step S600, forming an interlayer dielectric layer on one side of the grid layer, which is far away from the substrate, wherein the interlayer dielectric layer covers the conductive layer and fills the groove;

step S700, forming a routing layer on one side of the interlayer dielectric layer, which is far away from the substrate, wherein the routing layer comprises a plurality of auxiliary electrode wires; the orthographic projection of the auxiliary electrode line on the gate layer is intersected with the gate line in the groove, and the orthographic projection of the intersected part on the gate layer is completely positioned in the groove.

According to the manufacturing method of the display panel, the crossed part of the grid line and the auxiliary electrode line is disconnected, and the two disconnected ends of the grid line are respectively connected through the conducting layer; after the grid line disconnection, the below that auxiliary electrode line corresponds does not have the grid line, and because the thickness of conducting layer and grid insulating layer is less, consequently, the height of the relative substrate in the crossing position of auxiliary electrode line and grid line extending direction can reduce, thereby make the difference in height between each position of auxiliary electrode line reduce, and then, when the grid layer forms the flat layer, can effectively alleviate the problem that auxiliary electrode line leads to the uneven thickness of flat layer, thereby when forming the via hole of overlap joint auxiliary electrode line through the sculpture on the flat layer, can effectively fall and avoid appearing causing the bad phenomenon of sculpture to the routing layer.

In addition, two insulating layers, namely a grid insulating layer and an interlayer dielectric layer, exist between the auxiliary electrode wire and the conducting layer, so that the risk of short circuit between the auxiliary electrode wire and the conducting layer can be reduced, namely the DGS risk is basically solved.

Next, each step of the manufacturing method of the display panel in the present exemplary embodiment will be further described.

In step S100, a substrate is provided.

Specifically, as shown in fig. 2, the material of the substrate 10 may be an inorganic material, such as a glass material, for example, soda-lime glass, quartz glass, sapphire glass, or a metal material of various metals, such as stainless steel, aluminum, nickel, or an alloy thereof; and may also be an organic material such as polymethylmethacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, or a combination thereof.

In step S200, a conductive layer is formed on one side of a substrate.

Specifically, as shown in fig. 2, the conductive layer 20 may be formed on one side of the substrate 10 by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, a spin coating (spinning) process, a combination thereof, or the like, and the conductive layer 20 may also serve as a light shielding layer. The material of the conductive layer 20 is at least one of copper, aluminum, molybdenum, titanium, chromium and tungsten; the conductive layer 20 may have a single-layer metal structure or a multilayer metal structure, and for example, a multilayer metal of molybdenum, aluminum, and molybdenum, a multilayer metal of titanium, copper, and titanium, or a multilayer metal of molybdenum, titanium, and copper may be used. The thickness of the conductive layer 20 is 0.1 μm to 0.2. mu.m, and may be, for example, 0.1. mu.m, 0.13. mu.m, 0.15. mu.m, 0.17. mu.m, or 0.2. mu.m, which are not specifically exemplified herein. Of course, the thickness of the conductive layer 20 may be greater than 0.2 μm and may be less than 0.1 μm, which is not limited by the present disclosure.

In step S300, a gate insulating layer is formed on a side of the conductive layer away from the substrate.

Specifically, as shown in fig. 2, before the gate insulating layer 40 is formed, the buffer layer 30 covering the substrate 10 and the conductive layer 20 may be formed on the substrate 10 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof. The material of the buffer layer 30 may be an insulating material such as silicon oxide, silicon nitride, etc., which is not limited in this disclosure. Next, a gate insulating layer 40 is formed on the side of the buffer layer 30 away from the substrate 10 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof, wherein the material of the gate insulating layer 40 may be silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymer compounds), or a combination thereof.

In addition, before the gate electrode layer 50 is formed, via holes are formed on the gate insulating layers 40 on both sides of the predetermined position of the groove 510 by etching or the like, respectively, and then the gate electrode layer 50 is connected to the conductive layer 20 through the via holes on the gate insulating layers 40 on both sides of the groove 510 when formed. When the buffer layer 30 is further provided, the via hole penetrates through the buffer layer 30 and the gate insulating layer 40 at the same time to expose the conductive layer 20.

In step S400, a gate layer is formed on a side of the gate insulating layer away from the substrate, and the thickness of the gate layer is made greater than that of the conductive layer, the gate layer including a plurality of gate lines.

Specifically, as shown in fig. 2, a gate electrode layer 50 is formed on a side of the gate insulating layer 40 away from the substrate 10 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof, the gate electrode layer 50 has a thickness greater than that of the conductive layer 20, that is, the gate electrode layer 50 has a thickness greater than 0.2 μm, the gate electrode layer 40 forms a plurality of gate lines by a patterning process, and the gate lines are connected to the conductive layer 20 through the gate insulating layer 40 or the gate insulating layer 40 and via holes on the buffer layer 30. The material of the gate layer 50 may be metal, conductive metal oxide, conductive polymer, conductive composite material, or a combination thereof. For example, the metal can be platinum, gold, silver, aluminum, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, iron, manganese, or combinations thereof. The conductive metal oxide may be Indium Tin Oxide (ITO), fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO), or a combination thereof, which is not limited in this disclosure.

In step S500, a groove extending toward the substrate and cutting off the gate line is formed in the gate line, the groove is aligned with the conductive layer, and the gate line on the two sides of the groove is connected to the conductive layer through the gate insulating layer.

Specifically, as shown in fig. 2, a groove 510 for cutting off the gate line is formed at a position where the gate layer 50 intersects with the position of the predetermined auxiliary electrode line by etching or the like, and the groove 510 is aligned with the conductive layer 20, so that the position of the predetermined auxiliary electrode line is completely dislocated from the orthographic projection of the gate line on the substrate 10. Wherein, the disconnected gate lines at the two sides of the groove 510 respectively penetrate through the holes to be connected with the conductive layer 20.

And step S600, forming an interlayer dielectric layer on one side of the grid layer far away from the substrate, wherein the interlayer dielectric layer covers the conductive layer and fills the groove.

Specifically, as shown in fig. 2, an interlayer dielectric layer 60 is formed on the side of the gate layer 50 away from the substrate 10 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof, and the interlayer dielectric layer 60 covers the gate layer 50 and fills the groove 510. The material of the interlayer dielectric layer 60 may be silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymer compounds), or a combination thereof.

Step S700, a routing layer is formed on one side, far away from the substrate, of the interlayer dielectric layer, the routing layer comprises a plurality of auxiliary electrode wires, the orthographic projections of the auxiliary electrode wires on the gate electrode layer are intersected with the gate lines in the grooves, and the orthographic projections of the intersected parts on the gate electrode layer are completely located in the grooves.

Specifically, as shown in fig. 2, a routing layer 70 may be formed on a side of the interlayer dielectric layer 60 away from the substrate 10 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof, and the routing layer 70 forms a plurality of auxiliary electrode lines by a patterning process; the orthogonal projection of the auxiliary electrode line on the gate layer 50 intersects the gate line in the groove 510, and the orthogonal projection of the intersecting portion on the gate layer 50 is completely located in the groove 510. The material of the routing layer 70 may be metal, conductive oxide, or a combination thereof. For example, the metal may be titanium, platinum, gold, silver, aluminum, tungsten, copper, or an alloy thereof or a combination thereof, and the conductive oxide may be IZO, AZO, ITO, GZO, ZTO, or a combination thereof.

In addition, as shown in fig. 2 and 3, the method for manufacturing a display panel provided by the present disclosure may further include the steps of: the passivation layer 80 covering the conductive layer 60 may be formed on the side of the interlayer dielectric layer 70 away from the substrate 10 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof, and the planarization layer 90 may be formed on the side of the passivation layer 80 away from the substrate 10 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, or a combination thereof; a via hole 910 communicating with the auxiliary electrode line is formed on the passivation layer 80 and the planarization layer 90 by etching or the like, so as to realize the overlapping of the auxiliary cathode.

The passivation layer 80 may be made of silicon oxide, silicon oxynitride, silicon nitride, organic material, or a combination thereof; the material of the planarization layer may be any one of butadiene rubber, polyurethane, polyvinyl chloride, and polyamide, or any one of polycarbonate, polyimide, polyether alum, and epoxy, which is not limited by the present disclosure.

The difference h1-h2 of the uneven thickness of the flat layer 90 caused by the auxiliary electrode wires is equal to the thickness of the conducting layer 20, and the thickness of the conducting layer 20 is 0.1-0.2 μm, so that the manufacturing method can reduce the thickness difference of the flat layer 90 by one order of magnitude, greatly improve the thickness uniformity of the flat layer 90, more effectively avoid the phenomenon of poor etching of the routing layer 70, and ensure the reliability of the display panel.

In addition, a planar layer 90 covering the routing layer 70 and the interlayer dielectric layer 60 may also be formed directly on the side of the interlayer dielectric layer 60 away from the substrate 10, which may be selected by those skilled in the art according to the actual situation, and the disclosure is not limited thereto.

The present disclosure further provides a display device including the display panel, and the advantageous effects of the display device can refer to the description about the advantageous effects of the display panel, which is not repeated herein. The display device may be a device having a display function, such as a television, a mobile phone, a tablet computer, a notebook computer, a display screen, an advertisement product, an electronic watch, and a vehicle-mounted display screen, which are not listed here.

It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A display panel, comprising:

a substrate;

the conducting layer is arranged on one side of the substrate;

2. The display panel according to claim 1, wherein the conductive layer is a light-shielding conductive material.

3. The display panel according to claim 1, characterized in that the display panel further comprises:

4. The display panel according to claim 1, characterized in that the display panel further comprises:

5. The display panel according to claim 1, wherein the conductive layer has a thickness of 0.1 μm to 0.2 μm.

6. A method of manufacturing a display panel, comprising:

providing a substrate;

forming a conductive layer on one side of the substrate;

forming a wiring layer on one side of the interlayer dielectric layer, which is far away from the substrate, wherein the wiring layer comprises a plurality of auxiliary electrode wires; the orthographic projection of the auxiliary electrode line on the gate layer intersects with the orthographic projection of the gate line on the groove, and the intersecting part is completely positioned in the groove.

7. The manufacturing method according to claim 6, wherein after forming a conductive layer on a side of the substrate and before forming a gate insulating layer on a side of the conductive layer away from the substrate, the manufacturing method further comprises:

8. The method of manufacturing according to claim 7, wherein forming a groove in the gate line extending toward the substrate and intercepting the gate line comprises:

9. The manufacturing method according to claim 6, further comprising:

10. A display device comprising the display panel according to any one of claims 1 to 5.