CN110767590A - Method for aligning and bonding two silicon wafers by using silicon wafer notches - Google Patents
Method for aligning and bonding two silicon wafers by using silicon wafer notches Download PDFInfo
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- CN110767590A CN110767590A CN201911063022.1A CN201911063022A CN110767590A CN 110767590 A CN110767590 A CN 110767590A CN 201911063022 A CN201911063022 A CN 201911063022A CN 110767590 A CN110767590 A CN 110767590A
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- 235000012431 wafers Nutrition 0.000 title claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 66
- 239000010703 silicon Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012360 testing method Methods 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000011156 evaluation Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
A method for aligning and bonding two silicon wafers by using silicon wafer notches belongs to the field of semiconductor manufacturing, and comprises the following steps: forming a first pattern on a surface to be bonded of a carrier silicon wafer, wherein the first pattern is used as a test mark; forming a second pattern matched with the first pattern on the surface to be bonded of the product silicon wafer, wherein the second pattern is used as a test mark, and bonding the carrier silicon wafer with the first pattern and the product silicon wafer with the second pattern in a notch alignment mode; and after bonding, testing the relative positions of the centers of the first graph and the second graph, comparing the central positions of the first graph and the second graph, and obtaining an alignment result after bonding the carrier silicon wafer and the product silicon wafer by using the deviation of the central positions of the first graph and the second graph. The method can effectively solve the problem that the registration result evaluation of two silicon wafers cannot be realized after notch alignment is used, and output the evaluation result for the alignment after the adjustment of a bonding machine and the bonding of a product.
Description
Technical Field
The invention discloses a method for bonding two silicon wafers by aligning silicon wafer notches, and belongs to the field of semiconductor manufacturing.
Background
In the conventional method, alignment and testing are performed by using marks made on silicon wafers, so that the alignment result of a bonding machine is evaluated, and therefore, a notch at the upper edge of the silicon wafer is required to be used for aligning the positions of two silicon wafers, but alignment evaluation after notch mark alignment cannot be achieved at present, and therefore, a new technical scheme is urgently needed to solve the problems.
Disclosure of Invention
Aiming at the problem that the alignment evaluation cannot be realized at present after the notch mark is aligned in the prior art, the invention aims to provide a method for aligning and bonding two silicon wafers by using a silicon wafer notch.
The technical scheme adopted by the invention for realizing the purpose is as follows: a method for bonding two silicon wafers by aligning silicon wafer notches is characterized by comprising the following steps:
selecting a carrier silicon wafer and a product silicon wafer;
step two, forming a first pattern on the surface to be bonded of the carrier silicon wafer by adopting photoetching and etching processes, wherein the first pattern is used as a test mark;
step three, forming a second graph matched with the first graph on the surface to be bonded of the product silicon wafer by adopting photoetching and etching processes, wherein the second graph is used as a test mark, when the carrier silicon wafer and the surface to be bonded of the product silicon wafer are oppositely placed, the projection of the second graph is nested in the first graph, the central point of the first graph and the central point of the second graph are positioned on the same straight line, and the projection of the center of the first graph on the second graph is superposed with the center of the second graph;
bonding the carrier silicon wafer with the first pattern and the product silicon wafer with the second pattern in a notch alignment mode;
and fifthly, testing the relative positions of the centers of the first graph and the second graph after bonding, comparing the central positions of the first graph and the second graph, and obtaining an alignment result after the carrier silicon wafer and the product silicon wafer are bonded by using the deviation of the central positions of the first graph and the second graph.
Further, the first graph is a closed graph formed by sequentially connecting circular or more than three line segments end to end.
Further, the second graph is a closed graph formed by sequentially connecting circular or more than three line segments end to end.
Through the design scheme, the invention can bring the following beneficial effects: the method for aligning and bonding two silicon wafers by using the silicon wafer notches solves the problem that the registration of the two silicon wafers cannot be evaluated when the notches of the silicon wafers are used for aligning and bonding the two silicon wafers, can effectively evaluate the results of the alignment bonding and the registration, and can better control the bonding interface and the precision by using a machine.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below in connection with preferred embodiments. As will be appreciated by those skilled in the art. The following detailed description is to be construed as illustrative and not restrictive, and various changes may be made in the following parameters by a user without departing from the spirit and scope of the invention as set forth in the appended claims. Well-known methods and procedures have not been described in detail so as not to obscure the present invention.
The invention provides a method for aligning and bonding two silicon wafers by using silicon wafer notches, which comprises the following steps:
firstly, manufacturing a photoetching plate required by a test mark for measuring overlay;
selecting a carrier silicon wafer and a product silicon wafer;
forming a first pattern on the surface to be bonded of the carrier silicon wafer by adopting photoetching and etching processes, wherein the first pattern is used as a test mark, and the first pattern is a closed pattern formed by sequentially connecting circular or more than three line segments end to end;
forming a second graph matched with the first graph on the surface to be bonded of the product silicon wafer by adopting photoetching and etching processes, wherein the second graph is used as a test mark, the second graph is a closed graph formed by sequentially connecting circular or more than three line segments end to end, when the surfaces to be bonded of the carrier silicon wafer and the product silicon wafer are oppositely placed, the projection of the second graph is nested in the first graph, the central point of the first graph and the central point of the second graph are positioned on the same straight line, and the projection of the center of the first graph on the second graph is superposed with the center of the second graph;
bonding a carrier silicon wafer with a test mark and a product silicon wafer by adopting a notch alignment mode, wherein the two silicon wafers are bonded together under the action of physical and chemical bonds;
and step six, after bonding, testing the relative positions of the centers of the first graph and the second graph, comparing the central positions of the first graph and the second graph, and obtaining an alignment result after bonding the carrier silicon wafer and the product silicon wafer by using the deviation of the central positions of the first graph and the second graph.
The invention adopts photoetching and etching processes to form a pattern to be measured on two silicon wafers to be bonded as a test mark, and tests the registration condition of the manufactured test mark after bonding the two silicon wafers.
Claims (3)
1. A method for bonding two silicon wafers by aligning silicon wafer notches is characterized by comprising the following steps:
selecting a carrier silicon wafer and a product silicon wafer;
step two, forming a first pattern on the surface to be bonded of the carrier silicon wafer by adopting photoetching and etching processes, wherein the first pattern is used as a test mark;
step three, forming a second graph matched with the first graph on the surface to be bonded of the product silicon wafer by adopting photoetching and etching processes, wherein the second graph is used as a test mark, when the carrier silicon wafer and the surface to be bonded of the product silicon wafer are oppositely placed, the projection of the second graph is nested in the first graph, the central point of the first graph and the central point of the second graph are positioned on the same straight line, and the projection of the center of the first graph on the second graph is superposed with the center of the second graph;
bonding the carrier silicon wafer with the first pattern and the product silicon wafer with the second pattern in a notch alignment mode;
and fifthly, testing the relative positions of the centers of the first graph and the second graph after bonding, comparing the central positions of the first graph and the second graph, and obtaining an alignment result after the carrier silicon wafer and the product silicon wafer are bonded by using the deviation of the central positions of the first graph and the second graph.
2. The method of claim 1, wherein the bonding of two silicon wafers with the wafer notch aligned is performed by: the first graph is a closed graph formed by sequentially connecting circular or more than three line segments end to end.
3. The method of claim 1, wherein the bonding of two silicon wafers with the wafer notch aligned is performed by: the second graph is a closed graph formed by sequentially connecting circular or more than three line segments end to end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911063022.1A CN110767590A (en) | 2019-10-31 | 2019-10-31 | Method for aligning and bonding two silicon wafers by using silicon wafer notches |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911063022.1A CN110767590A (en) | 2019-10-31 | 2019-10-31 | Method for aligning and bonding two silicon wafers by using silicon wafer notches |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110767590A true CN110767590A (en) | 2020-02-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911063022.1A Pending CN110767590A (en) | 2019-10-31 | 2019-10-31 | Method for aligning and bonding two silicon wafers by using silicon wafer notches |
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| CN (1) | CN110767590A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112908898A (en) * | 2021-01-27 | 2021-06-04 | 长鑫存储技术有限公司 | Control wafer measuring method and measuring device |
| CN116313971A (en) * | 2023-05-17 | 2023-06-23 | 拓荆键科(海宁)半导体设备有限公司 | Wafer bonding alignment method through edge detection |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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Application publication date: 20200207 |