CN110767545A - Silicon wafer etching method - Google Patents
Silicon wafer etching method Download PDFInfo
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- CN110767545A CN110767545A CN201910986346.6A CN201910986346A CN110767545A CN 110767545 A CN110767545 A CN 110767545A CN 201910986346 A CN201910986346 A CN 201910986346A CN 110767545 A CN110767545 A CN 110767545A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 100
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 100
- 239000010703 silicon Substances 0.000 title claims abstract description 100
- 238000005530 etching Methods 0.000 title claims abstract description 85
- 238000000034 method Methods 0.000 title claims abstract description 64
- 235000012431 wafers Nutrition 0.000 claims abstract description 100
- 238000001312 dry etching Methods 0.000 claims description 20
- 239000007789 gas Substances 0.000 claims description 15
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 13
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 6
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The application discloses a silicon wafer etching method, and relates to the field of semiconductor manufacturing. The method is applied to a certas machine, the certas machine comprises two reaction cavities, each reaction cavity is provided with two air inlet pipes, and the two air inlet pipes are symmetrically distributed at an angle of 180 degrees; the method comprises the steps of placing two silicon wafers into two reaction cavities of the certas machine, wherein one silicon wafer is arranged in each reaction cavity; and etching the two silicon wafers simultaneously. The problems that when the existing certas machine station etches two silicon wafers simultaneously, the etching rates of the two silicon wafers are different and the uniformity is low are solved; the phenomenon that the etching rates are different under different loads is improved, the etching uniformity of two silicon wafers in the certas machine table is improved, and the product yield is improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a silicon wafer etching method.
Background
With the development of integrated circuits, the critical dimension of semiconductor devices is smaller and smaller, and the requirements on etching processes are higher and higher. The currently common etching technique is dry etching, i.e. plasma etching. In dry etching, material is removed by bombarding the wafer surface with an excited plasma. Uniformity is an important index of etching rate difference of different etching positions, the quality of uniformity affects the yield of products, and the better the uniformity is, the higher the yield is.
The existing machine used in the process of channel isolation and double-gate back etching before back etching is a certas (chemical gas etching) machine, and the certas machine can simultaneously feed two silicon wafers for processing. As shown in FIG. 1, the certas etch process uses ammonia (NH)3)11 and hydrogen fluoride gas (HF)12, ammonia gas 11 being fed through line 111, hydrogen fluoride gas 12 being passed throughConveying through a pipeline 121, arranging an air inlet pipe 112 and an air inlet pipe 122 on two sides of the machine table, respectively connecting the pipeline 111 and the pipeline 121 through the air inlet pipe 112 and the air inlet pipe 122, and conveying the ammonia gas 11 and the hydrogen fluoride gas 12 into a reaction cavity in the certas machine table through the air inlet pipe 112 and the air inlet pipe 121. The surfaces of the silicon wafer 110 and the silicon wafer 120 in the certas machine may include various etching patterns, and during the dry etching process, the gas pumped by the molecular pump flows out from the pipeline 13. Due to the influence of process factors such as air flow and different etching patterns, the silicon wafer 110 and the silicon wafer 120 have the problem of edge deviation; if a silicon wafer includes a plurality of etching patterns, the density structures of different regions on the silicon wafer are different, as shown in fig. 2, the density structures corresponding to the etching regions 20 and 21 are different, and the etching numbers of the etching regions 20 and 21 are different, which results in uneven etching.
Disclosure of Invention
The application provides a silicon wafer etching method which can solve the problems of poor uniformity and edge deviation of etching of two silicon wafers in the related art.
On one hand, the embodiment of the application provides a silicon wafer etching method, which is applied to a certas machine, wherein the certas machine comprises two reaction chambers, each reaction chamber is provided with two air inlet pipes, and the two air inlet pipes are symmetrically distributed at an angle of 180 degrees;
the method comprises the following steps:
placing two silicon wafers into two reaction cavities of a certas machine table, wherein one silicon wafer is arranged in each reaction cavity;
and simultaneously etching the two silicon wafers.
Optionally, one of the two air inlet pipes is connected with ammonia gas, and the other air inlet pipe is connected with hydrogen fluoride gas.
Optionally, etching two silicon wafers simultaneously includes:
and etching the two silicon wafers simultaneously by adopting a certas dry etching process.
Optionally, the certas dry etching process includes remote dry etching and in-situ annealing performed after the remote dry etching.
Optionally, in the remote dry etching process, the flow rate of the ammonia gas is 50-500sccm, the flow rate of the hydrogen fluoride gas is 20-300 sccm, the pressure of the chamber is 2000-.
Optionally, in the in-situ annealing process, the temperature is 100-.
Optionally, the etching patterns on the surfaces of the two silicon wafers are different.
Optionally, the certas machine is applied to a back-etching shallow trench isolation process and/or a back-etching double-gate process.
The technical scheme at least comprises the following advantages:
the silicon wafer etching method provided by the embodiment of the application is applied to a certas machine table, the certas machine table comprises two reaction chambers, each reaction chamber is provided with two air inlet pipes, the two air inlet pipes are symmetrically distributed at 180 degrees, two silicon wafers are placed in the two reaction chambers of the certas machine table, one silicon wafer is arranged in each reaction chamber, and the two silicon wafers are etched at the same time; the problems that when the existing certas machine station etches two silicon wafers simultaneously, the etching rates of the two silicon wafers are different and the uniformity is low are solved; the phenomenon that the etching rates are different under different loads is improved, the etching uniformity of two silicon wafers in the certas machine table is improved, and the product yield is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a conventional certas machine;
FIG. 2 is a schematic diagram showing the uniformity of a silicon wafer etched by using a conventional certas machine;
FIG. 3 is a schematic diagram of the etching rate after etching a silicon wafer by using the conventional certas machine;
fig. 4 is a schematic diagram of a certas machine according to an embodiment of the present disclosure;
FIG. 5 is a flowchart of a method for etching a silicon wafer according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating uniformity after a silicon wafer is etched by using the silicon wafer etching method according to the embodiment of the present application;
FIG. 7 is a schematic diagram illustrating an etching rate after a silicon wafer is etched by using the silicon wafer etching method according to the embodiment of the present application;
fig. 8 is a flowchart of another method for etching a silicon wafer according to an embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
As shown in fig. 1, two silicon wafers can be fed into a certas machine at one time for processing, specifically, two silicon wafers are placed in parallel in one reaction chamber of the certas machine, two air inlet pipes are arranged on the certas machine, for each silicon wafer, the air inlet of the certas machine is a single-side air inlet of the silicon wafer, in the process, due to the fact that the density distribution of plasma is not uniform, the etching rates of different positions are different, especially the etching difference between the middle of the reaction chamber and the edge of the reaction chamber is large, the problem that the etching rate of the silicon wafer is biased is caused, as shown in fig. 3, the silicon wafer 110 and the silicon wafer 120 are biased after being etched, that is, the etching rate of the middle area of the corresponding reaction chamber on the silicon wafer 110 and the silicon wafer 120 is larger than that of the. If the surface of a silicon wafer comprises a plurality of etching patterns, namely the surface of the silicon wafer has structures with different densities, the etching uniformity of the silicon wafer is also influenced. In order to improve the problems that when the existing certas machine is used for etching two silicon wafers, the uniformity of silicon wafer etching is poor, and the two silicon wafers are deviated, the certas machine is improved, and a silicon wafer etching method is provided.
The embodiment of the application provides a certas machine, which comprises two reaction cavities, wherein the two reaction cavities are mutually independent, each reaction cavity is provided with two air inlet pipes, and the two air inlet pipes are symmetrically distributed at an angle of 180 degrees.
As shown in fig. 4, the reaction chamber 41 and the reaction chamber 42 are independent of each other, the reaction chamber 41 is provided with an air inlet pipe 411 and an air inlet pipe 412, and the air inlet pipe 411 and the air inlet pipe 412 are symmetrically distributed at 180 degrees; the reaction chamber 42 is provided with an air inlet pipe 421 and an air inlet pipe 422, and the air inlet pipe 421 and the air inlet pipe 422 are symmetrically distributed at 180 degrees.
An inlet line 411 and an inlet line 421 are connected to the line 111, the line 111 being used for conveying ammonia (NH)3)11, feed line 412 and feed line 422 are connected to line 121, line 121 being used for the supply of Hydrogen Fluoride (HF) gasThe ammonia gas 11 and the hydrogen fluoride gas 12 are used for the certas dry etching process in the reaction chamber 41 and the reaction chamber 42 on the certas machine.
The gas extracted from the reaction chamber 41 is discharged through the line 413, and the gas extracted from the reaction chamber 42 is discharged through the line 423.
When carrying out the certas dry etching process, each reaction cavity is provided with a silicon wafer, and as can be seen from fig. 4, the air inlet of the certas machine station is used for introducing air to the two sides of the silicon wafer 110 and the silicon wafer 120.
As shown in fig. 5, which shows a flowchart of a method of a silicon wafer etching method provided in an embodiment of the present application, the method is applied to the certas machine shown in fig. 4, and the method may include the following steps:
step 501, two silicon wafers are placed in two reaction chambers of a certas machine, and one silicon wafer is arranged in each reaction chamber.
The two reaction chambers of the certas machine table are mutually independent, each reaction chamber is provided with two air inlet pipes, and the two air inlet pipes are symmetrically distributed at an angle of 180 degrees.
Step 502, etching two silicon wafers simultaneously.
After etching by using the certas machine and the silicon wafer etching method provided by the application, because the certas machine is changed into the silicon wafer bilateral gas inlet, reaction gas flows through both sides of each silicon wafer, aiming at one silicon wafer, the etching patterns corresponding to the etching area 20 and the etching area 21 are different, namely the corresponding density structures are different, but the etching quantity corresponding to the etching area 20 and the etching area 21 is the same, so that the etching uniformity is ensured, as shown in fig. 6; the silicon wafer 110 and the silicon wafer 120 also do not have the edge misalignment problem, as shown in fig. 7.
In summary, the silicon wafer etching method provided by the embodiment of the present application is applied to a certas machine, the certas machine comprises two reaction chambers, each reaction chamber is provided with two air inlet pipes, the two air inlet pipes are symmetrically distributed at 180 degrees, two silicon wafers are placed in the two reaction chambers of the certas machine, and one silicon wafer is arranged in each reaction chamber to etch the two silicon wafers at the same time; the problems that when the existing certas machine station etches two silicon wafers simultaneously, the etching rates of the two silicon wafers are different and the uniformity is low are solved; the phenomenon that the etching rates are different under different loads is improved, the etching uniformity of two silicon wafers in the certas machine table is improved, and the product yield is improved.
As shown in fig. 8, which shows a flowchart of another method for etching a silicon wafer according to an embodiment of the present application, the method is applied to the certas machine shown in fig. 4, and the method may include the following steps:
The two reaction chambers of the certas machine table are mutually independent, each reaction chamber is provided with two air inlet pipes, and the two air inlet pipes are symmetrically distributed at an angle of 180 degrees.
One of the two air inlet pipes is connected with ammonia (NH) in each reaction cavity3) And the other inlet pipe is connected with hydrogen fluoride gas (HF).
Optionally, the etching patterns on the surfaces of the two silicon wafers are different, or the etching patterns of the two silicon wafers are the same.
Whether the etching patterns on the surfaces of the two silicon wafers entering the certas machine station reaction cavity at the same time are the same or not is not limited, and the etching patterns on the surfaces of the two silicon wafers are determined according to actual conditions.
And step 802, etching the two silicon wafers simultaneously by adopting a certas dry etching process.
The certas dry etching process comprises remote dry etching and in-situ annealing after the remote dry etching.
In the remote dry etching process, the flow rate of ammonia gas is 50-500sccm, the flow rate of hydrogen fluoride gas is 20-300 sccm, the pressure of the chamber is 2000-.
In the in-situ annealing process, the temperature is 100-200 ℃. It should be noted that the certas machine and the silicon wafer etching method provided by the application are applied to the back etching shallow trench isolation process and the back etching double gate (dual gate) process, or applied to any one of the back etching shallow trench isolation process and the back etching double gate (dual gate) process.
In summary, the silicon wafer etching method provided by the embodiment of the present application is applied to a certas machine, the certas machine comprises two reaction chambers, each reaction chamber is provided with two air inlet pipes, the two air inlet pipes are symmetrically distributed at 180 degrees, two silicon wafers are placed in the two reaction chambers of the certas machine, and one silicon wafer is arranged in each reaction chamber to etch the two silicon wafers at the same time; the problems that when the existing certas machine station etches two silicon wafers simultaneously, the etching rates of the two silicon wafers are different and the uniformity is low are solved; the phenomenon that the etching rates are different under different loads is improved, the etching uniformity of two silicon wafers in the certas machine table is improved, and the product yield is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. The silicon wafer etching method is characterized by being applied to a certas machine, wherein the certas machine comprises two reaction cavities, each reaction cavity is provided with two air inlet pipes, and the two air inlet pipes are symmetrically distributed at an angle of 180 degrees;
the method comprises the following steps:
placing two silicon wafers into two reaction cavities of the certas machine table, wherein one silicon wafer is arranged in each reaction cavity;
and etching the two silicon wafers simultaneously.
2. The method according to claim 1, characterized in that one of the two inlet pipes is connected to ammonia gas and the other inlet pipe is connected to hydrogen fluoride gas.
3. The method of claim 1 or 2, wherein the etching the two pieces of silicon wafer simultaneously comprises:
and etching the two silicon wafers simultaneously by adopting a certas dry etching process.
4. The method of claim 3, wherein the certas dry etching process comprises remote dry etching and in-situ annealing after the remote dry etching.
5. The method as claimed in claim 4, wherein the flow rate of the ammonia gas is 50-500sccm, the flow rate of the hydrogen fluoride gas is 20-300 sccm, the chamber pressure is 2000-5000mtorr, and the temperature is 20-200 ℃ in the remote dry etching process.
6. The method as claimed in claim 4, wherein the temperature in the in-situ annealing process is 100-200 ℃.
7. The method of claim 1, wherein the etched patterns on the surfaces of the two silicon wafers are different.
8. The method of claim 1, wherein the certas machine is applied to a etchback shallow trench isolation process and/or an etchback double gate process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910986346.6A CN110767545A (en) | 2019-10-17 | 2019-10-17 | Silicon wafer etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910986346.6A CN110767545A (en) | 2019-10-17 | 2019-10-17 | Silicon wafer etching method |
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| CN110767545A true CN110767545A (en) | 2020-02-07 |
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| CN201910986346.6A Pending CN110767545A (en) | 2019-10-17 | 2019-10-17 | Silicon wafer etching method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101076219A (en) * | 2007-06-20 | 2007-11-21 | 中微半导体设备(上海)有限公司 | Decoupling reactive ion etching chamber containing multiple processing platforms |
| CN101736326A (en) * | 2008-11-26 | 2010-06-16 | 中微半导体设备(上海)有限公司 | Capacitively coupled plasma processing reactor |
| CN107345294A (en) * | 2017-07-26 | 2017-11-14 | 北京芯微诺达科技有限公司 | A kind of air intake structure of plasma apparatus |
| US20180174885A1 (en) * | 2016-12-15 | 2018-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device, Method, and Tool of Manufacture |
| US20190067028A1 (en) * | 2017-08-25 | 2019-02-28 | Andrew L. Li | Vapor-etch cyclic process |
-
2019
- 2019-10-17 CN CN201910986346.6A patent/CN110767545A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101076219A (en) * | 2007-06-20 | 2007-11-21 | 中微半导体设备(上海)有限公司 | Decoupling reactive ion etching chamber containing multiple processing platforms |
| CN101736326A (en) * | 2008-11-26 | 2010-06-16 | 中微半导体设备(上海)有限公司 | Capacitively coupled plasma processing reactor |
| US20180174885A1 (en) * | 2016-12-15 | 2018-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor Device, Method, and Tool of Manufacture |
| CN107345294A (en) * | 2017-07-26 | 2017-11-14 | 北京芯微诺达科技有限公司 | A kind of air intake structure of plasma apparatus |
| US20190067028A1 (en) * | 2017-08-25 | 2019-02-28 | Andrew L. Li | Vapor-etch cyclic process |
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