CN110764599A - Reset control device and method - Google Patents
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- CN110764599A CN110764599A CN201810847491.1A CN201810847491A CN110764599A CN 110764599 A CN110764599 A CN 110764599A CN 201810847491 A CN201810847491 A CN 201810847491A CN 110764599 A CN110764599 A CN 110764599A
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Abstract
The invention provides a reset control device and a method, wherein the device comprises: the reset signal generator is used for outputting a square wave reset signal to the square wave detector within a preset first reset time interval; the square wave detector is used for outputting a reset control signal to the to-be-reset device when the square wave reset signal is detected; and the to-be-reset device is used for resetting after receiving the reset control signal. According to the reset control device and method provided by the invention, when the reset chip is damaged, continuous reset of the DSP, the FPGA and the like can not be caused, so that the reset control device and method can work normally.
Description
Technical Field
The invention relates to the technical field of control, in particular to a reset control device and method.
Background
Many Control units are not necessary for complex functions of the vehicle, such as an Electronic Control Unit (ECU) in a new energy vehicle, a Battery Management System (BMS), a Motor Control Unit (MCU) and some multimedia Control units. These control units are constituted by a DSP or FPGA as a core and peripheral circuits, and during power-on, a reset circuit is designed to prevent malfunction of the DSP or FPGA due to unstable power supply.
In the related art, a reset chip (e.g., X5325, X5045, TPS767D301PWP, TPS3803-Q1, etc.) is generally used for resetting. When the reset chip executes reset, it sends a single-level reset Signal to control a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), and the like to perform reset. For example, when the reset chip performs resetting, a high-level reset signal is sent out and is converted into a low-level control signal through the level conversion circuit to control the DSP, the FPGA and the like to perform resetting operation, and when the reset chip sends out the low-level reset signal, the low-level reset signal is converted into a high-level control signal through the level conversion circuit to control the DSP, the FPGA and the like to normally work.
However, the related art has at least the following defects: the damage of the reset chip can lead to the continuous reset of the DSP, the FPGA and the like, and the normal work can not be realized, and particularly, in the running process of the vehicle, the continuous reset of the DSP, the FPGA and the like can influence the normal running of the vehicle.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, a first object of the present invention is to provide a reset control device, so that when a reset chip is damaged, the device will not cause continuous reset of a DSP, an FPGA, etc., and can operate normally.
The second objective of the present invention is to provide a reset control method.
A third object of the invention is to propose an electronic device.
A fourth object of the invention is to propose a non-transitory computer-readable storage medium.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a reset control apparatus, including: the reset signal generator is used for outputting a square wave reset signal to the square wave detector within a preset reset time interval; the square wave detector is used for outputting a reset control signal to the to-be-reset device when the square wave reset signal is detected; and the to-be-reset device is used for resetting after receiving the reset control signal.
The reset control device of the embodiment of the invention adopts the square wave reset signal to control the device to be reset to reset, when the reset signal generator is damaged, the square wave reset signal can not be output, and further the square wave detector can not output the reset control signal because the square wave reset signal can not be detected, so that the device to be reset (such as DSP, FPGA and the like) can not be continuously reset, and the device to be reset can normally work.
In order to achieve the above object, a second embodiment of the present invention provides a reset control method, including: controlling a reset signal generator to output a square wave reset signal to a square wave detector within a preset first reset time interval; controlling the square wave detector to output a reset control signal to the to-be-reset device when detecting the square wave reset signal; and controlling the to-be-reset device to reset after receiving the reset control signal.
According to the reset control method, the square wave reset signal is adopted to control the to-be-reset device to reset, when the reset signal generator is damaged, the square wave reset signal cannot be output, and further, the square wave detector cannot output the reset control signal because the square wave reset signal cannot be detected, so that the to-be-reset device (such as a DSP (digital signal processor), an FPGA (field programmable gate array) and the like) cannot be continuously reset, and the to-be-reset device can normally work.
To achieve the above object, a third aspect of the present invention provides an electronic device, including: the reset control method comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the reset control method according to the embodiment of the second aspect of the invention.
To achieve the above object, a fourth aspect of the present invention provides a non-transitory computer-readable storage medium, on which a computer program is stored, the computer program being executed by a processor for implementing the reset control method according to the second aspect of the present invention.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic diagram illustrating an operation principle of reset control in the related art;
fig. 2 is a schematic structural diagram of a reset control apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a reset control device according to another embodiment of the present invention;
fig. 4 is a flow chart illustrating a reset control method of the reset control device according to the embodiment shown in fig. 3;
fig. 5 is a flowchart illustrating a reset control method according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
For clarity of explanation of the reset control apparatus and method according to the embodiments of the present invention, a reset control scheme in the related art is described in detail below.
Fig. 1 is a schematic diagram illustrating an operation principle of reset control in the related art. As shown in fig. 1, when the reset chip performs reset, a single-level reset signal is sent to control the DSP, the FPGA, and the like to perform reset. Specifically, when the reset chip sends a high-level reset signal, the switching tube Q1 is turned on, the second capacitor C2 discharges, a low-level control signal is output, and the DSP, the FPGA, and the like are controlled to perform reset operation. When the reset chip sends a low-level reset signal, the switching tube Q1 is turned off, the second capacitor C2 is charged, a high-level control signal is output, and normal work of the DSP, the FPGA and the like is controlled. Because the DSP, the FPGA and the like are controlled to reset by adopting the reset signal with a single level, on one hand, the reset signal is interfered and generates accidental jump, for example, when the low-level reset signal jumps into the high-level reset signal, the false reset operation can be generated; on the other hand, the damage of the reset chip can cause the continuous reset of the DSP, the FPGA and the like, and the normal work can not be realized, and particularly, the continuous reset of the DSP, the FPGA and the like can influence the normal running of the vehicle in the running process of the vehicle.
The reset control apparatus and method according to the embodiments of the present invention are described below with reference to the drawings.
Fig. 2 is a schematic structural diagram of a reset control device according to an embodiment of the present invention. As shown in fig. 2, the reset control apparatus according to the embodiment of the present invention includes:
the reset signal generator 21 is configured to output a square wave reset signal to the square wave detector 22 within a preset first reset time interval.
And the square wave detector 22 is used for outputting a reset control signal to the to-be-reset device 23 when the square wave reset signal is detected.
And the to-be-reset device 23 is used for resetting after receiving the reset control signal.
Specifically, the reset signal generator 21 may use a chip (e.g., CPLD) to send the square wave reset signal by program control, or use a square wave generating circuit to send the square wave reset signal. The square wave reset signal is a square wave signal with a non-single level, namely a signal with high-low level conversion. The frequency and amplitude of the square wave reset signal, and the length of time for transmission, i.e., the preset first reset interval (e.g., 100 ms), may be determined on a case-by-case basis. And stopping sending the square wave reset signal after the sending of the square wave reset signal is finished.
And the square wave detector 22 is configured to detect whether the reset signal generator 21 outputs a square wave reset signal, generate a reset control signal when the square wave reset signal is detected, and output the reset control signal to the to-be-reset device 23.
The device to be reset 23 is a device requiring reset control, such as a DSP, an FPGA, or the like in an automobile. The to-be-reset device 23 performs a reset operation upon receiving the reset control signal output from the square wave detector 22.
The reset control device of the embodiment of the invention adopts the square wave reset signal to control the device to be reset to reset, when the reset signal generator is damaged, the square wave reset signal can not be output, and further the square wave detector can not output the reset control signal because the square wave reset signal can not be detected, so that the device to be reset (such as DSP, FPGA and the like) can not be continuously reset, and the device to be reset can normally work.
Fig. 3 is a schematic structural diagram of a reset control device according to another embodiment of the present invention. The reset control device according to the embodiment of the present invention is a specific implementation manner of the reset control device according to the embodiment shown in fig. 2. As shown in fig. 3, in the reset control apparatus according to the embodiment of the present invention, the square wave detector 22 can be specifically configured to:
and when the square wave reset signal is detected to exceed a preset second reset time interval, outputting a reset control signal to the to-be-reset device 23, wherein the second reset time interval is smaller than the first reset time interval.
Specifically, the square wave detector 22 outputs a reset control signal to the to-be-reset device 23 when detecting that the square wave reset signal exceeds the preset second reset time interval. Therefore, when the square wave reset signal output by the reset generator is interfered and accidental jump occurs, an abnormal square wave reset signal in a very short time (smaller than the second reset time interval) can be formed, so that the square wave detector 22 is not influenced to output the reset control signal, and the error operation of the reset device (such as a DSP, an FPGA and the like) which fails in the middle of the reset operation can not occur.
Since the time when the reset signal generator 21 sends the square wave reset signal is the first reset time interval, the time delay of the square wave detector 22 when detecting the square wave reset signal and outputting the reset control signal, that is, the second reset time interval, should be less than the first reset time interval, so as to avoid that the square wave detector 22 cannot output the reset control signal because the square wave reset signal cannot be detected because the reset signal generator 21 stops sending the square wave reset signal when the time delay exceeds the first reset time interval.
Further, the to-be-reset device 23 may be further configured to: after the reset is completed, the normal operation is performed, and the return detection signal is output to the reset signal generator 21. The reset signal generator 21 is further configured to: when the back detection signal abnormality is detected, the square wave reset signal is output to the square wave detector 22 again within the first reset time interval.
Specifically, the to-be-reset device 23 continuously sends back the detection signal to the reset signal generator 21, the to-be-reset device 23 sends the single-level return detection signal when performing the reset operation, and after the reset operation is completed, the device resumes normal operation, and sends the square wave return detection signal, for example, the square wave return detection signal with the frequency of 5000 hz and the duty ratio of 50%. After the reset operation of the reset device 23 is completed under the control of the reset control signal, the normal operation is resumed, and the return detection signal is output to the reset signal generator 21. The reset signal generator 21 detects the received back detection signal, and determines that the to-be-reset device 23 is in a dead halt when the back detection signal is detected to be abnormal (for example, the back detection signal cannot be detected within 800 milliseconds and has 2 rising edges, that is, the back detection signal cannot be detected within 800 milliseconds and changes from a low level to a high level for 2 times), so that the square wave reset signal is output to the square wave detector 22 again within the first reset time interval to control the to-be-reset device 23 to perform the reset operation again, and resume the normal operation. When the reset device 23 fails to reset or fails to work normally after the reset operation is completed under the control of the reset control signal, it outputs an abnormal return detection signal to the reset signal generator 21. The reset signal generator 21 detects the received return detection signal, finds that the return detection signal is abnormal, and determines that the device to be reset 23 is in a dead halt state, so that the square wave reset signal is output to the square wave detector 22 again in the first reset time interval to control the device to be reset 23 to perform reset operation again, and normal work is recovered.
Further, the square wave detector 22 may specifically include:
a first terminal of the first capacitor C1, a first terminal of the first capacitor C1 is connected to the output terminal of the reset signal generator 21.
A first resistor R1, a first terminal of the first resistor R1 is connected to a second terminal of the first capacitor C1.
And a first end of a second resistor R3, R3 is connected with the power supply DC.
The control end of the switching tube Q1 is connected to the second end of the first resistor R1, the first end of the switching tube Q1 is connected to the second end of the second resistor R3, and the second end of the switching tube Q1 is grounded.
And a first end of the third resistor R2, a first end of the third resistor R2 is connected with the control end of the switching tube Q1, and a second end of the third resistor R2 is grounded.
A first end of the fourth resistor R4 and a first end of the fourth resistor R4 are connected to the first end of the switching tube Q1.
A first end of a second capacitor C2 and a first end of a second capacitor C2 are connected with a second end of the fourth resistor R4, a second end of the second capacitor C2 is grounded, and a first end of a second capacitor C2 is connected with the to-be-reset device 23.
Specifically, the first capacitor C1 has the function of blocking direct current and alternating current, so that the square wave reset signal can pass through the first capacitor C1, and the single level signal cannot pass through the first capacitor C1. When the control terminal of the switching tube Q1 is at low level, the switching tube Q1 is turned off. When the control terminal of the switching tube Q1 is at high level, the switching tube Q1 is turned on.
When the reset signal generator 21 outputs the square wave reset signal, the square wave reset signal passes through the first capacitor C1, and controls the switching on and off of the switching tube Q1 through high and low levels, so as to control the charging and discharging of the second capacitor C2. Specifically, when the voltage reaching the control terminal of the switching tube Q1 through the first capacitor C1 is at a low level, the switching tube Q1 is turned off, the power supply DC charges the second capacitor C2 through the second resistor R3 and the fourth resistor R4, when the voltage reaching the control terminal of the switching tube Q1 through the first capacitor C1 is at a high level, the switching tube Q1 is turned on, and the second capacitor C2 is grounded through the fourth resistor R4 and the switching tube Q1 to perform discharging. When the reset signal generator 21 outputs the square wave reset signal, the square wave reset signal passes through the first capacitor C1, so that the second capacitor C2 is repeatedly charged and discharged, and the discharging speed is greater than the charging speed, so that the second capacitor C2 is not fully charged and shows a low level, that is, a low level reset control signal is output, and a device to be reset (such as a DSP, an FPGA, and the like) is controlled to perform a reset operation. When the reset signal generator 21 stops outputting the square wave reset signal, the control terminal of the switching tube Q1 is at a low level, the switching tube Q1 is turned off, the power supply DC continuously charges the second capacitor C2 through the second resistor R3 and the fourth resistor R4, the second capacitor C2 is fully charged, and a high potential is displayed, that is, a high level control signal is output, so as to control the device to be reset (such as a DSP, an FPGA, and the like) to normally operate.
Therefore, when the reset signal generator is damaged, the square wave reset signal is not output, the switching tube Q1 is always in the off state, and the square wave detector 22 does not output the reset control signal, so that the device to be reset (such as DSP, FPGA, etc.) is not continuously reset, but is enabled to work normally. In addition, when the square wave reset signal output by the reset generator is interfered and accidentally jumps, an abnormal square wave reset signal can be formed in a very short time, so that the change of the charging and discharging time of the second capacitor C2 is very short, and the low voltage is still displayed, so that the output of the reset control signal by the square wave detector 22 is not influenced, and the error reset operation of the reset device (such as a DSP, an FPGA and the like) which fails in the middle of the reset operation can not occur.
In order to clearly illustrate the operation principle of the reset control apparatus according to the embodiment of the present invention, the following description is made by way of specific examples. Fig. 4 is a schematic flowchart of a reset control method of the reset control device based on the embodiment shown in fig. 3, and as shown in fig. 4, the reset control method includes:
s401, resetting the power-on initial of the control device.
S402, the reset signal generator outputs a square wave reset signal to the square wave detector for 100 milliseconds, and the device to be reset is controlled to reset.
S403, the reset signal generator stops outputting the square wave reset signal to the square wave detector.
S404, the to-be-reset device sends a detection signal back to the reset signal generator.
S405, the reset signal generator determines whether the recheck signal has 2 rising edges detected within 800 msec.
If yes, the process proceeds to step S406. If not, the process proceeds to step S407.
S406, judging that the device to be reset is normal. Returning to step S405, the reset signal generator continues to determine whether the back detection signal has 2 rising edges within 800 milliseconds.
And S407, judging that the to-be-reset device is halted. Returning to the step S402, the reset signal generator outputs the square wave reset signal to the square wave detector again for 100 milliseconds, and controls the device to be reset to reset.
The reset control device of the embodiment of the invention adopts the square wave reset signal to control the device to be reset to reset, when the reset signal generator is damaged, the square wave reset signal can not be output, and further the square wave detector can not output the reset control signal because the square wave reset signal can not be detected, so that the device to be reset (such as DSP, FPGA and the like) can not be continuously reset, and the device to be reset can normally work. In addition, when the square wave reset signal output by the reset generator is interfered and accidental jump occurs, an abnormal square wave reset signal in a very short time (smaller than a second reset time interval) can be formed, so that the square wave detector is not influenced to output a reset control signal, and the error reset operation of failure in the reset operation process of the reset device (such as a DSP, an FPGA and the like) can not occur.
Fig. 5 is a flowchart illustrating a reset control method according to an embodiment of the present invention. The reset control method according to the embodiment of the present invention can be implemented by the reset control apparatus shown in the above-described embodiment. As shown in fig. 5, the reset control method according to the embodiment of the present invention includes the following steps:
and S501, controlling the reset signal generator to output the square wave reset signal to the square wave detector within a preset first reset time interval.
And S502, controlling the square wave detector to output a reset control signal to the to-be-reset device when detecting the square wave reset signal.
And S503, controlling the to-be-reset device to reset after receiving the reset control signal.
Further, in a possible implementation manner of the embodiment of the present invention, step S502 may specifically include: and when detecting that the square wave reset signal exceeds a preset second reset time interval, the control square wave detector outputs a reset control signal to the to-be-reset device, wherein the second reset time interval is smaller than the first reset time interval.
Further, in a possible implementation manner of the embodiment of the present invention, the reset control method of the embodiment of the present invention further includes: controlling the reset device to normally work after the reset is finished, and outputting a return detection signal to the reset signal generator; and controlling the reset signal generator to output the square wave reset signal to the square wave detector again within the reset time interval when the return detection signal is detected to be abnormal.
It should be noted that the foregoing explanation of the embodiment of the reset control apparatus is also applicable to the reset control method of the embodiment, and is not repeated here.
According to the reset control method, the square wave reset signal is adopted to control the to-be-reset device to reset, when the reset signal generator is damaged, the square wave reset signal cannot be output, and further, the square wave detector cannot output the reset control signal because the square wave reset signal cannot be detected, so that the to-be-reset device (such as a DSP (digital signal processor), an FPGA (field programmable gate array) and the like) cannot be continuously reset, and the to-be-reset device can normally work. In addition, when the square wave reset signal output by the reset generator is interfered and accidental jump occurs, an abnormal square wave reset signal in a very short time (smaller than a second reset time interval) can be formed, so that the square wave detector is not influenced to output a reset control signal, and the error reset operation of failure in the reset operation process of the reset device (such as a DSP, an FPGA and the like) can not occur.
In order to implement the foregoing embodiments, the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the reset control method proposed in the foregoing embodiments.
In order to implement the above-mentioned embodiments, the present invention also proposes a non-transitory computer-readable storage medium having stored thereon a computer program, which is executed by a processor, for implementing the reset control method proposed by the foregoing embodiments.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware that is related to instructions of a program, and the program may be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (9)
1. A reset control apparatus, comprising:
the reset signal generator is used for outputting a square wave reset signal to the square wave detector within a preset first reset time interval;
the square wave detector is used for outputting a reset control signal to the to-be-reset device when the square wave reset signal is detected;
and the to-be-reset device is used for resetting after receiving the reset control signal.
2. The reset control device of claim 1, wherein the square wave detector is specifically configured to:
and when the square wave reset signal is detected to exceed a preset second reset time interval, outputting the reset control signal to the to-be-reset device, wherein the second reset time interval is smaller than the first reset time interval.
3. The reset control apparatus of claim 1, wherein the to-be-reset device is further configured to: after the reset is finished, the normal work is carried out, and a return detection signal is output to the reset signal generator;
the reset signal generator is further configured to: and when the return detection signal is detected to be abnormal, outputting the square wave reset signal to the square wave detector within the first reset time interval again.
4. The reset control apparatus of claim 2, wherein the square wave detector comprises:
the first end of the first capacitor is connected with the output end of the reset signal generator;
a first resistor, a first end of the first resistor being connected to a second end of the first capacitor;
the first end of the second resistor is connected with a power supply;
the control end of the switch tube is connected with the second end of the first resistor, the first end of the switch tube is connected with the second end of the second resistor, and the second end of the switch tube is grounded;
a first end of the third resistor is connected with the control end of the switch tube, and a second end of the third resistor is grounded;
a first end of the fourth resistor is connected with the first end of the switching tube;
and a first end of the second capacitor is connected with a second end of the fourth resistor, a second end of the second capacitor is grounded, and a first end of the second capacitor is connected with the to-be-reset device.
5. A reset control method is characterized by comprising the following steps:
controlling a reset signal generator to output a square wave reset signal to a square wave detector within a preset first reset time interval;
controlling the square wave detector to output a reset control signal to the to-be-reset device when detecting the square wave reset signal;
and controlling the to-be-reset device to reset after receiving the reset control signal.
6. The reset control method according to claim 5, wherein the controlling the square wave detector to output a reset control signal to the to-be-reset device when detecting the square wave reset signal comprises:
and controlling the square wave detector to output the reset control signal to the to-be-reset device when detecting that the square wave reset signal exceeds a preset second reset time interval, wherein the second reset time interval is smaller than the first reset time interval.
7. The reset control method according to claim 5, further comprising:
controlling the to-be-reset device to normally work after the reset is finished, and outputting a return detection signal to the reset signal generator;
and controlling the reset signal generator to output the square wave reset signal to the square wave detector again within the reset time interval when the return detection signal is detected to be abnormal.
8. An electronic device, comprising: memory, processor and computer program stored on the memory and executable on the processor, the processor executing the program to implement the reset control method according to any one of claims 5 to 7.
9. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that the program is executed by a processor for implementing the reset control method according to any one of claims 5-7.
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| CN113325779A (en) * | 2021-06-07 | 2021-08-31 | 沈阳铁路信号有限责任公司 | Reset signal safety output circuit and implementation method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040210785A1 (en) * | 2002-09-07 | 2004-10-21 | Micrologic, Inc. | Method of and apparatus for achieving "watch dog" functions in microcontrollers and microcomputers and the like, required to shut down for extended periods of time for energy-conservation purposes |
| JP2005092314A (en) * | 2003-09-12 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Hang-up detecting device for microcomputer system |
| US20140089706A1 (en) * | 2012-09-21 | 2014-03-27 | Atmel Corporation | Delaying reset signals in a microcontroller system |
| CN106292434A (en) * | 2016-08-19 | 2017-01-04 | 东风汽车公司 | A kind of watchdog circuit for automobile electronic controller |
| CN206096920U (en) * | 2016-08-15 | 2017-04-12 | 威胜集团有限公司 | Controller reset circuit and metering device who makes with this circuit |
| CN106951336A (en) * | 2017-03-24 | 2017-07-14 | 北京经纬恒润科技有限公司 | A kind of MCU repositioning method, apparatus and system |
| CN107122032A (en) * | 2016-02-25 | 2017-09-01 | 西安中兴新软件有限责任公司 | Terminal, crash reset control circuit and method |
| CN107333367A (en) * | 2017-07-05 | 2017-11-07 | 深圳市晟碟半导体有限公司 | A kind of parameter adjustment system and method for sensing lamp |
| CN107368171A (en) * | 2017-07-20 | 2017-11-21 | 朱伟 | A kind of reset circuit of closed-loop control |
-
2018
- 2018-07-27 CN CN201810847491.1A patent/CN110764599B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040210785A1 (en) * | 2002-09-07 | 2004-10-21 | Micrologic, Inc. | Method of and apparatus for achieving "watch dog" functions in microcontrollers and microcomputers and the like, required to shut down for extended periods of time for energy-conservation purposes |
| JP2005092314A (en) * | 2003-09-12 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Hang-up detecting device for microcomputer system |
| US20140089706A1 (en) * | 2012-09-21 | 2014-03-27 | Atmel Corporation | Delaying reset signals in a microcontroller system |
| CN107122032A (en) * | 2016-02-25 | 2017-09-01 | 西安中兴新软件有限责任公司 | Terminal, crash reset control circuit and method |
| CN206096920U (en) * | 2016-08-15 | 2017-04-12 | 威胜集团有限公司 | Controller reset circuit and metering device who makes with this circuit |
| CN106292434A (en) * | 2016-08-19 | 2017-01-04 | 东风汽车公司 | A kind of watchdog circuit for automobile electronic controller |
| CN106951336A (en) * | 2017-03-24 | 2017-07-14 | 北京经纬恒润科技有限公司 | A kind of MCU repositioning method, apparatus and system |
| CN107333367A (en) * | 2017-07-05 | 2017-11-07 | 深圳市晟碟半导体有限公司 | A kind of parameter adjustment system and method for sensing lamp |
| CN107368171A (en) * | 2017-07-20 | 2017-11-21 | 朱伟 | A kind of reset circuit of closed-loop control |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113325779A (en) * | 2021-06-07 | 2021-08-31 | 沈阳铁路信号有限责任公司 | Reset signal safety output circuit and implementation method |
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| CN110764599B (en) | 2021-12-10 |
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