CN110739944B - Low-voltage reset circuit - Google Patents
Low-voltage reset circuit Download PDFInfo
- Publication number
- CN110739944B CN110739944B CN201911059977.XA CN201911059977A CN110739944B CN 110739944 B CN110739944 B CN 110739944B CN 201911059977 A CN201911059977 A CN 201911059977A CN 110739944 B CN110739944 B CN 110739944B
- Authority
- CN
- China
- Prior art keywords
- delay
- voltage
- resistor
- comparator
- reset circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Electronic Switches (AREA)
Abstract
The invention provides a low-voltage reset circuit, which comprises: the device comprises a first resistor, a second resistor, a delay capacitor, a band gap reference source and a comparator. The first resistor and the second resistor are connected in series and are coupled between a power supply voltage and ground. The delay resistor and the delay capacitor are connected in series and are coupled between the power supply voltage and the ground. The comparator is provided with a positive input end, a first negative input end, a second negative input end and an output end, and the positive input end of the comparator is connected with a reference voltage VREF generated by the band gap reference source; the first negative input end of the comparator is connected with a sampling voltage VSAMP drawn out between the first resistor and the second resistor; the second negative input end of the comparator is connected with delay voltage VDLY extracted between the delay resistor and the delay capacitor; the output end of the comparator is used as the output result of the low-voltage reset circuit.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits or digital-analog hybrid integrated circuits, in particular to a low-voltage reset circuit.
Background
The main function of the Low Voltage Reset (LVR) circuit is to generate a Reset (Reset) signal with a high level pulse of a proper width to Reset the system when the power supply voltage is lower than a set voltage value during the power-up or power-down process of the system, so as to ensure the stability of all internal digital logic. LVR circuits are an essential important circuit module of a Microcontroller (MCU) system and are widely applied to the field of analog integrated circuits and digital-analog hybrid integrated circuits.
The problem that the traditional high-precision low-voltage reset circuit is easy to generate low-voltage reset failure when the system is powered on rapidly is solved, other circuit modules are needed to be added in the system to compensate the serious problem caused by the rapid power on, but the newly added circuit not only needs to increase power consumption and area, but also has more or less defects in other aspects.
Disclosure of Invention
The invention aims to provide a high-reliability low-voltage reset circuit which can accurately generate a high-level pulse reset signal in the process of rapidly powering up a system power supply VDD. The high-reliability low-voltage reset circuit is widely applied to a monolithic integrated circuit chip of an MCU system.
The invention provides a low-voltage reset circuit, which comprises:
a first resistor R1 (101), a second resistor R2 (102), a delay resistor R0 (103), a delay capacitor C0 (104), a band gap reference source (105) and a comparator CMP (106);
the first resistor R1 (101) and the second resistor R2 (102) are connected in series and are coupled between a power supply voltage and ground;
the delay resistor R0 (103) and the delay capacitor C0 (104) are connected in series and are coupled between the power supply voltage and the ground;
the comparator CMP (106) is provided with a positive input end, a first negative input end, a second negative input end and an output end, and the positive input end of the comparator CMP (106) is connected with a reference voltage VREF generated by the band gap reference source (105); a first negative input end of the comparator CMP (106) is connected with a sampling voltage VSAMP drawn between the first resistor R1 (101) and the second resistor R2 (102); the second negative input end of the comparator CMP (106) is connected with a delay voltage VDLY extracted between the delay resistor R0 (103) and the delay capacitor C0 (104); an output terminal of the comparator CMP (106) is used as an output result of the low-voltage reset circuit.
In one embodiment, the relationship of the positive input, the first negative input, the second negative input, and the output of the comparator is as follows:
when the delay voltage VDLY is smaller than the reference voltage VREF and the sampling voltage VSAMP is smaller than the reference voltage VREF, the output end of the comparator outputs a high level;
when the delay voltage VDLY < reference voltage VREF and the sampling voltage VSAMP > reference voltage VREF, the output terminal of the comparator outputs a high level;
when the delay voltage VDLY > the reference voltage VREF and the sampling voltage VSAMP < the reference voltage VREF, the output end of the comparator outputs a high level;
when the delay voltage VDLY > the reference voltage VREF and the sampling voltage VSAMP > the reference voltage VREF, the output terminal of the comparator outputs a low level.
In one embodiment, the delay resistance may include one or a combination of the following: common resistor, NMOS transistor, PMOS transistor.
In one embodiment, the gate voltage of the PMOS transistor is controlled by a node internal to the bandgap reference source circuit.
In one embodiment, the bandgap reference source has one or more PMOS transistors, and the one or more PMOS transistors of the bandgap reference source and the PMOS transistor of the delay resistor form a current mirror; the current of the PMOS transistor of the bandgap reference source determines the magnitude of the reference voltage VREF, and the current of the PMOS transistor of the delay resistor determines the magnitude of the delay voltage VDLY.
In one embodiment, the gate voltage of the NMOS transistor is controlled by a node internal to the bandgap reference source circuit.
In one embodiment, the bandgap reference source has one or more NMOS transistors, and the one or more NMOS transistors of the bandgap reference source and the NMOS transistor of the delay resistor form a current mirror; the current of the NMOS transistor of the bandgap reference source determines the magnitude of the reference voltage VREF, and the current of the NMOS transistor of the delay resistor determines the magnitude of the delay voltage VDLY.
In one embodiment, the comparator is a three-input comparator, the three-input comparator comprising:
a two-input comparator; and
an NMOS transistor or a PMOS transistor coupled to a drain terminal of the transistor connected to the negative input terminal of the two-input comparator;
the positive input end of the two-input comparator is used as the positive input end of the three-input comparator to be connected with the reference voltage VREF, the negative input end of the two-input comparator is used as the first negative input end of the three-input comparator to be connected with the sampling voltage VSAMP, and the grid electrode of the NMOS transistor or the PMOS transistor is used as the second negative input end of the three-input comparator to be connected with the delay voltage VDLY.
The invention also provides a low-voltage reset circuit, which comprises:
a first resistor R1 (301), a second resistor R2 (302), a delay resistor R0 (303), a delay capacitor C0 (304), a band gap reference source (305) and a comparator CMP (306);
the first resistor R1 (301) and the second resistor R2 (302) are connected in series and are coupled between a power supply voltage and ground;
the delay resistor R0 (303) and the delay capacitor C0 (304) are connected in series, one end of the delay resistor R0 (303) is coupled between the first resistor R1 (301) and the second resistor R2 (302), the other end of the delay resistor R0 is coupled with one end of the delay capacitor C0 (304), and the other end of the delay capacitor C0 (304) is coupled with the ground;
the positive input end of the comparator CMP (306) is connected with a reference voltage VREF generated by the band-gap reference source (305); the sampling extracted between the negative input end of the comparator CMP (306) and the delay resistor R0 (303) and the delay capacitor C0 (304) is connected with the delay voltage VSAMP_DLY; an output terminal of the comparator CMP (306) is used as an output result of the low-voltage reset circuit.
In one embodiment, the relationship of the positive input, negative input and output of the comparator is as follows:
when the sampling and delay voltage VSAMP_DLY > is reference voltage VREF, the output end of the comparator outputs low level;
when the sampling and delay voltage vsamp_dly < the reference voltage VREF, the output terminal of the comparator outputs a high level.
The low-voltage reset circuit has the beneficial technical effects that: the low-voltage reset circuit breaks through the limitation of the traditional low-voltage reset circuit, and is a high-reliability and high-precision low-voltage reset circuit capable of meeting the requirement of quick power-on. According to the low-voltage reset circuit, only one RC delay circuit and one MOS transistor are added on the basis of a traditional low-voltage reset circuit, and a reset signal of a high-level pulse can be correctly generated in the process of rapidly powering up the system. In addition, the high-reliability low-voltage reset circuit of the invention has little increase of chip area, power consumption and cost compared with the prior art, and can obviously improve the circuit performance without introducing other new defects.
Drawings
The foregoing summary of the invention, as well as the following detailed description of the invention, will be better understood when read in conjunction with the accompanying drawings. It is to be noted that the drawings are merely examples of the claimed invention. In the drawings, like reference numbers indicate identical or similar elements.
FIG. 1A illustrates a prior art low voltage reset circuit architecture;
FIG. 1B is a schematic diagram showing a prior art low voltage reset circuit failing during a system power-up process;
FIG. 2A shows an architecture schematic of a low voltage reset circuit according to an embodiment of the invention;
FIG. 2B is a schematic diagram illustrating the operation of the low voltage reset circuit during a system power-up process according to an embodiment of the present invention;
FIG. 3A is a schematic diagram of a low voltage reset circuit according to an embodiment of the invention;
FIG. 3B is a schematic diagram illustrating the operation of the low voltage reset circuit during a system power-up process according to an embodiment of the present invention;
FIGS. 4A-4E are schematic diagrams showing several different implementations of the delay resistor R0 in the low voltage reset circuit of the present invention;
FIG. 5 is a schematic diagram of an architecture of a low voltage reset circuit according to an embodiment of the present invention, in which an internal node of a bandgap reference circuit is used to control a gate of a PMOS transistor to realize a delay resistor function; and
fig. 6A and 6B are schematic diagrams illustrating a structure of a comparator CMP in a low voltage reset circuit according to an embodiment of the invention.
Detailed Description
The detailed features and advantages of the present invention will be readily apparent to those skilled in the art from the following detailed description, claims, and drawings that follow.
The main function of the Low Voltage Reset (LVR) circuit is to generate a Reset (Reset) signal with a high level pulse of a proper width to Reset the system when the power supply voltage is lower than a set voltage value during the power-up or power-down process of the system, so as to ensure the stability of all internal digital logic. LVR circuits are an essential important circuit module of a Microcontroller (MCU) system and are widely applied to the field of analog integrated circuits and digital-analog hybrid integrated circuits.
Fig. 1A illustrates a conventional, commonly employed high precision low voltage reset circuit architecture. As shown in fig. 1A, a BANDGAP reference source (BANDGAP) plus a Comparator (CMP) is implemented. But this architecture has a serious problem: because the band gap reference source circuit has longer establishment time, when the system is powered on rapidly, the rising speed of the sampling voltage VSAMP led OUT from the first resistor R1 and the second resistor R2 is faster than the establishment speed of the reference voltage VREF, so that the voltage of the sampling voltage VSAMP is always greater than the voltage of the reference voltage VREF, the output end OUT of the comparator CMP in the low-voltage reset circuit is always in a low level, a reset signal of high-level pulse cannot be generated, and the system is powered on to fail, as shown in FIG. 1B. The system also needs to add other circuit modules to compensate for this serious problem caused by rapid power-up, but the newly added circuit not only needs to increase power consumption and area, but also has some other disadvantages more or less.
The invention aims to provide a low-voltage reset circuit which can accurately generate a high-level pulse reset signal in the process of rapidly powering up a system power supply VDD.
In order to solve the above technical problems, the present invention provides a low voltage reset circuit.
Fig. 2A illustrates a high reliability low voltage reset circuit according to one embodiment of the present invention. As shown in fig. 2A, the low voltage reset circuit includes: a first resistor R1 (101), a second resistor R2 (102), a delay resistor R0 (103), a delay capacitor C0 (104), a band gap reference source (105) and a comparator CMP (106).
The first resistor R1 (101) and the second resistor R2 (102) are connected in series and are coupled between a power supply voltage and ground;
the delay resistor R0 (103) and the delay capacitor C0 (104) are connected in series and are coupled between the power supply voltage and the ground;
the positive input end of the comparator CMP (106) is connected with a reference voltage VREF generated by the band gap reference source (105); a first negative input end of the comparator CMP (106) is connected with a sampling voltage VSAMP drawn between the first resistor R1 (101) and the second resistor R2 (102); the second negative input end of the comparator CMP (106) is connected with a delay voltage VDLY extracted between the delay resistor R0 (103) and the delay capacitor C0 (104); an output terminal OUT of the comparator CMP (106) serves as an output result of the low-voltage reset circuit.
The comparator CMP (106) has two negative inputs VDLY and VSAMP, a positive input VREF and an output OUT, the functional description is shown in table 1:
TABLE 1
| Three input voltage comparison | Output OUT state |
| V(VDLY)<V(VREF)&V(VSAMP)<V(VREF) | High level |
| V(VDLY)<V(VREF)&V(VSAMP)>V(VREF) | High level |
| V(VDLY)>V(VREF)&V(VSAMP)<V(VREF) | High level |
| V(VDLY)>V(VREF)&V(VSAMP)>V(VREF) | Low level |
The working principle of the low-voltage reset circuit is as follows: as shown in fig. 2A and 2B, during the rapid rise of the power supply voltage VDD, the delay voltage VDLY drawn between the delay resistor R0 and the delay capacitor C0 does not rise as fast as VDD, but is delayed for a period of time (depending on the R0 and C0 design values, i.e., the product of R0 and C0), that is, for a period of time (the time corresponding to the hatched portion in fig. 2B), VDLY is at a lower level than the reference voltage VREF generated by the bandgap reference source, and the comparator CMP can generate a reset signal of a high level pulse during this period of time.
The low-voltage reset circuit architecture provided by the invention can also be realized by a simplified circuit.
FIG. 3A is a simplified circuit schematic of a low voltage reset circuit according to one embodiment of the present invention. It can be seen that the comparator CMP has been simplified as a conventional two-input comparator, and the delay voltage VDLY and the sampling voltage VSAMP are combined into a voltage VSAMP DLY (hereinafter referred to as sampling and delay voltage VSAMP DLY).
Specifically, the low-voltage reset circuit comprises a first resistor R1 (301), a second resistor R2 (302), a delay resistor R0 (303), a delay capacitor C0 (304), a band-gap reference source (305) and a comparator CMP (306).
The first resistor R1 (301) and the second resistor R2 (302) are connected in series and are coupled between a power supply voltage and ground.
The delay resistor R0 (303) and the delay capacitor C0 (304) are connected in series, one end of the delay resistor R0 (303) is coupled between the first resistor R1 (301) and the second resistor R2 (302), the other end of the delay resistor R0 is coupled with one end of the delay capacitor C0 (304), and the other end of the delay capacitor C0 (304) is coupled with the ground.
The positive input end of the comparator CMP (306) is connected with a reference voltage VREF generated by the band-gap reference source (305); the sampling extracted between the negative input end of the comparator CMP (306) and the delay resistor R0 (303) and the delay capacitor C0 (304) is connected with the delay voltage VSAMP_DLY; an output terminal of the comparator CMP (306) is used as an output result of the low-voltage reset circuit.
The relationship between the positive input end, the negative input end and the output end of the comparator is as follows:
when the sampling and delay voltage VSAMP_DLY > is reference voltage VREF, the output end of the comparator outputs low level;
when the sampling and delay voltage vsamp_dly < the reference voltage VREF, the output terminal of the comparator outputs a high level.
The low voltage reset circuit in this embodiment works very similar to the low voltage reset circuit in fig. 2A: during the rapid rise of the power supply voltage VDD, the sampling and delay voltage vsamp_dly will be at a lower level for a period of time (the time corresponding to the shaded portion shown in fig. 3B), which is lower than the reference voltage VREF generated by the bandgap reference source, and the comparator CMP can generate a high-level pulsed reset signal during this period of time. This simplified circuit has one feature: because of the delay circuit, the sampling and delay voltage VSAMP DLY can be charged and discharged slowly, so the circuit is suitable for specific application environments.
The devices and circuits in the low voltage reset circuit architecture proposed by the present invention can be implemented in different ways. Several circuit implementations are provided below, but those skilled in the art will appreciate that other variations or alternatives exist without departing from the spirit of the invention.
1) For delay resistor R0
Fig. 4A to 4E are schematic diagrams showing several different implementations of the delay resistor R0 in the low voltage reset circuit according to the present invention. Fig. 4A shows that the implementation manner of the delay resistor R0 is a common resistor; FIGS. 4B and 4C illustrate that the delay resistor R0 implementation may employ NMOS type or PMOS type transistors, wherein the gate is controlled with a fixed voltage; fig. 4D and 4E show that the gate of the NMOS or PMOS type transistor may be controlled by a certain node VX inside the bandgap reference source circuit in addition to a fixed voltage control.
Fig. 5 is a schematic diagram of an architecture of a low-voltage reset circuit according to an embodiment of the present invention, in which an internal node of a bandgap reference circuit is used to control a gate of a PMOS transistor to implement a delay resistance function. The control mode has simple circuit and obvious advantages: the bandgap reference circuit may include one or more PMOS transistors P1. The reference voltage VREF is determined by the current of the PMOS transistor P1, the delay voltage VDLY is determined by the current of the PMOS transistor P0 (the delay resistance function is realized by the PMOS transistor P0), and P1 and P0 constitute a current mirror structure. The designer can precisely control the rising speed of the reference voltage VREF and the delay voltage VDLY in the power-up process by controlling the proportion of the number of the P1 and P0 transistors, so that the width of the high-level pulse of the reset signal generated by the system is precisely controlled.
Similarly, for the case that the delay resistor adopts an NMOS type transistor, the bandgap reference source circuit may include one or more NMOS transistors and an NMOS transistor of the delay resistor, where 1:1 or 1: n to realize accurate control of the rising speed of the reference voltage VREF and the delay voltage VDLY in the power-on process, thereby accurately controlling the width of the high-level pulse of the reset signal generated by the system.
(2) For comparator CMP
Unlike conventional comparators, the comparator CMP of the present application is a three-input comparator, comprising two negative inputs, a positive input.
Fig. 6A and 6B are schematic diagrams illustrating a structure of a comparator CMP in a low voltage reset circuit according to an embodiment of the present invention. It can be seen that the comparator of the present application has an NMOS transistor (N0 transistor in fig. 6A) or PMOS transistor (P0 transistor in fig. 6B) in series with the drain terminal of the transistor connected to the negative input terminal of the conventional two-input comparator.
Specifically, the three-input comparator of the present application includes: a two-input comparator; and an NMOS transistor or PMOS transistor coupled to the drain terminal of the transistor connected to the negative input terminal of the two-input comparator.
The positive input end of the two-input comparator is used as the positive input end of the three-input comparator to be connected with the reference voltage VREF, the negative input end of the two-input comparator is used as the first negative input end of the three-input comparator to be connected with the sampling voltage VSAMP, and the grid electrode of the NMOS transistor or the PMOS transistor is used as the second negative input end of the three-input comparator to be connected with the delay voltage VDLY.
The series connection method is applicable to all types and architectures of comparators and has the same working principle as the traditional comparator circuit, and is not described here.
In summary, the low-voltage reset circuit of the invention has very beneficial technical effects: the low-voltage reset circuit breaks through the limitation of the traditional low-voltage reset circuit, and is a high-reliability and high-precision low-voltage reset circuit capable of meeting the requirement of quick power-on. According to the low-voltage reset circuit, only one RC delay circuit and one MOS transistor are added on the basis of a traditional low-voltage reset circuit, and a reset signal of a high-level pulse can be correctly generated in the process of rapidly powering up the system. In addition, the high-reliability low-voltage reset circuit of the invention has little increase of chip area, power consumption and cost compared with the prior art, and can obviously improve the circuit performance without introducing other new defects.
This application uses specific words to describe embodiments of the application. Reference to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic is associated with at least one embodiment of the present application. Thus, it should be emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various positions in this specification are not necessarily referring to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of the present application may be combined as suitable.
Likewise, it should be noted that in order to simplify the presentation disclosed herein and thereby aid in understanding one or more inventive embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof. This method of disclosure, however, is not intended to imply that more features than are presented in the claims are required for the subject application.
The terms and expressions which have been employed herein are used as terms of description and not of limitation. The use of these terms and expressions is not meant to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible and are intended to be included within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.
Also, it should be noted that while the present invention has been described with reference to the particular embodiments presently, it will be appreciated by those skilled in the art that the above embodiments are provided for illustration only and that various equivalent changes or substitutions may be made without departing from the spirit of the invention, and therefore, the changes and modifications to the above embodiments shall fall within the scope of the claims of the present application as long as they are within the true spirit of the invention.
Claims (10)
1. A low voltage reset circuit, the low voltage reset circuit comprising:
a first resistor R1 (101), a second resistor R2 (102), a delay resistor R0 (103), a delay capacitor C0 (104), a band gap reference source (105) and a comparator CMP (106);
the first resistor R1 (101) and the second resistor R2 (102) are connected in series and are coupled between a power supply voltage and ground;
the delay resistor R0 (103) and the delay capacitor C0 (104) are connected in series and are coupled between the power supply voltage and the ground;
the comparator CMP (106) is provided with a positive input end, a first negative input end, a second negative input end and an output end, and the positive input end of the comparator CMP (106) is connected with a reference voltage VREF generated by the band gap reference source (105); a first negative input end of the comparator CMP (106) is connected with a sampling voltage VSAMP drawn between the first resistor R1 (101) and the second resistor R2 (102); the second negative input end of the comparator CMP (106) is connected with a delay voltage VDLY extracted between the delay resistor R0 (103) and the delay capacitor C0 (104); an output terminal of the comparator CMP (106) is used as an output result of the low-voltage reset circuit.
2. The low voltage reset circuit of claim 1 wherein the relationship of the positive input, the first negative input, the second negative input, and the output of the comparator is as follows:
when the delay voltage VDLY is smaller than the reference voltage VREF and the sampling voltage VSAMP is smaller than the reference voltage VREF, the output end of the comparator outputs a high level;
when the delay voltage VDLY < reference voltage VREF and the sampling voltage VSAMP > reference voltage VREF, the output terminal of the comparator outputs a high level;
when the delay voltage VDLY > the reference voltage VREF and the sampling voltage VSAMP < the reference voltage VREF, the output end of the comparator outputs a high level;
when the delay voltage VDLY > the reference voltage VREF and the sampling voltage VSAMP > the reference voltage VREF, the output terminal of the comparator outputs a low level.
3. The low voltage reset circuit of claim 1 wherein the delay resistor may comprise one or a combination of: common resistor, NMOS transistor, PMOS transistor.
4. A low voltage reset circuit as claimed in claim 3 wherein the gate voltage of the PMOS transistor is controlled by a node internal to the bandgap reference source circuit.
5. The low voltage reset circuit of claim 4 wherein the bandgap reference source has one or more PMOS transistors, the one or more PMOS transistors of the bandgap reference source forming a current mirror with the PMOS transistors of the delay resistor; the current of the PMOS transistor of the bandgap reference source determines the magnitude of the reference voltage VREF, and the current of the PMOS transistor of the delay resistor determines the magnitude of the delay voltage VDLY.
6. A low voltage reset circuit as claimed in claim 3 wherein the gate voltage of the NMOS transistor is controlled by a node internal to the bandgap reference source circuit.
7. The low voltage reset circuit of claim 6 wherein the bandgap reference source has one or more NMOS transistors, the one or more NMOS transistors of the bandgap reference source forming a current mirror with the NMOS transistors of the delay resistor; the current of the NMOS transistor of the bandgap reference source determines the magnitude of the reference voltage VREF, and the current of the NMOS transistor of the delay resistor determines the magnitude of the delay voltage VDLY.
8. The low voltage reset circuit of claim 6 wherein said comparator is a three-input comparator comprising:
a two-input comparator; and
an NMOS transistor or a PMOS transistor coupled to a drain terminal of the transistor connected to the negative input terminal of the two-input comparator;
the positive input end of the two-input comparator is used as the positive input end of the three-input comparator to be connected with the reference voltage VREF, the negative input end of the two-input comparator is used as the first negative input end of the three-input comparator to be connected with the sampling voltage VSAMP, and the grid electrode of the NMOS transistor or the PMOS transistor is used as the second negative input end of the three-input comparator to be connected with the delay voltage VDLY.
9. A low voltage reset circuit, the low voltage reset circuit comprising:
a first resistor R1 (301), a second resistor R2 (302), a delay resistor R0 (303), a delay capacitor C0 (304), a band gap reference source (305) and a comparator CMP (306);
the first resistor R1 (301) and the second resistor R2 (302) are connected in series and are coupled between a power supply voltage and ground;
the delay resistor R0 (303) and the delay capacitor C0 (304) are connected in series, one end of the delay resistor R0 (303) is coupled between the first resistor R1 (301) and the second resistor R2 (302), the other end of the delay resistor R0 is coupled with one end of the delay capacitor C0 (304), and the other end of the delay capacitor C0 (304) is coupled with the ground;
the positive input end of the comparator CMP (306) is connected with a reference voltage VREF generated by the band-gap reference source (305); the sampling extracted between the negative input end of the comparator CMP (306) and the delay resistor R0 (303) and the delay capacitor C0 (304) is connected with the delay voltage VSAMP_DLY; an output terminal of the comparator CMP (306) is used as an output result of the low-voltage reset circuit.
10. The low voltage reset circuit of claim 9 wherein the relationship of the positive input, negative input and output of the comparator is as follows:
when the sampling and delay voltage VSAMP_DLY > is reference voltage VREF, the output end of the comparator outputs low level;
when the sampling and delay voltage vsamp_dly < the reference voltage VREF, the output terminal of the comparator outputs a high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911059977.XA CN110739944B (en) | 2019-11-01 | 2019-11-01 | Low-voltage reset circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911059977.XA CN110739944B (en) | 2019-11-01 | 2019-11-01 | Low-voltage reset circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110739944A CN110739944A (en) | 2020-01-31 |
| CN110739944B true CN110739944B (en) | 2023-05-02 |
Family
ID=69270550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911059977.XA Active CN110739944B (en) | 2019-11-01 | 2019-11-01 | Low-voltage reset circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110739944B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734679A (en) * | 2015-02-05 | 2015-06-24 | 西安中颖电子有限公司 | Low-voltage reset circuit |
| JP2019036002A (en) * | 2017-08-10 | 2019-03-07 | 株式会社ミツトヨ | Reset circuit and reference voltage generation circuit |
-
2019
- 2019-11-01 CN CN201911059977.XA patent/CN110739944B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734679A (en) * | 2015-02-05 | 2015-06-24 | 西安中颖电子有限公司 | Low-voltage reset circuit |
| JP2019036002A (en) * | 2017-08-10 | 2019-03-07 | 株式会社ミツトヨ | Reset circuit and reference voltage generation circuit |
Non-Patent Citations (2)
| Title |
|---|
| 方明 ; 姚若河 ; .基于施密特比较器的高可靠上电复位电路.微电子学.2010,(第05期),全文. * |
| 陈铖颖 ; 陈黎明 ; 范军 ; 胡晓宇 ; 黑勇 ; .一种用于助听器SoC的上电复位及欠压检测电路.微电子学.2015,(第05期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110739944A (en) | 2020-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8803580B2 (en) | Power-on-reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage | |
| CN109088532B (en) | Current type segmented gate drive circuit with active clamp | |
| US20120044021A1 (en) | Differential amplifier circuit | |
| CN112039507B (en) | High-precision power-on reset and low-power-consumption power-off reset circuit | |
| US8786324B1 (en) | Mixed voltage driving circuit | |
| CN110837267B (en) | High-reliability power-on reset circuit | |
| CN111934657B (en) | Low-power-consumption power-on reset and power-off reset circuit | |
| CN103901935A (en) | Automatic biasing band-gap reference source | |
| CN110703010A (en) | Test circuit | |
| CN108233917B (en) | Level conversion circuit | |
| WO2020098404A1 (en) | Low-power-consumption pmos tube substrate switching circuit with voltage isolation function, and integrated chip | |
| CN110739944B (en) | Low-voltage reset circuit | |
| CN114637367B (en) | Chip internal low-voltage power generation circuit | |
| CN108418573B (en) | Power supply sampling circuit and zero-power-consumption power-on reset circuit comprising same | |
| CN113885644B (en) | Substrate switching circuit for preventing LDO backflow | |
| CN110798187B (en) | Power-on reset circuit | |
| CN108768362B (en) | Pure enhancement type MOS tube static power consumption-free power-on reset circuit | |
| JP5817306B2 (en) | Power supply voltage detection circuit | |
| CN212935871U (en) | Low-power consumption low temperature floats pre-reset circuit | |
| CN111313879B (en) | Time delay circuit | |
| CN216216815U (en) | Time delay circuit | |
| CN219611748U (en) | High-voltage floating gate driving circuit and driving chip thereof | |
| CN113821068B (en) | Multi-power-supply system management circuit and method in chip | |
| US20230091800A1 (en) | Bootstrapped switch | |
| CN108964645B (en) | Delay circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |