CN110739292A - 3D packaging structure and manufacturing method thereof - Google Patents

3D packaging structure and manufacturing method thereof Download PDF

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Publication number
CN110739292A
CN110739292A CN201910830776.9A CN201910830776A CN110739292A CN 110739292 A CN110739292 A CN 110739292A CN 201910830776 A CN201910830776 A CN 201910830776A CN 110739292 A CN110739292 A CN 110739292A
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CN
China
Prior art keywords
layer
electrical contact
contact pads
redistribution layer
insulating isolation
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CN201910830776.9A
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Chinese (zh)
Inventor
李恒甫
曹立强
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Shanghai Xianfang Semiconductor Co Ltd
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Shanghai Xianfang Semiconductor Co Ltd
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Priority to CN201910830776.9A priority Critical patent/CN110739292A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention discloses 3D packaging structures and a manufacturing method thereof, wherein each 3D packaging structure comprises an electric interconnection structure, an insulating isolation layer, a chip, an insulating plastic packaging layer and a second chip, wherein the electric interconnection structure comprises a redistribution layer, a plurality of conductive through holes, a second redistribution layer, a plurality of electrical contact pads and second electrical contact pads which are sequentially stacked from bottom to top and are electrically connected, the insulating isolation layer is positioned on the electric interconnection structure, a plurality of conformal conductive structures are arranged in the insulating isolation layer, at least parts of the conformal conductive structures are positioned on the upper surface of the insulating isolation layer, at least parts of the conformal conductive structures are electrically connected with electrical contact pads, the second chip is arranged in the insulating isolation layer and is electrically connected with the second electrical contact pads, the insulating plastic packaging layer is positioned on the insulating isolation layer, a plurality of third electrical contact pads are arranged in the insulating plastic packaging layer and are electrically connected with the conformal conductive structures positioned on the upper surface of the insulating isolation layer, and the second chip is arranged in the.

Description

3D packaging structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to 3D packaging structures and a manufacturing method thereof.
Background
With the rapid development of integrated circuit technology, the number of chips per unit area of a wafer is increasing, the feature size of the chip is gradually miniaturized to meet the requirement of moore's law, and although the feature size of the chip is reduced, the number of electronic components in the chip is increasing due to the continuous improvement of the integration density of the electronic components (including resistors, capacitors, diodes, transistors, etc.) in the chip, and the chip needs to package more and more output terminals I/O in a smaller area, thereby making the packaging of the chip more difficult. Therefore, there is a strong need in the packaging field for packaging technology with compact package size and higher I/O number of output terminals.
Disclosure of Invention
Therefore, the invention provides types of 3D packaging structures and a manufacturing method thereof, and aims to solve the problem that a packaging technology with compact packaging size and more output terminal I/O (input/output) quantity is urgently needed in the field of packaging.
According to , the embodiment of the invention provides a kind of 3D packaging structure, which includes an electrical interconnection structure including a redistribution layer, a plurality of conductive vias, a second redistribution layer, a plurality of electrical contact pads and a second electrical contact pad, wherein the electrical interconnection structure is stacked from bottom to top and electrically connected, an insulating isolation layer is positioned on the electrical interconnection structure, a plurality of conformal conductive structures are arranged in the insulating isolation layer, at least parts of the conformal conductive structures are positioned on the upper surface of the insulating isolation layer, at least parts of the conformal conductive structures are electrically connected with the electrical contact pads, a chip is arranged in the insulating isolation layer and electrically connected with the second electrical contact pads, an insulating plastic-sealing layer is positioned on the insulating isolation layer, a plurality of third electrical contact pads are arranged in the insulating plastic-sealing layer and electrically connected with the conformal conductive structures positioned on the upper surface of the insulating isolation layer, and a second chip is arranged in the insulating plastic-sealing layer and electrically connected with the third electrical contact pads.
Optionally, the 3D package structure further includes an th encapsulant layer, wherein the th redistribution layer and the plurality of conductive vias are disposed in the th encapsulant layer, upper surfaces of the plurality of conductive vias are flush with an upper surface of the th encapsulant layer, and a lower surface of the th redistribution layer is flush with a lower surface of the th encapsulant layer, and wherein the second encapsulant layer, the second redistribution layer, the plurality of th electrical contact pads and the second electrical contact pads are disposed in the second encapsulant layer, and upper surfaces of the th electrical contact pads and the second electrical contact pads are flush with an upper surface of the second encapsulant layer.
Optionally, the 3D package structure further includes a plurality of solder balls disposed on a lower surface of the redistribution layer and electrically connected to the redistribution layer.
Optionally, the insulating isolation layer is made of phenolic resin or epoxy resin.
Optionally, the insulating plastic layer is made of phenolic resin or epoxy resin.
Optionally, the material of the redistribution layer, the second redistribution layer, the conductive via, the electrical contact pad, the second electrical contact pad, and the third electrical contact pad is any of copper, titanium, tungsten, aluminum, nickel, and tin.
According to a second aspect, the present invention provides a method for manufacturing types of 3D package structures, including forming an electrical interconnection structure over a carrier, wherein the electrical interconnection structure includes a redistribution layer, a plurality of conductive vias, a second redistribution layer, and a plurality of 0 electrical contact pads and second electrical contact pads, which are stacked and electrically connected from bottom to top, placing a 1 th chip on at least second electrical contact pads, forming an insulating isolation layer over the electrical interconnection structure, the insulating isolation layer surrounding a th chip, patterning the insulating isolation layer to form a plurality of vias penetrating the insulating isolation layer, filling the plurality of vias to form a plurality of conformal conductive structures, wherein at least portions of the conformal conductive structures are located on an upper surface of the insulating isolation layer, and at least portions of the conformal conductive structures are electrically connected to the electrical contact pads, placing a plurality of third electrical contact pads on an upper surface of the conformal conductive structures located on the insulating isolation layer, placing a second chip on at least third electrical contact pads, and forming an insulating isolation layer over the insulating isolation layer, the insulating plastic encapsulation layer surrounding the second electrical contact pads and the second electrical contact pads.
Optionally, forming an electrical interconnect structure over a carrier includes forming a th redistribution layer over the carrier, forming a th sealing material layer over the carrier, the th sealing material layer surrounding the th redistribution layer, patterning a th sealing material layer to form a plurality of second vias exposing at least a portion of an upper surface of the th redistribution layer, filling the plurality of second vias to form a plurality of conductive vias, forming a second redistribution layer over the plurality of conductive vias, placing a plurality of th electrical contact pads and a plurality of second electrical contact pads over the second redistribution layer, forming a second sealing material layer over the th sealing material layer, the second sealing material layer surrounding the second redistribution layer, the plurality of th electrical contact pads and the second electrical contact pads, wherein upper surfaces of the plurality of th electrical contact pads and the second electrical contact pads are flush with an upper surface of the second sealing material layer.
Optionally, the method for fabricating the 3D package structure further includes removing the carrier to expose a lower surface of the redistribution layer, and disposing a plurality of solder balls on the lower surface of the redistribution layer.
Optionally, filling the th through holes respectively to form a plurality of conformal conductive structures comprises forming the conformal conductive structures at th through holes respectively through metal sputtering, electroplating and corrosion processes.
The embodiment of the invention has the following beneficial effects:
according to the 3D packaging structure provided by the embodiment of the invention, the th redistribution layer, the second redistribution layer, the th chip and the second chip which are electrically connected are sequentially arranged from bottom to top, so that 3D packaging interconnection of multiple chips is realized, more I/O (input/output) numbers of output terminals can be provided in a smaller area by arranging the electrically connected multiple redistribution layers, the size of the packaging structure is compact, and the packaging structure can be connected with multiple terminals outside the area of the characteristic size of the chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 shows a schematic diagram of a 3D package structure according to an embodiment of the invention;
FIG. 2 is a schematic diagram of another 3D package structure according to an embodiment of the invention;
FIG. 3 is a schematic diagram of another 3D package structure according to an embodiment of the invention;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a 3D package structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a 3D package structure after forming an electrical interconnect structure according to an embodiment of the invention;
fig. 6 is a schematic diagram of a 3D package structure after forming an insulating isolation layer according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a 3D package structure after forming a plurality of conformal conductive structures according to an embodiment of the invention;
fig. 8 is a schematic diagram of a 3D package structure after forming an insulating molding layer according to an embodiment of the invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete description of the technical solutions of the embodiments of the present invention will be given below with reference to the accompanying drawings of the embodiments of the present invention, and it is obvious that the described embodiments are partial embodiments of of the present invention, rather than all embodiments.
Also, for ease of description, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe the relationship of elements or components to another (or another ) elements or components as illustrated.
As shown in FIG. 1, the -type 3D package structure includes an electrical interconnection structure 100 including a redistribution layer 111, a plurality of conductive vias 112, a second redistribution layer 113, a plurality of -th electrical contact pads 120 and a second electrical contact pad 130, which are stacked and electrically connected from bottom to top, an insulating isolation layer 200 on the electrical interconnection structure 100, wherein a plurality of conformal conductive structures 221 are disposed in the insulating isolation layer 200, at least portions of the conformal conductive structures 221 are disposed on an upper surface of the insulating isolation layer 200, at least another portions of the conformal conductive structures 221 are electrically connected to the -th electrical contact pad 120, a chip 210 disposed in the insulating isolation layer 200 and electrically connected to the second electrical contact pad 130, an insulating molding layer 400 on the insulating isolation layer 200, wherein a plurality of third electrical contact pads 310 are disposed in the insulating molding layer 400, and the plurality of third electrical contact pads 310 are electrically connected to the conformal conductive structures 221 disposed on the upper surface of the insulating isolation layer 200, and a second chip 300 disposed in the insulating molding layer 400 and electrically connected to the third electrical contact pads 221.
In an embodiment of the present invention, the redistribution layer 111 and the 113 redistribution layer respectively include conductive components, such as layers or multiple layers of conductive wires, which may be made of suitable conductive materials (e.g., copper, titanium, tungsten, aluminum, etc.), the plurality of conductive vias 112 may be formed by laying a material such as silicon oxide, PBO, or other photosensitive materials on the redistribution layer 111, and performing photolithography, electroplating, and etching processes, or may be directly obtained using formed conductive vias, and the material of the conductive vias 112 may be copper, titanium, tungsten, aluminum, etc., the insulating isolation layer 200 may be a plastic molding material with photolithography capability, such as phenolic resin, epoxy resin, etc., or other organic or inorganic materials, the insulating plastic molding layer 400 may be a plastic molding material with photolithography capability, such as phenolic resin, epoxy resin, etc., or other organic or inorganic materials, and the insulating plastic molding layer 400 may be formed by grinding, chemical etching, leveling, UV-irradiating, etc. to achieve molding and reduce the height to a suitable position.
It should be noted that, the embodiment of the present invention is only described by taking an example that the 3D package structure includes two layers of redistribution structures and two chips, and in other embodiments, the 3D package structure may not be limited to only the number of layers of redistribution structures and the number of chips provided by the embodiment of the present invention.
According to the 3D packaging structure provided by the embodiment of the invention, the th redistribution layer, the second redistribution layer, the th chip and the second chip which are electrically connected are sequentially arranged from bottom to top, so that 3D packaging interconnection of multiple chips is realized, more I/O (input/output) numbers of output terminals can be provided in a smaller area by arranging the electrically connected multiple redistribution layers, the size of the packaging structure is compact, and the packaging structure can be connected with multiple terminals outside the area of the characteristic size of the chip.
In an alternative embodiment, as shown in fig. 2, the 3D package structure further includes a th sealing material layer 114, a th redistribution layer 111 and a plurality of conductive vias 112 disposed in the th sealing material layer 114, the upper surfaces of the plurality of conductive vias 112 being flush with the upper surface of the th sealing material layer 114, the lower surface of the th redistribution layer 111 being flush with the lower surface of the th sealing material layer 114, such that the upper surface of the th sealing material layer 114 has a th opening correspondingly exposing the upper surfaces of the plurality of conductive vias 112, the lower surface of the th sealing material layer 114 has a plurality of second openings correspondingly exposing the lower surface of the th redistribution layer 111, a second sealing material layer 115, a second redistribution layer 113, a plurality of th electrical contact pads 120 and a second electrical contact pad 130 disposed in the second sealing material layer 115, the upper surfaces of the th electrical contact pad 120 and the second electrical contact pad 130 being flush with the upper surface of the second sealing material layer 115, such that the upper surface of the second sealing material layer 115 has a corresponding plurality of second electrical contact pad 120 and a second electrical contact pad 130 being flush with the upper surface of the second sealing material layer 115, such as a salicide, a salicide (which may be formed by a spin-on a doped silicon oxide, a polyimide, a silicon oxide, such as a doped silicon oxide (pbga-doped silicon oxide, a pbga-based sealing material layer) (such as a pbga-doped silicon oxide) or a CVD (such as a doped silicon oxide) deposited, a doped silicon oxide, a pbga-doped silicon oxide, a doped silicon oxide (e) and a doped silicon oxide (e.g) deposited in a.
In an alternative embodiment, as shown in fig. 3, the 3D package structure further includes a plurality of solder balls 140 disposed on a lower surface of the redistribution layer 111 and electrically connected to the redistribution layer 111, in an embodiment of the present invention, the plurality of solder balls 140 are disposed on a lower surface of the redistribution layer 111 to electrically communicate the redistribution layer 111 with a Printed Circuit Board (PCB) (not shown).
In an alternative embodiment, the insulating isolation layer 200 is made of phenolic resin or epoxy resin. In the embodiment of the present invention, the insulating isolation layer 200 is formed by a phenolic resin or an epoxy resin, and the insulating isolation layer 200 can be formed by photolithography, so as to form a plurality of conformal conductive structures 221 in the insulating isolation layer 200.
In an alternative embodiment, the insulating molding layer 400 is made of phenolic resin or epoxy resin. In the embodiment of the present invention, the insulating isolation layer 400 may be formed by photolithography by providing phenolic resin or epoxy resin as a constituent material of the insulating isolation layer 400.
In an alternative embodiment, the materials of the redistribution layer 111, the second redistribution layer 113, the conductive via 112, the electrical contact pad 120, the second electrical contact pad 130, and the third electrical contact pad 310 may be of copper, titanium, tungsten, aluminum, nickel, and tin, respectively.
The embodiment of the present invention further provides a manufacturing method of types of 3D package structures, as shown in fig. 4, including:
s101, forming an electrical interconnection structure above a carrier, wherein the electrical interconnection structure comprises an th redistribution layer, a plurality of conductive through holes, a second redistribution layer, a plurality of th electrical contact pads and a second electrical contact pad, which are sequentially stacked from bottom to top and are electrically connected.
Fig. 5 is a schematic diagram of an embodiment of the invention after forming an electrical interconnection structure, and fig. 5 illustrates the carrier 110, the th redistribution layer 111, the 4 th conductive vias, the second redistribution layer, and the 3 th and 2 second electrical contact pads by way of example only, but is not limited to the electrical interconnection structure of the embodiment of the invention.
S102, placing the th chip on at least second electric contact pads.
S103, forming an insulating isolation layer above the electric interconnection structure, wherein the insulating isolation layer surrounds the th chip.
Illustratively, fig. 6 is a schematic diagram of a 3D package structure after forming an insulating isolation layer according to an embodiment of the present invention, in the embodiment of the present invention, the thickness of the insulating isolation layer 200 is greater than that of the th chip 210.
S104. the insulating isolation layer is patterned to form a plurality of th through holes penetrating the insulating isolation layer, specifically, the number of the th through holes can be set to be 2, but the number of the th through holes is not limited, in other embodiments, the number of the th through holes can be other numbers, the plurality of th through holes can be formed by using a laser drilling process, a photoetching and/or etching process and the like.
And S105, respectively filling a plurality of th through holes to form a plurality of conformal conductive structures, wherein at least parts of the conformal conductive structures are positioned on the upper surface of the insulating isolation layer, and at least another parts of the conformal conductive structures are electrically connected with the th electric contact pad.
In an exemplary embodiment of the invention, a plurality of conductive structures of the 3D package are formed by filling a plurality of th through holes respectively, and a conformal conductive structure can be formed at each th through hole respectively by metal sputtering, electroplating and etching processes.
S106, a plurality of third electrical contact pads are placed on the upper surface of the conformal conductive structure on the upper surface of the insulating isolation layer.
S107. place the second chip on at least third electrical contact pads.
And S108, forming an insulating plastic packaging layer above the insulating isolation layer, wherein the insulating plastic packaging layer surrounds the third electric contact pad and the second chip.
Exemplarily, fig. 8 is a schematic diagram of a 3D package structure after forming an insulating molding layer according to an embodiment of the present invention. The insulating molding layer 400 can be planarized and lowered to a proper height by grinding, chemical etching, UV irradiation, etc.
According to the manufacturing method of the 3D packaging structure provided by the embodiment of the invention, the th redistribution layer, the second redistribution layer, the th chip and the second chip which are electrically connected are sequentially arranged from bottom to top, so that 3D packaging interconnection of multiple chips is realized, more I/O (input/output) quantity of output terminals can be provided in a smaller area by arranging the electrically connected multiple redistribution layers, the size of the packaging structure is compact, and the packaging structure can be connected with multiple terminals outside the area of the characteristic size of the chip.
In an alternative embodiment, step S101, forming an electrical interconnect structure over a carrier includes forming a redistribution layer over the carrier, forming a second a sealing material layer over the carrier, the second 0 a sealing material layer surrounding the second 1 redistribution layer, patterning the second sealing material layer to form a plurality of second vias exposing at least a portion of an upper surface of the second redistribution layer, filling the plurality of second vias to form a plurality of conductive vias, forming a second redistribution layer over the plurality of conductive vias, placing a plurality of pads and a plurality of second electrical contact pads over the second redistribution layer such that the second redistribution layer is electrically connected to the plurality of electrical contact pads and the second electrical contact pads, forming a second sealing material layer over the second sealing material layer, the second sealing material layer surrounding the second redistribution layer, the plurality of electrical contact pads and the second electrical contact pads, wherein upper surfaces of the plurality of second electrical contact pads and the second electrical contact pads are flush with an upper surface of the second sealing material layer such that the upper surface of the second sealing material layer has a corresponding plurality of exposed second electrical contact pads formed by a sputtering process, forming a plurality of conductive vias, and etching the plurality of conductive vias.
In yet another alternative embodiment, the method of fabricating the 3D package structure further includes removing the carrier to expose a lower surface of the redistribution layer, disposing a plurality of solder balls on the lower surface of the redistribution layer, in an embodiment of the present invention, an adhesive layer (not shown) may be deposited or laminated over the carrier before forming the electrical interconnection structure, the adhesive layer may be photosensitive and may be easily released from the carrier by, for example, irradiating Ultraviolet (UV) light to the carrier in a subsequent carrier debonding process, thereby achieving a carrier removal purpose, disposing a plurality of solder balls on a lower surface of the redistribution layer for achieving electrical communication between the redistribution layer and a Printed Circuit Board (PCB) (not shown).
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims (10)

1, kinds of 3D packaging structure, its characterized in that includes:
the electrical interconnection structure comprises an redistribution layer, a plurality of conductive through holes, a second redistribution layer, a plurality of electrical contact pads and a second electrical contact pad which are sequentially stacked from bottom to top and electrically connected;
an insulating isolation layer on the electrical interconnect structure, the insulating isolation layer having a plurality of conformal conductive structures disposed therein, at least portions of the conformal conductive structures being on an upper surface of the insulating isolation layer, at least another portions of the conformal conductive structures being in electrical connection with the electrical contact pad;
an chip disposed in the insulating isolation layer and electrically connected to the second electrical contact pad;
the insulating plastic packaging layer is positioned on the insulating isolation layer, a plurality of third electric contact pads are arranged in the insulating plastic packaging layer, and the third electric contact pads are electrically connected with conformal conductive structures positioned on the upper surface of the insulating isolation layer;
and the second chip is arranged in the insulating plastic packaging layer and is electrically connected with the third electric contact pad.
2. The 3D package structure of claim 1, further comprising:
an th encapsulant layer, the th redistribution layer and a plurality of conductive vias disposed in the th encapsulant layer, an upper surface of the plurality of conductive vias being flush with an upper surface of the th encapsulant layer, a lower surface of the th redistribution layer being flush with a lower surface of the th encapsulant layer;
a second layer of encapsulant material, the second redistribution layer, a plurality of th electrical contact pads and second electrical contact pads disposed in the second layer of encapsulant material, upper surfaces of the th and second electrical contact pads being flush with an upper surface of the second layer of encapsulant material.
3. The 3D package structure of claim 1, further comprising:
a plurality of solder balls disposed on a lower surface of the redistribution layer and electrically connected to the redistribution layer.
4. The 3D package structure of claim 1,
the insulating isolation layer is made of phenolic resin or epoxy resin.
5. The 3D package structure of claim 1,
the insulating plastic packaging layer is made of phenolic resin or epoxy resin.
6. The 3D package structure of claim 1,
the redistribution layer, the second redistribution layer, the conductive via, the electrical contact pad, the second electrical contact pad, and the third electrical contact pad are made of any materials selected from copper, titanium, tungsten, aluminum, nickel, and tin.
7, kinds of 3D packaging structure's preparation method, characterized by, including:
forming an electrical interconnect structure over the carrier, wherein the electrical interconnect structure includes an th redistribution layer, a plurality of conductive vias, a second redistribution layer, and a plurality of th and second electrical contact pads, stacked and electrically connected in sequence from bottom to top;
placing an th chip on at least of the second electrical contact pads;
forming an insulating isolation layer over the electrical interconnect structure, the insulating isolation layer surrounding the th chip;
patterning the insulating isolation layer to form a plurality of th through holes penetrating through the insulating isolation layer;
filling a plurality of th through holes respectively to form a plurality of conformal conductive structures, wherein, at least parts of the conformal conductive structures are positioned on the upper surface of the insulation isolation layer, and at least another parts of the conformal conductive structures are electrically connected with the th electric contact pad;
placing a plurality of third electrical contact pads on an upper surface of a conformal conductive structure located on an upper surface of the insulating isolation layer;
placing a second chip on at least of said third electrical contact pads;
forming an insulating molding compound over the insulating isolation layer, the insulating molding compound surrounding the third electrical contact pad and the second chip.
8. The method of claim 7, wherein forming the electrical interconnect structure over the carrier comprises:
forming an redistribution layer over the carrier;
forming a fourth layer of sealing material over the carrier, the fourth layer of sealing material surrounding the redistribution layer;
patterning the sealant layer to form a plurality of second vias exposing at least a portion of an upper surface of the redistribution layer;
filling a plurality of second through holes to form a plurality of conductive through holes respectively;
forming a second redistribution layer over the plurality of conductive vias;
placing th electrical contact pads and second electrical contact pads on the second redistribution layer;
forming a second layer of sealing material over an th layer of sealing material, the second layer of sealing material surrounding the second redistribution layer, the plurality of th and second electrical contact pads, wherein upper surfaces of the plurality of th and second electrical contact pads are flush with an upper surface of the second layer of sealing material.
9. The method for manufacturing a 3D package structure according to claim 7, further comprising:
removing the carrier to expose a lower surface of the redistribution layer;
a plurality of solder balls are disposed on a lower surface of the redistribution layer.
10. The method for manufacturing the 3D packaging structure according to claim 7, wherein the respectively filling the th through holes to form a plurality of conformal conductive structures comprises:
and respectively forming the conformal conductive structure at each th through hole by metal sputtering, electroplating and etching processes.
CN201910830776.9A 2019-09-02 2019-09-02 3D packaging structure and manufacturing method thereof Pending CN110739292A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110739291A (en) * 2018-07-20 2020-01-31 联咏科技股份有限公司 Chip on film package

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104078451A (en) * 2013-03-29 2014-10-01 英特尔公司 Method, Apparatus and Material for Radio Frequency Passives and Antennas
CN204464262U (en) * 2015-03-27 2015-07-08 江阴长电先进封装有限公司 A kind of 3-D stacks encapsulating structure
CN104851816A (en) * 2015-04-13 2015-08-19 华进半导体封装先导技术研发中心有限公司 Method for packaging multiple chips in high density
CN105895538A (en) * 2016-04-28 2016-08-24 合肥祖安投资合伙企业(有限合伙) Manufacture method for chip packaging structure and chip packaging structure
CN106571356A (en) * 2015-10-08 2017-04-19 美光科技公司 Package-on-package assembly
CN107195551A (en) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 Fan-out-type laminated packaging structure and preparation method thereof
CN107851615A (en) * 2015-08-21 2018-03-27 苹果公司 Independent 3D is stacked
CN108022871A (en) * 2016-11-03 2018-05-11 美光科技公司 Semiconductor packages and its manufacture method
CN109300863A (en) * 2018-09-28 2019-02-01 中国科学院微电子研究所 Semiconductor package and method for packaging semiconductor

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104078451A (en) * 2013-03-29 2014-10-01 英特尔公司 Method, Apparatus and Material for Radio Frequency Passives and Antennas
CN204464262U (en) * 2015-03-27 2015-07-08 江阴长电先进封装有限公司 A kind of 3-D stacks encapsulating structure
CN104851816A (en) * 2015-04-13 2015-08-19 华进半导体封装先导技术研发中心有限公司 Method for packaging multiple chips in high density
CN107851615A (en) * 2015-08-21 2018-03-27 苹果公司 Independent 3D is stacked
CN106571356A (en) * 2015-10-08 2017-04-19 美光科技公司 Package-on-package assembly
CN105895538A (en) * 2016-04-28 2016-08-24 合肥祖安投资合伙企业(有限合伙) Manufacture method for chip packaging structure and chip packaging structure
CN108022871A (en) * 2016-11-03 2018-05-11 美光科技公司 Semiconductor packages and its manufacture method
CN107195551A (en) * 2017-07-05 2017-09-22 中芯长电半导体（江阴）有限公司 Fan-out-type laminated packaging structure and preparation method thereof
CN109300863A (en) * 2018-09-28 2019-02-01 中国科学院微电子研究所 Semiconductor package and method for packaging semiconductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110739291A (en) * 2018-07-20 2020-01-31 联咏科技股份有限公司 Chip on film package
US11322427B2 (en) 2018-07-20 2022-05-03 Novatek Microelectronics Corp. Chip on film package

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