CN110739281A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110739281A
CN110739281A CN201910658593.3A CN201910658593A CN110739281A CN 110739281 A CN110739281 A CN 110739281A CN 201910658593 A CN201910658593 A CN 201910658593A CN 110739281 A CN110739281 A CN 110739281A
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China
Prior art keywords
semiconductor chip
semiconductor
region
heat
thermal
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CN201910658593.3A
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English (en)
Inventor
金贤基
金祥洙
金承焕
吴琼硕
李镕官
李种昊
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110739281A publication Critical patent/CN110739281A/zh
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Abstract

公开了一种半导体封装，包括：封装衬底；封装衬底上的第一半导体芯片，该第一半导体芯片包括第一区域和第二区域；第一区域上的第二半导体芯片；第二区域上的热辐射间隔物；第三半导体芯片，由第二半导体芯片和热辐射间隔物支撑；以及模塑层，覆盖第一半导体芯片至第三半导体芯片和热辐射间隔物。

Description

半导体封装
相关申请的交叉引用
本申请要求于2018年7月20日在韩国知识产权局递交的韩国专利申请No.10-2018-0084510的优先权，其全部内容通过引用合并于此。
技术领域
本发明构思涉及半导体封装，更具体地，涉及包括热辐射间隔物的半导体封装。
背景技术
随着电子工业的快速发展和响应于客户的需求，已经将电子设备制造成尺寸缩小和/或重量轻并且具有更高的容量。已经开发出包括许多半导体芯片的半导体封装。已经开发出包括多个具有各种类型和大小的半导体芯片的半导体封装。
发明内容
本发明构思的一些示例实施例提供了一种能够有效地释放从半导体芯片产生的热量的半导体封装。
根据本发明构思的一些示例实施例，半导体封装可以包括：封装衬底；封装衬底上的第一半导体芯片，包括第一区域和第二区域；第一区域中的第二半导体芯片；第二区域中的热辐射间隔物；第三半导体芯片，由第二半导体芯片和热辐射间隔物支撑；以及模塑层，覆盖第一半导体芯片至第三半导体芯片和热辐射间隔物。
根据本发明构思的一些示例实施例，半导体封装可以包括：封装衬底；封装衬底上的第一半导体芯片，包括第一区域和第二区域；第一半导体芯片上的热辐射间隔物，该热辐射间隔物包括：基底，所述基底包括在第一区域中的第一区段和在第二区域中的第二区段，以及在第二区段上的突起；第一区段上的第二半导体芯片；第三半导体芯片，由第二半导体芯片和突起支撑；以及模塑层，覆盖第一半导体芯片至第三半导体芯片和热辐射间隔物。
根据本发明构思的一些示例实施例，半导体封装可以包括：封装衬底；封装衬底上的第一半导体芯片，包括第一区域和第二区域；一对第二半导体芯片，在第一区域中彼此间隔开；第二区域中的热辐射间隔物；一对第三半导体芯片，在一对第二半导体芯片中的对应一个上；以及模塑层，覆盖第一半导体芯片至第三半导体芯片和热辐射间隔物。每个第三半导体芯片可以包括：第二半导体芯片上的第一区段；以及热辐射间隔物上的第二区段。
附图说明
图1A示出了示出根据本发明构思的一些示例实施例的半导体封装的平面图。
图1B示出了沿图1A的线A-A′截取的横截面图。
图1C示出了沿图1A的线B-B′截取的横截面图。
图2A和图3A示出了示出根据本发明构思的一些示例实施例的制造半导体封装的方法的平面图。
图2B和3B示出了分别沿图2A和3A的线A-A′截取的横截面图。
图2C和3C示出了分别沿图2A和3A的线B-B′截取的横截面图。
图4A示出了示出根据本发明构思的一些示例实施例的半导体封装的平面图。
图4B示出了沿图4A的线A-A′截取的横截面图。
图5示出了示出根据本发明构思的一些示例实施例的半导体封装的平面图。
图6A示出了沿图1A的线A-A′截取的横截面图。
图6B示出了沿图1A的线B-B’截取的横截面图。
具体实施方式
图1A示出了示出根据本发明构思的一些示例实施例的半导体封装的平面图。图1B示出了沿图1A的线A-A′截取的横截面图。图1C示出了沿图1A的线B-B′截取的横截面图。
参考图1A至图1C，可以提供衬底100。封装衬底100可以是具有电路图案的印刷电路板(PCB)。
外部端子105可以设置在封装衬底100的底表面上。外部端子105可以是但不限于焊球、导电凸块、导电间隔物、引脚栅格阵列等。外部端子105可以将封装衬底100电连接到外部电气设备(未示出)。
第一半导体芯片SC1可以设置在封装衬底100上。第一半导体芯片SC1可以包括存储器电路、逻辑电路或其组合。第一半导体芯片SC1可以包括第一区域RG1和第二区域RG2。热源111可以嵌入在第一半导体芯片SC1的第二区域RG2中。热源111可以是中央处理单元(CPU)、存储器接口、通用串行总线(USB)或其他知识产权(IP)块。术语“IP块”可以意指以硬件或软件方式配置构成半导体集成电路所需的功能的块。热源111可以在第一半导体芯片SC1中彼此间隔开地设置，这可以导致热源111之间的电和/或热干扰的最小化或减少。当操作第一半导体芯片SC1时，从第二区域RG2产生的热量可以大于从第一区域RG1产生的热量。
第一半导体芯片SC1和封装衬底100可以通过设置在它们之间的连接端子112彼此电连接。当在平面中查看时，连接端子112可以彼此间隔开。连接端子112可以具有焊料或凸块形状。连接端子112可以包括导电材料。例如，连接端子112可以包括锡(Sn)、铅(Pb)、镍(Ni)、金(Au)、银(Ag)、铜(Cu)和铋(Bi)中的一种或多种。
可以提供底部填充层114以填充第一半导体芯片SC1和封装衬底100之间的间隙。底部填充层114可以通过底部填充工艺形成，在底部填充工艺中，涂覆底部填充浆料，然后固化。底部填充浆料可以是例如不含导电颗粒的环氧基材料。底部填充层114可以围绕连接端子112的表面。
在与所示示例实施例不同的一些示例实施例中，可以使用引线接合将第一半导体芯片SC1电连接到封装衬底100。
一对第二半导体芯片SC2可以设置在第一半导体芯片SC1的第一区域RG1上。第二半导体芯片SC2可以具有沿第一方向D1的第一长度和沿第二方向D2的第二长度。第一长度可以大于第二长度。第一方向D1和第二方向D2可以彼此相交并且可以平行于封装衬底100的顶表面。一对第二半导体芯片SC2可以沿第二方向D2彼此间隔开。
第一粘合层AL1可以设置在第二半导体芯片SC2和第一半导体芯片SC1之间。第二半导体芯片SC2可以通过第一粘合层AL1粘附到第一半导体芯片SC1的顶表面。第一粘合层AL1可以是例如直接粘合膜(DAF)或线上膜(FOW)。例如，第一粘合层AL1可以包括介电材料。第一粘合层AL1可以使第一半导体芯片SC1和第二半导体芯片SC2彼此电绝缘。
热辐射间隔物140可以设置在第一半导体芯片SC1的第二区域RG2上。热辐射间隔物140可以沿第二方向D2延伸。热辐射间隔物140可以与嵌入在第一半导体芯片SC1的第二区域RG2中的热源111竖直重叠。热辐射间隔物140可以引导从第一半导体芯片SC1产生的热量的释放。在一些示例实施例中，热辐射间隔物140可以接收从第一半导体芯片SC1产生的热量。例如，可以将从热源111产生的热量传递给热辐射间隔物140。热辐射间隔物140可以包括导热率高的材料。例如，热辐射间隔物140可以包括铜(Cu)或银(Ag)。热辐射间隔物140可以包括粘附强的材料。例如，热辐射间隔物140可以包括粘合聚合物。又例如，热辐射间隔物140可以包括其中分布有铜(Cu)或银(Ag)颗粒的粘合聚合物。
可以在每个第二半导体芯片SC2上设置第三半导体芯片SC3。第三半导体芯片SC3可以偏移堆叠在第二半导体芯片SC2上。例如，可以在第二半导体芯片SC2上堆叠部分地暴露第二半导体芯片SC2的顶表面的第三半导体芯片SC3。一对第三半导体芯片SC3可以沿第二方向D2彼此间隔开。第三半导体芯片SC3可以具有在与热辐射间隔物140的顶表面的高度基本相同的高度处的顶表面。
第二粘合层AL2可以设置在第三半导体芯片SC3和第二半导体芯片SC2之间。第二粘合层AL2可以包括与第一粘合层AL1的材料基本相同的材料。
第四半导体芯片SC4可以设置在热辐射间隔物140和每个第三半导体芯片SC3上。例如，第四半导体芯片SC4的一部分可以设置在第三半导体芯片SC3上，第四半导体芯片SC4的其他部分可以设置在热辐射间隔物140上。在该配置中，第四半导体芯片SC4可以由第三半导体芯片SC3和热辐射间隔物140支撑。第四半导体芯片SC4可以偏移堆叠在第三半导体芯片SC3上。第四半导体芯片SC4可以跨越热辐射间隔物140。一对第四半导体芯片SC4可以沿第二方向D2彼此间隔开。
第三粘合层AL3可以设置在第四半导体芯片SC4和第三半导体芯片SC3之间以及第四半导体芯片SC4和热辐射间隔物140之间。第三粘合层AL3可以包括与第一粘合层AL1的材料基本相同的材料。第四半导体芯片SC4可以通过第三粘合层AL3粘附到第三半导体芯片SC3和热辐射间隔物140的顶表面。
可以在每个第四半导体芯片SC4上设置第五半导体芯片SC5。第五半导体芯片SC5可以偏移堆叠在第四半导体芯片SC4上。一对第五半导体芯片SC5可以沿第二方向D2彼此间隔开。
第二半导体芯片SC2至第五半导体芯片SC5中的每个半导体芯片可以包括存储器电路、逻辑电路或其组合。第二半导体芯片SC2至第五半导体芯片SC5中的每个半导体芯片可以是与第一半导体芯片SC1不同类型的半导体芯片。例如，第一半导体芯片SC1可以是包括逻辑电路的逻辑芯片，第二半导体芯片SC2至第五半导体芯片SC5中的每个半导体芯片可以是包括多个存储器单元的存储器芯片。在一些示例实施例中，第一半导体芯片SC1可以管理和控制第二半导体芯片SC2至第五半导体芯片SC5的操作，并且从第一半导体芯片SC1产生的热量可以大于从第二半导体芯片SC2至第五半导体芯片SC5中的每个半导体芯片或全部半导体芯片产生的热量。
第四粘合层AL4可以设置在第五半导体芯片SC5和第四半导体芯片SC4之间。第四粘合层AL4可以包括与第一粘合层AL1的材料基本相同的材料。
连接焊盘181可以设置在第一半导体芯片SC1至第五半导体芯片SC5中的每个半导体芯片上。连接焊盘181可以是向第一半导体芯片SC1至第五半导体芯片SC5中的每个半导体芯片输入或从其输出电信号的端子。连接焊盘181可以包括导电材料。例如，连接焊盘181可以包括金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铝(Al)、锡(Sn)、铅(Pb)、铂(Pt)、铋(Bi)、铟(In)及其合金中的一种或多种。
可以设置接合线182以将连接焊盘181彼此连接。接合线182可以将第一半导体芯片SC1至第五半导体芯片SC5彼此电连接。接合线182可以包括导电材料。例如，接合线182可以包括金(Au)、银(Ag)、铜(Cu)、铝(A1)及其合金中的一种或多种。
在与所示实施例不同的一些示例实施例中，可以使用倒装芯片接合来将第一半导体芯片SC1至第五半导体芯片SC5彼此电连接。在一些示例实施例中，代替第一粘合层AL1至第四粘合层AL4，可以在第一半导体芯片SC1至第五半导体芯片SC5之间设置连接端子和底部填充层。
模塑层190可以设置在封装衬底100上。模塑层190可以覆盖第一半导体芯片SC1至第五半导体芯片SC5的横向表面和顶表面。模塑层190还可以覆盖热辐射间隔物140的横向表面和顶表面。例如，模塑层190可以包括环氧模塑料(EMC)。
可以设置热路径图案191以穿透模塑层190。热路径图案191可以设置在热辐射间隔物140上。当在平面中查看时，热路径图案191可以彼此间隔开。每个热路径图案191可以设置在热辐射间隔物140的边缘上或者设置在一对第三半导体芯片SC3之间。热路径图案191可以沿竖直方向延伸，例如，沿第三方向D3延伸。每个热路径图案191可以具有大于模塑层190的导热率的导热率。热路径图案191可以包括导电材料和/或粘合聚合物。例如，导电材料可以包括铝(Al)、锡(Sn)、铜(Cu)、银(Ag)、氧化铝(Al2O3)、氧化锌(ZnO)、碳化硅(SiC)、氮化铝(AlN)、氮化硼(BN)、金刚石中的一种或多种，及其组合。从第一半导体芯片SC1产生的热量可以通过热辐射间隔物140传递到热路径图案191。
热辐射构件192可以设置在模塑层190上。热辐射构件192可以包括导热率高的材料。例如，热辐射构件192可以包括热熔渣、散热器和石墨片中的一种。热辐射构件192可以接收并向外释放从第一半导体芯片SC1产生的热量。
传热层193可以***在模塑层190和热辐射构件192之间。传热层193可以连接到热路径图案191。传热层193可以在模塑层190和热辐射构件192之间延伸。传热层193可以包括与热路径图案191的材料相同的材料。例如，传热层193可以包括导电材料和/或粘合聚合物。热辐射构件192可以通过传热层193粘附到模塑层190。从第一半导体芯片SC1产生的热量可以通过传热层193传递到热辐射构件192。与既不设置传热层193也不设置热辐射构件192的情况相比，根据本发明构思的半导体封装可以提高第一半导体芯片SC1的操作可靠性。
图2A和图3A示出了示出根据本发明构思的一些示例实施例的制造半导体封装的方法的平面图。图2B和3B示出了分别沿图2A和3A的线A-A′截取的横截面图。图2C和3C示出了分别沿图2A和3A的线B-B′截取的横截面图。
为了简化描述，与参考图1A至图1C所讨论的组件基本相同的组件被分配了相同的附图标记，并省略其重复说明。
参考图2A至图2C，可以制备封装衬底100。可以在封装衬底100的底表面上形成外部端子105。可以在封装衬底100上设置第一半导体芯片SC1。可以形成连接端子112以将第一半导体芯片SC1和封装衬底100彼此电连接。可以形成底部填充层114以填充第一半导体芯片SC1和封装衬底100之间的间隙。底部填充层114可以通过底部填充工艺形成，在底部填充工艺中，涂覆底部填充浆料，然后固化。在与所示示例实施例不同的一些示例实施例中，可以使用引线接合将第一半导体芯片SC1电连接到封装衬底100。
可以在第一半导体芯片SC1的第一区域RG1上设置第二半导体芯片SC2。每个第二半导体芯片SC2可以通过第一粘合层AL1粘附到第一半导体芯片SC1的顶表面。
可以在每个第二半导体芯片SC2上设置第三半导体芯片SC3。第三半导体芯片SC3可以偏移堆叠在第二半导体芯片SC2上。每个第三半导体芯片SC3可以通过第二粘合层AL2粘附到第二半导体芯片SC2的顶表面。
可以在第一半导体芯片SC1的第二区域RG2上形成热辐射间隔物140。例如，可以通过在第一半导体芯片SC1的第二区域RG2上涂覆和固化包括导热率高的材料的糊剂来形成热辐射间隔物140。又例如，可以通过在第一半导体芯片SC1的第二区域RG2上设置包括导热率高的材料的膜来形成热辐射间隔物140。可以在设置第二半导体芯片SC2和第三半导体芯片SC3之前或之后形成热辐射间隔物140。热源111可以嵌入在第一半导体芯片SC1的第二区域RG2中。热辐射间隔物140可以与热源111竖直重叠。
参考图3A至图3C，可以在热辐射间隔物140和第三半导体芯片SC3中的每个半导体芯片上设置第四半导体芯片SC4。例如，第四半导体芯片SC4可以由第三半导体芯片SC3和热辐射间隔物140支撑。第四半导体芯片SC4可以偏移堆叠在第三半导体芯片SC3上。第四半导体芯片SC4可以通过第三粘合层AL3粘附到第三半导体芯片SC3和热辐射间隔物140的顶表面。
可以在每个第四半导体芯片SC4上设置第五半导体芯片SC5。第五半导体芯片SC5可以偏移堆叠在第四半导体芯片SC4上。每个第五半导体芯片SC5可以通过第四粘合层AL4粘附到第四半导体芯片SC4的顶表面。
可以形成接合线182以将设置在第一半导体芯片SC1至第五半导体芯片SC5中的每个半导体芯片上的连接焊盘181彼此电连接。接合线182可以将第一半导体芯片SC1至第五半导体芯片SC5彼此电连接。
在与所示实施例不同的一些示例实施例中，可以使用倒装芯片接合来将第一半导体芯片SC1至第五半导体芯片SC5彼此电连接。在一些示例实施例中，代替第一粘合层AL1至第四粘合层AL4，可以在第一半导体芯片SC1至第五半导体芯片SC5之间形成连接端子和底部填充层。
可以在封装衬底100上形成模塑层190。模塑层190可以覆盖第一半导体芯片SC1至第五半导体芯片SC5的横向表面和顶表面。模塑层190还可以覆盖热辐射间隔物140的横向表面和顶表面。
返回参考图1A至图1C，可以形成热路径图案191以穿透模塑层190。热路径图案191的形成可以包括去除模塑层190的一部分以形成开口以暴露热辐射间隔物140，以及用导电材料和/或粘合聚合物填充开口。开口的形成可以包括执行激光钻孔以去除模塑层190的一部分。因为开口形成在热辐射间隔物140上，所以可以减少或防止第一半导体芯片SC1被激光钻孔损坏。
可以在模塑层190上形成传热层193。传热层193的形成可以包括在模塑层190上涂覆导电材料和/或粘合聚合物。传热层193可以连接到每个热路径图案191。
可以在传热层193上形成热辐射构件192。传热层193可以将热辐射构件192附接到模塑层190。当热辐射构件192包括石墨片时，传热层193和热辐射构件192可以同时附接到模塑层190。
图4A示出了示出根据本发明构思的一些示例实施例的半导体封装的平面图。图4B示出了沿图4A的线A-A′截取的横截面图。
为了简化描述，与参考图1A至图1C所讨论的组件基本相同的组件被分配了相同的附图标记，并省略其重复说明。
参考图4A和图4B，热辐射间隔物140可以包括基底141和突起142。基底141可以包括第一区段141a和第二区段141b。第一区段141a可以设置在第一半导体芯片SC1的第一区域RG1上。第二区段141b可以设置在第一半导体芯片SC1的第二区域RG2上。突起142可以设置在第二区段141b上。突起142可以在基底141的第二区段141b上沿第三方向D3突出。例如，突起142可以具有在比基底141的顶表面的高度更高的高度处的顶表面。突起142可以沿第二方向D2延伸。突起142可以与嵌入在第一半导体芯片SC1的第二区域RG2中的热源111竖直重叠。
第二半导体芯片SC2可以设置在热辐射间隔物140的基底141的第一区段141a上。第二半导体芯片SC2可以通过热辐射间隔物140的粘附来附接到第一区段141a。
第三半导体芯片SC3可以设置在每个第二半导体芯片SC2上。第三半导体芯片SC3可以具有在与热辐射间隔物140的突起142的顶表面的高度基本相同的高度处的顶表面。
第四半导体芯片SC4可以设置在热辐射间隔物140的突起142和每个第三半导体芯片SC3上。例如，第四半导体芯片SC4的一部分可以设置在第三半导体芯片SC3上，第四半导体芯片SC4的其他部分可以设置在热辐射间隔物140的突起142上。第四半导体芯片SC4可以通过第二粘合层AL2粘附到第三半导体芯片SC3的顶表面和热辐射间隔物140的突起142的顶表面。
图5示出了示出根据本发明构思的一些示例实施例的半导体封装的平面图。
为了简化描述，与参考图1A至图1C所讨论的组件基本相同的组件被分配了相同的附图标记，并省略其重复说明。
参考图5，一对热辐射间隔物140可以设置在第一半导体芯片SC1的第二区域RG2上。热辐射间隔物140可以沿第二方向D2彼此间隔开。热辐射间隔物140可以单独地支撑第四半导体芯片SC4。例如，一个热辐射间隔物140可以支撑一个第四半导体芯片SC4。每个热辐射间隔物140可以与嵌入第一半导体芯片SCl的第二区域RG2中的热源111竖直重叠。
图6A示出了沿图1A的线A-A′截取的横截面图。图6B示出了沿图1A的线B-B’截取的横截面图。
为了简化描述，与参考图1A至图1C所讨论的组件基本相同的组件被分配了相同的附图标记，并省略其重复说明。
参考图1A、图6A和图6B，第三粘合层AL3可以选择性地设置在第四半导体芯片SC4和第三半导体芯片SC3之间，而不设置在第四半导体芯片SC4和热辐射间隔物140之间。在一些示例实施例中，热辐射间隔物140可以具有在与第三粘合层AL3的顶表面的高度基本相同的高度处的顶表面，并且第四半导体芯片SC4可以直接接触热辐射间隔物140。可以通过热辐射间隔物140的粘附来实现第四半导体芯片SC4的附接。
根据本发明构思的示例实施例，半导体封装可以包括半导体芯片之间的热辐射间隔物，因此可以有效地释放从半导体芯片产生的热量。
尽管已经结合附图中的本发明构思的示例实施例描述了本发明构思的示例实施例，但是本领域技术人员应理解，可以在不脱离本发明构思的技术精神和基本特征的情况下进行各种改变和修改。对于本领域技术人员来说显而易见的是，在不脱离本发明构思的范围和精神的情况下可以对其进行各种替换、修改和改变。

Claims (20)

1.一种半导体封装，包括：
封装衬底；
所述封装衬底上的第一半导体芯片，包括第一区域和第二区域；
所述第一区域中的第二半导体芯片；
所述第二区域中的热辐射间隔物；
第三半导体芯片，由所述第二半导体芯片和所述热辐射间隔物支撑；以及
模塑层，覆盖所述第一半导体芯片至所述第三半导体芯片和所述热辐射间隔物。
2.根据权利要求1所述的半导体封装，其中，所述第一半导体芯片包括热源，所述热源在所述第二区域中。
3.根据权利要求2所述的半导体封装，其中，所述热源与所述热辐射间隔物竖直重叠。
4.根据权利要求1所述的半导体封装，还包括：
热路径图案，穿透所述模塑层并连接到所述热辐射间隔物；以及
热辐射构件，在所述模塑层上。
5.根据权利要求4所述的半导体封装，还包括：传热层，所述传热层在所述模塑层和所述热辐射构件之间，
其中，所述传热层将所述热路径图案连接到所述热辐射构件。
6.根据权利要求1所述的半导体封装，还包括：粘合层，所述粘合层在所述第三半导体芯片和所述第二半导体芯片之间，且在所述第三半导体芯片和所述热辐射间隔物之间。
7.根据权利要求1所述的半导体封装，还包括：粘合层，所述粘合层在所述第三半导体芯片和所述第二半导体芯片之间，
其中，所述第三半导体芯片直接接触所述热辐射间隔物。
8.一种半导体封装，包括：
封装衬底；
所述封装衬底上的第一半导体芯片，包括第一区域和第二区域；
所述第一半导体芯片上的热辐射间隔物，所述热辐射间隔物包括：
基底，包括所述第一区域中的第一区段和所述第二区域中的第二区段，以及
所述第二区段上的突起；
所述第一区段上的第二半导体芯片；
第三半导体芯片，由所述第二半导体芯片和所述突起支撑；以及
模塑层，覆盖所述第一半导体芯片至所述第三半导体芯片和所述热辐射间隔物。
9.根据权利要求8所述的半导体封装，其中，所述第一半导体芯片包括热源，所述热源在所述第二区域中。
10.根据权利要求9所述的半导体封装，其中，所述热源与所述突起竖直重叠。
11.根据权利要求8所述的半导体封装，其中，所述突起的顶表面的高度与所述第二半导体芯片的顶表面的高度基本相同。
12.根据权利要求8所述的半导体封装，其中，所述突起和所述第三半导体芯片彼此直接接触。
13.根据权利要求8所述的半导体封装，还包括：
热路径图案，穿透所述模塑层并连接到所述突起；以及
热辐射构件，在所述模塑层上，
其中，所述热路径图案的导热率大于所述模塑层的导热率。
14.根据权利要求13所述的半导体封装，还包括：传热层，所述传热层在所述模塑层和所述热辐射构件之间，
其中，所述传热层包括与所述热路径图案的材料相同的材料。
15.一种半导体封装，包括：
封装衬底；
所述封装衬底上的第一半导体芯片，包括第一区域和第二区域；
一对第二半导体芯片，在所述第一区域中彼此间隔开；
所述第二区域中的热辐射间隔物；
一对第三半导体芯片，在所述一对第二半导体芯片上；以及
模塑层，覆盖所述第一半导体芯片至所述第三半导体芯片和所述热辐射间隔物，
其中，每个所述第三半导体芯片包括：
第一区段，在对应的所述第二半导体芯片上；以及
第二区段，在所述热辐射间隔物上。
16.根据权利要求15所述的半导体封装，其中，所述热辐射间隔物包括一对热辐射间隔物，
其中，每个热辐射间隔物支撑对应的所述第三半导体芯片的所述第二区段。
17.根据权利要求16所述的半导体封装，其中，所述第一半导体芯片包括多个热源，所述多个热源在所述第二区域中，
其中，每个所述热源与所述热辐射间隔物竖直重叠。
18.根据权利要求15所述的半导体封装，还包括：
热路径图案，穿透所述模塑层并连接到所述热辐射间隔物；以及
热辐射构件，在所述模塑层上。
19.根据权利要求18所述的半导体封装，其中，所述热路径图案包括多个热路径图案，
其中，至少一个所述热路径图案在所述一对第三半导体芯片之间。
20.根据权利要求18所述的半导体封装，其中，所述热路径图案包括多个热路径图案，
其中，至少一个所述热路径图案在所述热辐射间隔物的边缘上。
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