CN110739236A - novel three-dimensional heterogeneous stacking method with anti-overflow tin structure - Google Patents
novel three-dimensional heterogeneous stacking method with anti-overflow tin structure Download PDFInfo
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- CN110739236A CN110739236A CN201910924284.6A CN201910924284A CN110739236A CN 110739236 A CN110739236 A CN 110739236A CN 201910924284 A CN201910924284 A CN 201910924284A CN 110739236 A CN110739236 A CN 110739236A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81051—Forming additional members
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Abstract
The invention discloses novel three-dimensional heterogeneous stacking methods with anti-overflow tin structures, which specifically comprise the following steps of 101) metal column manufacturing step, 102) retreating step, 103) tin plating step and 104) anti-overflow step, and the invention provides novel three-dimensional heterogeneous stacking methods with anti-overflow tin structures, wherein distances are provided between bumps or welding rings and pad metals to provide enough space for solder reservation.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an novel three-dimensional heterogeneous stacking method with a tin overflow prevention structure.
Background
The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.
However, for the rf chip, such as the analog chip, the area of the analog chip cannot be reduced by the same factor as that of the digital chip , so that the rf microsystem with very high frequency does not have enough area to place the PA/LNA and needs to stack the PA/LNA.
In practical applications, the module stacking process is a process of performing metal fusion bonding on the metal dams on the upper and lower surfaces of the module, for wafer-level bonding process and large-sized chip bonding process, extremely harsh bonding conditions are required to avoid the tin overflow surface on the surfaces of the metal dams or the interconnection pads in the bonding process, for the dams with large areas , the problem that tin overflow does not occur on all chips is basically not realized, and when tin overflow occurs in , the amount of tin on the surface of the dam is greatly reduced, which is very disadvantageous for the subsequent metal fusion process.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides novel three-dimensional heterogeneous stacking methods with a tin overflow prevention structure.
The technical scheme of the invention is as follows:
A new three-dimensional heterogeneous stacking method with a tin overflow prevention structure specifically comprises the following steps:
101) coating th layer of photoresist on the seed layer, removing part of the seed layer through a developing process to expose an area to be electroplated, and electroplating metal to form a metal column, wherein the upper surface of the metal column is a plane;
102) and a second treatment step: coating a second layer of photoresist on the upper surface of the carrier plate processed in the step 101), exposing and developing to expose the part of the metal column, and removing the exposed area at the top of the part of the metal column by wet etching to form a groove; wherein, the depth range of the etched groove is 1nm to 100um, and the etching width range is 1um to 1000 um;
103) tin plating, namely soldering tin on the electroplated metal area, removing the second layer of photoresist, the th layer of photoresist and the seed layer, coating soldering flux, cleaning the soldering flux after refluxing to obtain a structure of the carrier plate with the soldering tin layer on the upper surface;
104) an anti-overflow step: and arranging the chip on the soldering tin in the step 103) to form a new chip module, carrying out surface welding on the new chip module and the new chip module, and welding the new chip module and the new chip module to be tightly combined to form the three-dimensional stacking of the anti-overflow tin structure.
And , the seed layer has layers or multi-layer structure, thickness of 1nm to 100um, and material selected from or mixture of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
, the thickness of the metal column ranges from 1nm to 100um, the structure of the metal column is layers or multi-layer structure, the material is or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and gallium metal alloy.
Compared with the prior art, the invention has the advantages that the protective patterns with different heights are manufactured around the cofferdam or the welding pad, so that the protective patterns can be preferentially contacted to form a surrounding block in the bonding engineering of the wafer or the chip, and thus, the distance between the salient point or the welding ring and the pad metal is to provide enough space for the solder reservation, thereby ensuring that the subsequent metal melting provides three-dimensional stacking of the anti-overflow tin structure.
Drawings
Fig. 1 is a schematic view of a carrier according to the present invention;
FIG. 2 is a schematic view of the seed layer and the electroplating area of FIG. 1;
FIG. 3 is a schematic illustration of the plating area of FIG. 2 according to the present invention;
FIG. 4 is a schematic view of FIG. 3 with a second layer of photoresist provided in accordance with the present invention;
FIG. 5 is a schematic view of FIG. 4 with grooves according to the present invention;
FIG. 6 is a schematic view of FIG. 5 illustrating the removal of the second layer of photoresist;
FIG. 7 is a schematic view of the invention shown in FIG. 6 with the solder removed from the th layer of photoresist;
FIG. 8 is a schematic view of the present invention;
FIG. 9 is a schematic view of a second carrier board of the present invention having metal posts and top solder;
FIG. 10 is a schematic view of FIG. 9 after photoresist removal in accordance with the present invention;
FIG. 11 is a schematic view of the invention shown in FIG. 10 with solder removed;
FIG. 12 is a schematic view of FIG. 11 with portions of the metal pillar removed in accordance with the present invention;
FIG. 13 is a second schematic of the present invention.
The carrier board 101, th layer of photoresist 102, the region to be electroplated 103, the metal pillar 104, the second layer of photoresist 105, and the top solder 106 are marked.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein by .
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described in conjunction with the figures and the detailed description.
Example 1:
as shown in fig. 1 to 8, new three-dimensional heterogeneous stacking methods with a tin overflow prevention structure specifically include the following steps:
101) the manufacturing method of the metal column 104 comprises the steps of manufacturing a seed layer on the upper surface of a carrier plate 101 through a physical sputtering, magnetron sputtering or evaporation process, wherein the seed layer is layers or a multilayer structure, the thickness range is 1nm to 100um, the material is or a mixture of a plurality of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, the seed layer is coated with a layer of photoresist 102, a part of the seed layer is removed through a developing process to expose an area 103 to be electroplated, the metal is electroplated to form the metal column 104, the upper surface of the metal column 104 is a plane, the thicknesses of the metal column 104 and the layer of photoresist 102 are almost equal, the metal column 104 is convenient to electroplate, the thickness range of the metal column 104 is 1nm to 100um, the metal column 104 is layers or a multilayer structure, and the material is or a mixture of a plurality of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and gallium metal alloy and the like.
102) And a second treatment step: coating a second layer of photoresist 105 on the upper surface of the carrier plate 101 processed in step 101), exposing and developing to expose a part of the metal column 104, and removing the exposed area on the top of the part of the metal column 104 by wet etching to form a groove. Wherein, the depth range of the etched groove is 1nm to 100um, and the etching width range is 1um to 1000 um.
103) And a tin plating step, namely, soldering tin on the top of the metal column 104 in the metal electroplating area, removing the second layer of photoresist 105, the th layer of photoresist 102 and the seed layer after soldering tin, then coating soldering flux, and cleaning the soldering flux after refluxing to obtain the structure of the carrier plate 101 with the soldering tin layer on the upper surface.
104) An anti-overflow step: and arranging the chip on the soldering tin in the step 103) to form a new chip module, carrying out surface welding on the new chip module and the new chip module, and welding the new chip module and the new chip module to be tightly combined to form the three-dimensional stacking of the anti-overflow tin structure. That is, the recess region is supported to prevent the excessive pressure from being applied, so that the top solder 106 is squeezed out, thereby completing the three-dimensional stacking of the anti-wicking structure.
Example 2:
as shown in fig. 9 to 13, it is basically the same as embodiment 1 except that the solder is directly applied to the metal posts 104. When the photoresist is removed, the metal pillar 104 is etched synchronously, so that a bump or a solder ring is formed on the top of the metal pillar 104. The process is then the same as in example 1, and the edge area of the metal pillar 104 is supported by the middle bump or bead, so that the top solder 106 is prevented from being squeezed out due to excessive pressure, thereby completing the three-dimensional stacking of the anti-overflow structure. The method comprises the following specific steps:
101) the metal column 104 is prepared by forming a seed layer on the upper surface of the carrier 101, wherein the thickness is in the range of 1nm to 100um, the structure of the seed layer can be layers or multiple layers, the metal material can be or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, and the region to be plated 103 is exposed by coating photoresist and developing.
The metal pillar 104 formed by electroplating metal has a thickness ranging from 1nm to 100um, and has a structure of layers or multiple layers, and can be made of or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, gallium metal alloy, and the like.
102) And electroplating a top layer of soldering tin on the top of the metal column 104, wherein the thickness of the soldering tin ranges from 1nm to 100um, the soldering tin can be layers or a multilayer structure, and the metal material can be or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, gallium metal alloy and the like.
103) Tin plating step: removing the photoresist, removing the seed layer, coating the soldering flux, and cleaning the soldering flux after refluxing to obtain a structure with a soldering tin layer on the surface;
removing tin by wet etching to expose the edge part of the metal column 104, wherein the width of the exposed part is between 100nm and 100 um; wet etching the metal pillar 104 to remove the portion of the metal pillar 104 not protected by tin; the removed portion has almost the same width as the exposed portion.
104) An anti-overflow step: the chip is arranged on the soldering tin in the step 103) to form a new chip module, the two new chip modules are subjected to surface mounting through a surface mounting process, after the salient points or the welding rings in the middle of the metal column 104 are tightly combined, the edge area of the metal column 104 is prevented from being extruded by the soldering tin 106 at the top with overlarge pressure due to the intermediate support, and thus the three-dimensional stacking of the anti-overflow tin structure is completed.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (3)
1, novel three-dimensional heterogeneous stacking method with anti-overflow tin structure, which is characterized by comprising the following steps:
101) coating th layer of photoresist on the seed layer, removing part of the seed layer through a developing process to expose an area to be electroplated, and electroplating metal to form a metal column, wherein the upper surface of the metal column is a plane;
102) and a second treatment step: coating a second layer of photoresist on the upper surface of the carrier plate processed in the step 101), exposing and developing to expose the part of the metal column, and removing the exposed area at the top of the part of the metal column by wet etching to form a groove; wherein, the depth range of the etched groove is 1nm to 100um, and the etching width range is 1um to 1000 um;
103) tin plating, namely soldering tin on the electroplated metal area, removing the second layer of photoresist, the th layer of photoresist and the seed layer, coating soldering flux, cleaning the soldering flux after refluxing to obtain a structure of the carrier plate with the soldering tin layer on the upper surface;
104) an anti-overflow step: and arranging the chip on the soldering tin in the step 103) to form a new chip module, carrying out surface welding on the new chip module and the new chip module, and welding the new chip module and the new chip module to be tightly combined to form the three-dimensional stacking of the anti-overflow tin structure.
2. The new three-dimensional heterogeneous stacking method with anti-overflow Sn structure as claimed in claim 1, wherein the seed layer has or multi-layer structure with thickness ranging from 1nm to 100 μm, and the material is or more of Ti, Cu, Al, Ag, Pd, Au, Tl, Sn and Ni.
3. The new three-dimensional heterogeneous stacking method with anti-overflow tin structure as claimed in claim 1, wherein the thickness of the metal pillar ranges from 1nm to 100um, the structure of the metal pillar itself is layers or multi-layer structure, the material is or more mixed in titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, gallium metal alloy.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910924284.6A CN110739236A (en) | 2019-09-27 | 2019-09-27 | novel three-dimensional heterogeneous stacking method with anti-overflow tin structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910924284.6A CN110739236A (en) | 2019-09-27 | 2019-09-27 | novel three-dimensional heterogeneous stacking method with anti-overflow tin structure |
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| CN110739236A true CN110739236A (en) | 2020-01-31 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014017454A (en) * | 2012-07-11 | 2014-01-30 | Fujitsu Semiconductor Ltd | Semiconductor device, semiconductor package manufacturing method and semiconductor package |
| CN103855116A (en) * | 2012-12-06 | 2014-06-11 | 富士通株式会社 | Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus |
| CN106104799A (en) * | 2014-03-28 | 2016-11-09 | 英特尔公司 | Method and process for the interconnection of EMIB chip |
| US20170133346A1 (en) * | 2012-07-25 | 2017-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump Structure for Yield Improvement |
-
2019
- 2019-09-27 CN CN201910924284.6A patent/CN110739236A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014017454A (en) * | 2012-07-11 | 2014-01-30 | Fujitsu Semiconductor Ltd | Semiconductor device, semiconductor package manufacturing method and semiconductor package |
| US20170133346A1 (en) * | 2012-07-25 | 2017-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump Structure for Yield Improvement |
| CN103855116A (en) * | 2012-12-06 | 2014-06-11 | 富士通株式会社 | Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus |
| CN106104799A (en) * | 2014-03-28 | 2016-11-09 | 英特尔公司 | Method and process for the interconnection of EMIB chip |
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Application publication date: 20200131 |