CN110739230A - manufacturing method of three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points - Google Patents
manufacturing method of three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention discloses a three-dimensional stacking heat dissipation module manufacturing method aiming at a radio frequency chip heat concentration point, which specifically comprises the following steps of 101) manufacturing an upper heat dissipation base, 102) manufacturing a heat dissipation base, and 103) integrating a chip, wherein a heat dissipation micro-flow channel is arranged at the bottom of the chip to serve as a heat radiator, and a secondary heat dissipation micro-flow channel is distributed and arranged at the position of a chip heating point or a nearby area, so that the heat in the area can be quickly taken away by heat dissipation fluid, and the problem that the chip fails due to the fact that a hot spot is large in heat is solved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of three-dimensional stacked heat dissipation modules for radio frequency chip heat concentration points.
Background
The rapid development of electronic products is the main driving force of the evolution of packaging technology, and miniaturization, high density, high frequency, high speed, high performance, high reliability and low cost are the mainstream development directions of advanced packaging, wherein system-in-package is the most important and most potential of the technology for satisfying the high-density system integration.
In various system-in-package (SIP) packages, a silicon interposer is used as a substrate technology of the SIP package, which provides the shortest connection distance, the smallest pad size and the smallest center-to-center distance for the chip-to-chip and the chip-to-PCB. Advantages of silicon interposer technology over other interconnect technologies, such as wire bonding, include: better electrical performance, higher bandwidth, higher density, smaller size, lighter weight.
However, a silicon interposer embedding process needs to use a relatively harsh heat dissipation structure, for some radio frequency chips, the heating positions may be only some points with a small area, and even if the whole radiator works fully under the chip, the heat dissipation capability of the radiator is still very little to the heating points with the small area, which may cause the chip to fail.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides methods for manufacturing the three-dimensional stacking heat dissipation module aiming at the heat concentration point of the radio frequency chip.
The technical scheme of the invention is as follows:
method for manufacturing three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points, comprising the following steps:
101) an upper heat dissipation base manufacturing step: the upper heat dissipation base comprises an upper layer and a lower layer, wherein silicon oxide or silicon nitride is deposited on the surfaces of the upper layer and the lower layer or an insulating layer is formed by direct thermal oxidation, and a seed layer is manufactured above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; manufacturing RDL on the seed layer;
manufacturing microfluidic grooves on the upper surfaces of the upper layer and the lower layer through photoetching and etching processes; the micro-flow grooves directly pass through the heating point area of the radio frequency chip, or are uniformly distributed in the area outside the heating point area of the radio frequency chip;
forming an upper heat dissipation base with micro-circulation inside on the upper surfaces of the upper layer and the lower layer through a eutectic bonding process;
102) the manufacturing step of the heat dissipation base comprises the following steps: repeating the step 101) to manufacture a lower heat dissipation base, and bonding the upper heat dissipation base and the lower heat dissipation base through a eutectic bonding process; wherein, the micro-flow grooves of the upper heat dissipation base and the lower heat dissipation base are stacked in a cross distribution manner;
103) chip integration step: and attaching the radio frequency chip to the corresponding position on the surface of the heat dissipation base to form the three-dimensional stacked heat dissipation module.
, the RDL manufacturing process comprises RDL routing and a PAD, an insulating layer is manufactured by depositing silicon oxide or silicon nitride, a chip PAD is exposed by photoetching and dry etching, RDL routing arrangement is performed by photoetching and electroplating processes, wherein the RDL routing adopts or a mixture of copper, aluminum, nickel, silver, gold and tin, the RDL routing adopts a layer or multilayer structure, the thickness range is 10nm to 1000um, bonding metal is manufactured by photoetching and electroplating processes to form the PAD, and the window diameter of the PAD is 10um to 10000 um.
, covering an insulating layer on the surface of the RDL and exposing the pad through a windowing process.
, the thickness of the insulating layer is 10nm to 100um, the seed layer is layer or multi-layer structure, the thickness is 1nm to 100um, the material is or a mixture of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, the thickness of the insulating layer is 10nm to 1000 um.
And , adopting wafers of 4, 6, 8 and 12 inches wafers as the upper layer and the lower layer, wherein the thickness ranges from 200um to 2000um, and the materials are glass, quartz, silicon carbide, alumina, epoxy resin or polyurethane.
Step , the microfluidic channel has a depth in the range of 10um to 700um and a length in the range of 100um to 10 mm.
, the micro-flow grooves of the lower heat sink base are vertically distributed.
Compared with the prior art, the invention has the advantages that: according to the invention, the heat dissipation micro-flow channel is arranged at the bottom of the chip to serve as a radiator, and the secondary heat dissipation micro-flow channels are distributed and arranged at the position of the heating point of the chip or in the area near the heating point of the chip, so that the heat in the area can be quickly taken away by the heat dissipation fluid, and the problem that the chip fails due to the fact that the hot point has large heat is avoided.
Drawings
FIG. 1 is a schematic diagram of an RF chip according to the present invention;
FIG. 2 is a schematic view of an upper heat sink base according to the present invention;
FIG. 3 is a schematic view of a lower heat sink base according to the present invention;
FIG. 4 is a schematic cross-sectional view of samples of the present invention;
fig. 5 is an overall cross-sectional view of the lower heat sink base of the present invention employing vertical micro-flow grooves.
The labels in the figure are: the chip comprises a radio frequency chip 101, a heating point area 102, an upper heat dissipation base 103, a micro-flow groove 104, a lower heat dissipation base 105 and a micro-flow groove 106 which is vertically distributed.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein by .
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described in conjunction with the figures and the detailed description.
Example 1:
as shown in fig. 1 to 4, methods for manufacturing a three-dimensional stacked heat dissipation module for a heat concentration point of an rf chip 101 include the following steps:
101) the upper heat dissipation base 103 comprises an upper layer and a lower layer, wherein silicon oxide or silicon nitride is deposited on the surfaces of the upper layer and the lower layer, or an insulating layer is formed by direct thermal oxidation, the thickness range of the insulating layer is between 10nm and 100um, a seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness range of the seed layer is between 1nm and 100um, the structure of the seed layer can be layers or multiple layers, the material can be or a mixture of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like, RDL is manufactured on the seed layer, the manufacturing process of the RDL comprises RDL routing and bonding PADs, the insulating layer is manufactured through depositing silicon oxide or silicon nitride, the thickness range of the insulating layer is between 10nm and 100um, the chip is exposed through photoetching and dry etching, the routing is arranged through photoetching and electroplating, the RDL is manufactured through a mixed welding PAD process of or a mixture of copper, aluminum, nickel, silver, gold and tin, the bonding PAD is manufactured through a layer or a multilayer structure, the thickness range of PAD is between 10nm and 1000 nm, and the bonding window is formed through photoetching and electroplating, and the diameter of the bonding window is formed between 10nm and the bonding window.
The upper surfaces of the upper layer and the lower layer are both manufactured with a micro-flow groove 104 through photoetching and etching processes, the micro-flow groove 104 adopts a plurality of S shapes which are connected in an end-to-end mode, the transition position of the micro-flow groove is of a right-angle structure or an arc transition mode, wherein the micro-flow groove 104 directly passes through the heating point area 102 of the radio frequency chip 101, or the micro-flow groove 104 is uniformly distributed outside the heating point area of the radio frequency chip 101.
The upper surface of the upper layer and the lower layer are formed into an upper heat dissipation base 103 with micro-circulation inside through a eutectic bonding process, wherein kinds of wafers with the thicknesses ranging from 200um to 2000um are adopted in the upper layer and the lower layer, the wafers are made of 4 inches, 6 inches, 8 inches and 12 inches, other materials can be adopted, the materials comprise inorganic materials such as glass, quartz, silicon carbide and aluminum oxide, and organic materials such as epoxy resin and polyurethane can be adopted, and the main function of the base is to provide a supporting effect.
102) The manufacturing step of the heat dissipation base comprises the following steps: and repeating the step 101) to manufacture the lower heat dissipation base 105, and bonding the upper heat dissipation base 103 and the lower heat dissipation base 105 through a eutectic bonding process. The micro-flow grooves 104 of the upper heat dissipation base 103 and the lower heat dissipation base 105 are arranged in a staggered manner, that is, the upper heat dissipation base 103 and the lower heat dissipation base 105 have the same structure and thus can be horizontally and vertically arranged with each other when stacked. Or the micro-flow grooves 104 of the upper heat dissipation base 103 are uniformly distributed in the region outside the heating point of the rf chip 101, the micro-flow grooves 104 of the lower heat dissipation base 105 directly pass through the heating point region 102 of the rf chip 101, and the micro-flow grooves 104 between the upper heat dissipation base and the lower heat dissipation base have a cross point.
103) Chip integration step: and attaching the radio frequency chip 101 to the corresponding position on the surface of the heat dissipation base to form a three-dimensional stacked heat dissipation module.
Example 2:
as shown in fig. 5, the difference from embodiment 1 is that the design of the micro-flow grooves 104 of the lower heat dissipation base 105 is different, and the micro-flow grooves 106 are vertically distributed, that is, the micro-flow grooves 104 similar to a spiral shape are formed, and the positions of the micro-flow grooves 104 of the lower heat dissipation base 105 correspond to the positions of the rf chips 101 to be attached.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (7)
1, method for manufacturing three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points, which is characterized by comprising the following steps:
101) an upper heat dissipation base manufacturing step: the upper heat dissipation base comprises an upper layer and a lower layer, wherein silicon oxide or silicon nitride is deposited on the surfaces of the upper layer and the lower layer or an insulating layer is formed by direct thermal oxidation, and a seed layer is manufactured above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; manufacturing RDL on the seed layer;
manufacturing microfluidic grooves on the upper surfaces of the upper layer and the lower layer through photoetching and etching processes; the micro-flow grooves directly pass through the heating point area of the radio frequency chip, or are uniformly distributed in the area outside the heating point area of the radio frequency chip;
forming an upper heat dissipation base with micro-circulation inside on the upper surfaces of the upper layer and the lower layer through a eutectic bonding process;
102) the manufacturing step of the heat dissipation base comprises the following steps: repeating the step 101) to manufacture a lower heat dissipation base, and bonding the upper heat dissipation base and the lower heat dissipation base through a eutectic bonding process; wherein, the micro-flow grooves of the upper heat dissipation base and the lower heat dissipation base are stacked in a cross distribution manner;
103) chip integration step: and attaching the radio frequency chip to the corresponding position on the surface of the heat dissipation base to form the three-dimensional stacked heat dissipation module.
2. The method for manufacturing a three-dimensional stacked heat dissipation module aiming at a heat concentration point of a radio frequency chip, according to claim 1, wherein the RDL manufacturing process comprises RDL wiring and a PAD, an insulating layer is manufactured by depositing silicon oxide or silicon nitride, a chip PAD is exposed by photoetching and dry etching, RDL wiring arrangement is performed by photoetching and electroplating processes, wherein the RDL wiring adopts or a mixture of more of copper, aluminum, nickel, silver, gold and tin, the RDL wiring adopts a layer or multilayer structure, the thickness range is 10nm to 1000um, bonding metal is manufactured by photoetching and electroplating processes to form the PAD, and the opening diameter of the PAD is 10um to 10000 um.
3. The method of claim 2, wherein the RDL is covered with an insulating layer and the pads are exposed by a windowing process.
4. The method for manufacturing three-dimensional stacked heat dissipation modules aiming at radio frequency chip heat concentration points according to claim 2, wherein the thickness of the insulation layer ranges from 10nm to 100um, the seed layer has a structure of layers or multi-layer structures, the thickness ranges from 1nm to 100um, the material is or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the thickness of the insulation layer ranges from 10nm to 1000 um.
5. The method for manufacturing three-dimensional stacked heat dissipation modules for heat concentration points of RF chips as claimed in claim 1, wherein the upper and lower layers are wafers of 4, 6, 8, 12 inches, the thickness is 200um to 2000um, and the material is glass, quartz, silicon carbide, alumina, epoxy resin or polyurethane.
6. The method of claim 1, wherein the micro-flow grooves have a depth of 10um to 700um and a length of 100um to 10 mm.
7. The method of claim 1, wherein the micro-grooves of the lower heat spreader base are vertically disposed.
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| CN201910904852.6A CN110739230A (en) | 2019-09-24 | 2019-09-24 | manufacturing method of three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration points |
| CN202010587711.9A CN111653491B (en) | 2019-09-24 | 2020-06-24 | Manufacturing method of three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration point |
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| WO2022227189A1 (en) * | 2021-04-26 | 2022-11-03 | 武汉新芯集成电路制造有限公司 | Three-dimensional integrated circuit module and fabrication method therefor |
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| CN110010491B (en) * | 2018-12-25 | 2021-05-28 | 浙江集迈科微电子有限公司 | Manufacturing process of cubic structure of multilayer stacked radio frequency microsystem |
| CN110010570B (en) * | 2018-12-25 | 2021-01-26 | 浙江集迈科微电子有限公司 | Manufacturing process of radio frequency micro-system assembly for liquid immersion heat dissipation |
| CN110010574B (en) * | 2018-12-29 | 2021-02-09 | 浙江臻镭科技股份有限公司 | Multilayer stacked longitudinally interconnected radio frequency structure and manufacturing method thereof |
| CN110010561B (en) * | 2018-12-31 | 2021-02-26 | 浙江臻镭科技股份有限公司 | Radio frequency structure with stacked multilayer chips and manufacturing method thereof |
| CN110255490A (en) * | 2019-06-26 | 2019-09-20 | 中国电子科技集团公司第三十八研究所 | Integrated fluid channel radiator structure, preparation method and wafer level packaging structure |
-
2019
- 2019-09-24 CN CN201910904852.6A patent/CN110739230A/en not_active Withdrawn
-
2020
- 2020-06-24 CN CN202010587711.9A patent/CN111653491B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022227189A1 (en) * | 2021-04-26 | 2022-11-03 | 武汉新芯集成电路制造有限公司 | Three-dimensional integrated circuit module and fabrication method therefor |
| CN113327904A (en) * | 2021-04-29 | 2021-08-31 | 中国电子科技集团公司第二十九研究所 | Double-sided efficient heat dissipation airtight packaging structure and preparation method thereof |
| CN113327904B (en) * | 2021-04-29 | 2023-06-02 | 中国电子科技集团公司第二十九研究所 | Double-sided efficient heat-dissipation airtight packaging structure and preparation method thereof |
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| Publication number | Publication date |
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| CN111653491B (en) | 2021-12-17 |
| CN111653491A (en) | 2020-09-11 |
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