CN110739212A - Hard mask preparation method and semiconductor device manufacturing method - Google Patents

Hard mask preparation method and semiconductor device manufacturing method Download PDF

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Publication number
CN110739212A
CN110739212A CN201911047827.7A CN201911047827A CN110739212A CN 110739212 A CN110739212 A CN 110739212A CN 201911047827 A CN201911047827 A CN 201911047827A CN 110739212 A CN110739212 A CN 110739212A
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layer
dielectric layer
hard mask
etching
patterned
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杨建国
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention provides a preparation method of hard masks, which comprises the steps of S1, providing a substrate, sequentially stacking a hard mask layer, a dielectric layer and a second dielectric layer above the substrate, S2, depositing a photoresist material on the upper surface of the second dielectric layer to form a photoresist layer, and performing photoetching to form a patterned photoresist layer, S3, etching the second dielectric layer by taking the patterned photoresist layer as a mask to form a patterned second dielectric layer, S4, removing the patterned photoresist layer, S5, etching the dielectric layer and the hard mask layer by taking the patterned second dielectric layer as a mask to form a hard mask pattern, namely, the invention increases the available space between photoetching and dry etching by adding the second dielectric layer, simultaneously increases the adjustable space of a photoetching process, and also increases the adjustable space of a dry etching process by adding , thereby achieving the purpose of increasing the whole process window.

Description

Hard mask preparation method and semiconductor device manufacturing method
Technical Field
The invention relates to the field of semiconductors, in particular to a preparation method of hard masks and a manufacturing method of a semiconductor device.
Background
As integrated circuits become smaller, metal hard masks are increasingly used to control feature size (CD) and feature size uniformity.
The photoresist thickness is required to be maintained in the range of , so that the photoetching process window is limited, and the insufficient photoetching process window causes the process window of the metal hard mask dry etching to be very small and the adjustable space is limited in the metal hard mask dry etching (MHM-ET) process.
Disclosure of Invention
The invention aims to provide a preparation method of hard masks and a manufacturing method of a semiconductor device, so as to increase the available space of photoetching and dry etching, thereby realizing the purpose of increasing the whole process window.
In order to achieve the above object, the present invention provides a method for preparing hard masks, comprising:
step S1, providing a substrate, and sequentially stacking a hard mask layer, a th dielectric layer and a second dielectric layer above the substrate;
step S2: depositing a photoresist material on the upper surface of the second medium layer to form a photoresist layer, and performing photoetching to form a patterned photoresist layer;
step S3: etching the second dielectric layer by taking the patterned photoresist layer as a mask to form a patterned second dielectric layer;
step S4: removing the photoresist layer;
and step S5, etching the dielectric layer and the hard mask layer by taking the patterned second dielectric layer as a mask to form a hard mask pattern.
Optionally, in the method for preparing a hard mask, the hard mask includes a metal hard mask, which at least includes metal nitride layers.
Optionally, in the method for preparing a hard mask, the etching in step S3 is wet etching.
Optionally, in the preparation method of the hard mask, the th dielectric layer has a high selectivity ratio relative to the second dielectric layer in wet etching, and the value of the high selectivity ratio is 15-30.
Optionally, in the method for preparing a hard mask, the etching of the wet etching is performedThe reagent accurately controls the etching rate to
Figure BDA0002254566000000022
The following.
Optionally, in the preparation method of the hard mask, the etching reagent for wet etching includes a mixed reagent of hydrofluoric acid and nitric acid.
Optionally, in the preparation method of the hard mask, the material of the second dielectric layer includes tetraethoxysilane.
Optionally, in the preparation method of the hard mask, the thickness of the second dielectric layer is
Figure BDA0002254566000000021
Optionally, in the method for preparing a hard mask, the connection position of the upper surface of the substrate exposed after etching in step S5 is lower than the hard mask layer.
To achieve the above and other objects, the present invention further provides methods for manufacturing a semiconductor device, comprising forming a hard mask having a desired pattern on a surface of a substrate by using the above-described method for forming a hard mask.
In summary, the present invention provides a method for preparing hard masks, which includes providing a substrate, sequentially stacking a hard mask layer, a th dielectric layer and a second dielectric layer on the substrate, depositing a photoresist material on the upper surface of the second dielectric layer to form a photoresist layer, performing photolithography to form a patterned photoresist layer, etching the second dielectric layer with the patterned photoresist layer as a mask to form a patterned second dielectric layer, removing the photoresist layer, and etching the th dielectric layer and the hard mask layer with the patterned second dielectric layer as a mask to form a hard mask pattern.
Drawings
FIG. 1 is a flow chart of a method for fabricating a hard mask according to an embodiment of the present invention;
FIGS. 2-6 are schematic structural diagrams illustrating steps of a method for forming a hard mask according to an embodiment of the present invention;
in fig. 1 to 6:
10-substrate, 101-link location, 20-hard mask layer, 201-patterned hard mask layer, 30- th dielectric layer, 301-patterned th dielectric layer, 40-second dielectric layer, 401-patterned second dielectric layer, 50-patterned photoresist layer.
Detailed Description
In order to make the objects, advantages and features of the present invention more clear, the following method for fabricating a metal hard mask according to an embodiment of the present invention is described in detail with reference to fig. 1-6, wherein the drawings are simplified and non-precise scales are used for convenience and clarity to assist in describing the embodiments of the present invention.
As shown in fig. 1, the invention discloses a method for manufacturing hard masks, comprising the following steps:
step S1, providing substrate 10, and stacking hard mask layer 20, dielectric layer 30 and second dielectric layer 40 on the substrate 10 in sequence;
step S2: depositing a photoresist material on the upper surface of the second dielectric layer 40 to form a photoresist layer, and performing photolithography to form a patterned photoresist layer 50;
step S3: etching the second dielectric layer 40 by using the patterned photoresist layer 50 as a mask to form a patterned second dielectric layer 401;
step S4: removing the patterned photoresist layer 50;
and step S5, etching the dielectric layer 30 and the hard mask layer 20 by using the patterned second dielectric layer 401 as a mask to form a hard mask pattern.
The substrate 10 may be, among other things, a conventional silicon substrate or other substrate comprising a layer of semiconductive material. The upper surface of the substrate 10 is formed hard by depositionAnd a mask layer 20, wherein the deposition comprises physical deposition or chemical deposition, and the like, and is preferably physical deposition. The thickness of the hard mask layer 20 is preferably set to be thick
Figure BDA0002254566000000041
The hard mask layer can be made of a metal hard mask, a silicon nitride hard mask, a silicon dioxide hard mask or the like, preferably the metal hard mask, the metal hard mask at least comprises layers of metal nitride layers, and the metal nitride layer in step is preferably a titanium nitride layer.
The th dielectric layer 30 is formed on the upper surface of the hard mask layer 20 by a deposition method, the deposition method comprises chemical deposition or physical deposition, preferably chemical deposition, and is preferably chemical vapor deposition, the thickness of the th dielectric layer 30 is preferably the same as that of the chemical vapor deposition
Figure BDA0002254566000000042
The th dielectric 30 material comprises at least of silicon nitride, silicon oxynitride and silicon oxide, preferably silicon nitride.
The second dielectric layer 40 is formed on the upper surface of the dielectric layer 30 by a deposition method, wherein the deposition method comprises chemical deposition or physical deposition, preferably chemical deposition, and steps preferably chemical vapor deposition, the thickness of the second dielectric layer 40 is preferably the same as that of the first dielectric layer 40
Figure BDA0002254566000000043
The material of the second dielectric layer 40 is preferably tetraethyl orthosilicate (TEOS).
As shown in fig. 3, in step S2, a photoresist material is deposited on the upper surface of the second dielectric layer 40 to form a photoresist layer, and the formed photoresist layer is photolithographically developed to form the patterned photoresist layer 50. Specifically, the patterned photoresist layer 50 includes two steps, i.e. depositing a photoresist and performing photolithography and development, i.e. depositing a photoresist material on the surface of the second dielectric layer 40, when the photoresist material is deposited to a thickness of
Figure BDA0002254566000000044
The deposition process is stopped and the deposited photoresist material is then developed by photolithography to form a patterned photoresist layer 50, opening the process window. The photoresist material may be a positive photoresist material or a negative photoresist material. Because of the existence of the second dielectric layer 40, the thickness of the patterned photoresist layer 50 can be thinner without the occurrence of insufficient etching photoresist and excessive development, so that the adjustable range of the thickness of the patterned photoresist layer 50 is increased, i.e. the process window of the photolithography is increased.
As shown in fig. 4, in step S3, the patterned photoresist layer 50 is used as a mask to etch the second dielectric layer 40 to form a patterned second dielectric layer 401, wherein the etching method is preferably wet etching, the dielectric layer has a high selectivity relative to the second dielectric layer in the wet etching, the value of the high selectivity is preferably 15 to 30, that is, the etching rate ratio of the etching reagent to the second dielectric layer 40 and the dielectric layer 30 is 15:1 to 30:1, that is, the etching reagent only has an obvious etching effect on the second dielectric layer 40 and a very weak etching effect on the dielectric layer 30, and the etching reagent needs to meet the requirement that the etching rate can be accurately controlled to reach
Figure BDA0002254566000000045
, etching the second dielectric layer 40 with the etching agent using the patterned photoresist layer 50 as a mask to expose the th dielectric layer 30 to form the patterned second dielectric layer 401. since the th dielectric layer 30 has a high selectivity in the wet etching process with respect to the second dielectric layer 40, the th dielectric layer 30 can be used as a stop layer for the wet etching process, but the th dielectric layer 30 is etched away slightly, i.e., stopped in a part of the depth of the th dielectric layer 30, and the etched thickness is less than that of the part of the depth of the th dielectric layer 30
Figure BDA0002254566000000051
As shown in fig. 5, in step S4, the patterned photoresist layer 50 is removed, the photoresist material removing process may be a wet etching process or a dry etching process, because the dry etching rate is high and the environmental pollution is small, the photoresist material is preferably removed by dry etching, and in step , the photoresist material is preferably removed by plasma dry etching, for example, using oxygen as an etching gas for plasma dry etching to remove the remaining patterned photoresist layer 50 on the surface of the patterned second dielectric layer 401, so that the upper surface of the patterned second dielectric layer 401 is completely exposed.
As shown in fig. 6, in step S5, the dielectric layer 30 and the hard mask layer 20 are etched using the patterned second dielectric layer 401 as a mask to form a hard mask pattern, the etching method is preferably dry etching, i.e., after the patterned photoresist layer 50 is removed, the dielectric layer 30 and the hard mask layer 20 corresponding to the position of the process window are removed by dry etching to form a patterned dielectric layer 301 and a patterned hard mask layer 201, i.e., a hard mask pattern4、CHF3、CH2F2Or CH3F, any combination thereof, and the like, as well as other etching media commonly used in the art. An etching rate of
Figure BDA0002254566000000052
Etching is stopped in the substrate 10 with a partial depth below the hard mask layer 20, so that the upper surface of the substrate 10 exposed after etching is lower than the bottom surface of the hard mask layer 20, that is, the connecting position 101 after etching is lower than the bottom surface of the hard mask layer 20, and the connecting position 101 is the upper surface of the substrate 10 exposed.
Meanwhile, the thickness of the photoresist can be thinner due to the addition of the second dielectric layer, so that the adjustable space of the photoetching is increased, and further , the adjustable space of the photoresist thickness is increased, so that the adjustable space of the subsequent dry etching process is also increased, and the whole process window is enlarged.
The invention also provides a manufacturing method of semiconductor devices, which comprises the step of preparing a hard mask with a required pattern on the surface of a substrate by adopting the hard mask preparation method.
Finally, it should be noted that the above-mentioned embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. That is, all equivalent changes and modifications made according to the content of the claims of the present invention should be within the technical scope of the present invention.

Claims (10)

  1. The preparation method of the hard masks is characterized by comprising the following steps:
    step S1, providing a substrate, and sequentially stacking a hard mask layer, a th dielectric layer and a second dielectric layer above the substrate;
    step S2: depositing a photoresist material on the upper surface of the second medium layer to form a photoresist layer, and performing photoetching to form a patterned photoresist layer;
    step S3: etching the second dielectric layer by taking the patterned photoresist layer as a mask to form a patterned second dielectric layer;
    step S4: removing the patterned photoresist layer;
    and step S5, etching the dielectric layer and the hard mask layer to form a hard mask pattern by taking the patterned second dielectric layer as a mask.
  2. 2. The method of claim 1, wherein said hard mask layer comprises a metal hard mask layer, said metal hard mask layer comprising at least metal nitride layers.
  3. 3. The method for manufacturing a hard mask according to claim 1, wherein the etching in step S3 includes wet etching.
  4. 4. The method for preparing the hard mask as claimed in claim 3, wherein the th dielectric layer has a high selectivity ratio in wet etching relative to the second dielectric layer, and the value of the high selectivity ratio is 15-30.
  5. 5. The method of claim 4, wherein the etching agent of the wet etch precisely controls the etch rate to a level that is accurate to
    Figure FDA0002254565990000011
    The following.
  6. 6. The method for preparing a hard mask according to claim 5, wherein the etching reagent for the wet etching comprises a mixed reagent of hydrofluoric acid and nitric acid.
  7. 7. The method of claim 1, wherein the material of the second dielectric layer comprises tetraethylorthosilicate.
  8. 8. The method of claim 1, wherein the second dielectric layer has a thickness of
    Figure FDA0002254565990000012
  9. 9. The method for preparing a hardmask layer according to claim 1, wherein the etching in step S5 is stopped at a portion of the depth of the substrate below the hardmask layer, such that the top surface of the substrate exposed after etching is lower than the bottom surface of the hardmask layer.
  10. A method for manufacturing semiconductor devices, comprising preparing a hard mask having a desired pattern on a surface of a substrate by the method for preparing a hard mask according to any of claims 1 to 9.
CN201911047827.7A 2019-10-30 2019-10-30 Hard mask preparation method and semiconductor device manufacturing method Pending CN110739212A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113066761A (en) * 2021-03-18 2021-07-02 长鑫存储技术有限公司 Manufacturing method of semiconductor device
CN114361012A (en) * 2021-12-31 2022-04-15 广东省大湾区集成电路与***应用研究院 Semiconductor device and manufacturing method thereof
CN114446769A (en) * 2020-11-06 2022-05-06 长鑫存储技术有限公司 Method for manufacturing semiconductor device
CN116299854A (en) * 2023-02-15 2023-06-23 上海铭锟半导体有限公司 Preparation method of silicon nitride device based on stress dispersion and crack blocking patterns

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CN108666208A (en) * 2017-03-30 2018-10-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
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KR19990038804A (en) * 1997-11-07 1999-06-05 구본준 Method of manufacturing mask of semiconductor device
US20010038972A1 (en) * 1998-11-20 2001-11-08 Christopher F. Lyons Ultra-thin resist shallow trench process using metal hard mask
US20080064203A1 (en) * 2006-09-11 2008-03-13 Pei-Yu Chou Method for fabricating a contact hole
CN102479693A (en) * 2010-11-30 2012-05-30 中芯国际集成电路制造(北京)有限公司 Gate forming method
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CN114446769A (en) * 2020-11-06 2022-05-06 长鑫存储技术有限公司 Method for manufacturing semiconductor device
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CN114361012B (en) * 2021-12-31 2024-05-31 广东省大湾区集成电路与***应用研究院 Semiconductor device and manufacturing method thereof
CN116299854A (en) * 2023-02-15 2023-06-23 上海铭锟半导体有限公司 Preparation method of silicon nitride device based on stress dispersion and crack blocking patterns
CN116299854B (en) * 2023-02-15 2024-02-13 上海铭锟半导体有限公司 Preparation method of silicon nitride device based on stress dispersion and crack blocking patterns

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Application publication date: 20200131