CN110704332B - Flash memory medium optimization method and nonvolatile storage device - Google Patents
Flash memory medium optimization method and nonvolatile storage device Download PDFInfo
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- CN110704332B CN110704332B CN201910807412.9A CN201910807412A CN110704332B CN 110704332 B CN110704332 B CN 110704332B CN 201910807412 A CN201910807412 A CN 201910807412A CN 110704332 B CN110704332 B CN 110704332B
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Abstract
The invention relates to the field of data storage, and discloses a flash memory medium optimization method and a nonvolatile storage device. The flash memory medium comprises a plurality of physical blocks, and the flash memory medium optimization method comprises the following steps: selecting a physical block with a first proportion from the plurality of physical blocks as a reference physical block; performing erase/write operations for a preset number of times on the reference physical block; acquiring a reference performance parameter of a reference physical block after executing erasing/writing operation for a preset number of times; and adjusting the performance parameters of the rest physical blocks according to the reference performance parameters. The embodiment of the invention can optimize the performance of the residual physical blocks and improve the accuracy of data reading and writing of the residual physical blocks.
Description
Technical Field
The present invention relates to the field of data storage, and in particular, to a flash memory medium optimization method and a nonvolatile memory device.
Background
With the development and wide application of technologies such as internet, cloud computing, internet of things and the like, mass data inevitably generated in human activities need to be processed and stored, so that higher requirements are put on a storage system, and the use of storage equipment or the storage system is influenced by the performance of a flash memory medium as a carrier for storing data.
At present, when a flash memory medium in any use stage executes read-write operation, a physical block of a target area is directly read and written according to an operation instruction and basic performance parameters of the physical block, but as long-term read-write or no use of a certain area, bit of the block area is reversed, or as the number of times of erase/write operation increases, the media characteristics of the flash memory medium change, the performance of the physical block in the flash memory medium may be reduced, so that data is lost or read incorrectly.
Disclosure of Invention
Embodiments of the present invention are directed to a flash memory medium optimization method and a non-volatile storage device, which can optimize performance of remaining physical blocks.
In order to solve the above technical problems, embodiments of the present invention provide the following technical solutions:
in a first aspect, an embodiment of the present invention provides a method for optimizing a flash memory medium, where the flash memory medium includes a plurality of physical blocks, and the method includes:
selecting a physical block with a first proportion from the plurality of physical blocks as a reference physical block;
performing erase/write operations for a preset number of times on the reference physical block;
acquiring a reference performance parameter of a reference physical block after executing erasing/writing operation for a preset number of times;
and adjusting the performance parameters of the rest physical blocks according to the reference performance parameters.
In some embodiments, after selecting a first proportion of physical blocks from the number of physical blocks as reference physical blocks, the method further comprises:
acquiring basic performance parameters of the physical blocks;
dividing the physical blocks into at least two reference levels according to the basic performance parameters;
then, the adjusting the performance parameter of the remaining physical block according to the reference performance parameter includes:
identifying a reference level of the reference physical block;
and adjusting the performance parameters of the residual physical blocks in the same level according to the reference level and the reference performance parameters.
In some embodiments, the base performance parameters include raw bit error rate, reference voltage distribution, and delay parameters.
In some embodiments, each of the physical blocks has a number;
the selecting a first proportion of physical blocks from the plurality of physical blocks as a reference physical block comprises:
dividing the physical block into a plurality of number sections according to the number of the physical block;
and respectively selecting physical blocks with a first preset proportion from each serial number section to obtain the physical blocks with the first proportion.
In some embodiments, the selecting a first proportion of the physical blocks from the plurality of physical blocks as a reference physical block includes:
acquiring the original bit error rate of each physical block;
dividing the physical blocks into physical blocks with a plurality of threshold sections according to the original bit error rate;
and respectively selecting physical blocks with a second preset proportion from each threshold segment to obtain the physical blocks with the first proportion.
In some embodiments, the reference performance parameter includes at least one of a bit error rate, an offset voltage distribution, and a delay parameter, wherein the delay parameter includes a read delay parameter, a write delay parameter, and an erase delay parameter.
In some embodiments, the bit error rate is calculated by the following formula: RBER/(D + P), wherein RBER is the bit error rate, D is user data, and P is a check bit;
when the reference performance parameter includes the bit error rate, the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameter includes:
judging whether the bit error rate is greater than a preset threshold value or not;
if so, increasing the value of the check bit;
and adjusting the bit error rate of the residual physical block to be the bit error rate after verification.
In some embodiments, when the reference performance parameter comprises the offset voltage profile;
the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameters includes:
and adjusting the reading reference voltage of the rest physical blocks according to the offset voltage distribution.
In some embodiments, when the delay parameter includes a write delay parameter, the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameter includes:
detecting whether the reference physical block completes a write operation;
and if so, allocating the I/O of the reference physical block to the remaining physical blocks with the same write delay parameters as the reference physical block.
In a second aspect, an embodiment of the present invention provides an apparatus for optimizing a flash memory medium, where the flash memory medium includes a plurality of physical blocks, and the apparatus includes:
a selecting module, configured to select a physical block with a first ratio from the plurality of physical blocks as a reference physical block;
the erasing/writing module is used for executing erasing/writing operation of preset times on the reference physical block;
the first acquisition module is used for acquiring the reference performance parameters of the reference physical block after the erasing/writing operation is performed for the preset times;
and the parameter adjusting module is used for adjusting the performance parameters of the rest physical blocks according to the reference performance parameters.
In some embodiments, the apparatus further comprises:
the second acquisition module is used for acquiring basic performance parameters of the physical blocks;
a level dividing module, configured to divide the physical blocks into at least two reference levels according to the basic performance parameter;
then, the adjusting the performance parameter of the remaining physical block according to the reference performance parameter includes:
identifying a reference level of the reference physical block; and adjusting the performance parameters of the residual physical blocks in the same level according to the reference level and the reference performance parameters.
In some embodiments, the reference performance parameter includes at least one of a bit error rate, an offset voltage distribution, and a delay parameter, wherein the delay parameter includes a read delay parameter, a write delay parameter, and an erase delay parameter.
In some embodiments, the bit error rate is calculated by the following formula: RBER/(D + P), wherein RBER is the bit error rate, D is user data, and P is a check bit;
when the reference performance parameter includes the bit error rate, the parameter adjusting module includes:
the judging unit is used for judging whether the bit error rate is greater than a preset threshold value or not;
the check unit is used for increasing the numerical value of the check bit when the bit error rate is greater than the preset threshold value;
and the bit error rate adjusting unit is used for adjusting the bit error rate of the residual physical block to be the bit error rate after verification.
In some embodiments, when the reference performance parameter comprises the offset voltage distribution, the parameter adjustment module further comprises:
and the voltage adjusting unit is used for adjusting the reading reference voltage of the residual physical blocks according to the offset voltage distribution.
In some embodiments, when the latency parameter comprises a write latency parameter, the parameter adjustment module further comprises:
a detection unit, configured to detect whether the reference physical block completes a write operation;
an allocating unit, configured to allocate, when the write operation is completed by the reference physical block, the I/O of the reference physical block to the remaining physical blocks having the same write latency parameter as the reference physical block.
In a third aspect, an embodiment of the present invention provides a nonvolatile memory device, including:
a flash memory medium; and the number of the first and second groups,
the main controller is connected with the flash memory medium;
wherein the main controller comprises:
at least one processor; and
a buffer connected to the at least one processor; wherein the content of the first and second substances,
the cache stores instructions executable by the at least one processor to enable the at least one processor to perform the flash media optimization method as described in any one of the above.
In a fourth aspect, the embodiment of the present invention further provides a non-volatile computer-readable storage medium, where the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a non-volatile storage device, the non-volatile storage device is caused to execute the flash memory medium optimization method described in any one of the above.
The embodiment of the invention has the beneficial effects that: different from the prior art, the embodiment of the invention provides a flash memory medium optimization method and a nonvolatile memory device. The method comprises the steps of selecting a physical block with a first proportion from a plurality of physical blocks of a flash memory medium as a reference physical block, executing erasing/writing operation on the reference physical block for a preset number of times, obtaining a reference performance parameter of the reference physical block after the erasing/writing operation is executed for the preset number of times, and adjusting the performance parameter of the rest physical block according to the reference performance parameter.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of a nonvolatile memory device according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a flash memory medium according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a physical block according to an embodiment of the present invention;
FIG. 4 is a flow chart of a method for optimizing a flash memory medium according to an embodiment of the present invention;
FIG. 5 is a flowchart of a method of step S11 of FIG. 4 according to an embodiment of the present invention;
FIG. 6 is a flowchart of another method of step S11 of FIG. 4 according to an embodiment of the present invention;
FIG. 7 is a flowchart of a method of step S14 of FIG. 4 according to an embodiment of the present invention;
FIG. 8 is a flowchart of another method of step S14 of FIG. 4 according to an embodiment of the present invention;
FIG. 9 is a flowchart of another method of step S14 of FIG. 4 according to an embodiment of the present invention;
FIG. 10 is a flow chart of a method for optimizing a flash memory medium according to another embodiment of the present invention;
FIG. 11 is a schematic structural diagram of an apparatus for optimizing a flash memory medium according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an apparatus for optimizing a flash memory medium according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1 to 3, a nonvolatile memory device 100 includes a flash memory medium 10 and a main controller 20 connected to the flash memory medium 10.
The nonvolatile memory device 100 is connected with the host 200 in a wired or wireless manner to realize data interaction. The storage device of the computer is divided into a volatile storage device and a nonvolatile storage device according to the length of the data storage time, and the common nonvolatile storage device 100 includes an SSD, an NVDIMM, a 3dxpion, a solid state disk, and the like.
The Flash memory medium 10 is also called a Flash storage medium, a Flash memory, a Flash granule or a Flash, belongs to one of memory devices, and is a nonvolatile memory, and stored data of the nonvolatile memory cannot be lost in case of power failure. As shown in fig. 1, the storage unit of Flash10 is a floating gate transistor, and stores data in the form of charges by using the floating gate transistor, and how much charges are stored depends on the magnitude of the voltage applied to the floating gate transistor, and specifically, whether data is stored in the storage unit depends on whether the voltage of the stored charges is greater than the preset voltage threshold Vth.
Flash10 can be classified into SLC, MLC and TLC according to different levels of voltages of memory cells. When the memory cell of Flash10 is SLC type, a single memory cell only stores one bit of data 1 or 0, and when the voltage of the charge stored by the single memory cell is greater than a preset voltage threshold Vth, the data of the memory cell is 1; when the voltage of the charge stored in the single memory cell is less than the preset voltage threshold Vth, the data representing the memory cell is 0. Since the default data of the memory cell is 1, the data of the memory cell is 0, which means that the charge stored in the single memory cell is released, and when the charge is released to a certain extent, the voltage of the floating gate transistor is smaller than the preset voltage threshold Vth, the operation of writing data 0 is completed. When the memory cell of Flash10 is of MLC type or TLC type, a single memory cell can store multi-bit data, for example, 2-bit data, by controlling the amount of charges in the memory cell, the data is divided into a plurality of preset voltage thresholds Vth, and for write-in data, by charging, the amount of charges in the memory cell is controlled, so that the charges fall into different intervals of two adjacent preset voltage thresholds Vth, which correspondingly represent different data 00, 01, 10, 11; for reading data, the data 00, 01, 10, 11 stored in the corresponding memory cell is analyzed by acquiring the current inside the corresponding memory cell and then completing reading through a series of decoding circuits.
As shown in fig. 2, the Flash10 includes a Flash Chip0 and a Flash Chip1, and taking the Flash Chip1 as an example, the Flash Chip1 includes N Chip areas planes, where N is a positive integer greater than or equal to 2. Each tile Plane includes a plurality of physical blocks, each of which includes a plurality of pages. A common Flash10 includes 1 Flash chip, and 1 Flash chip includes 1 area Plane, and of course, in the Flash memory 10 with a larger capacity, it may include a plurality of Flash chips, and 1 Flash chip may include a plurality of area planes.
In summary, a Flash chip is composed of many physical blocks, the capacity of the physical Block is generally 128Kb, 256Kb or 512Kb, and the physical Block is the minimum unit for Flash to execute an erase operation. Each physical Block includes a plurality of pages, and each Page is used as a minimum unit of read-write operation, has a capacity of 2Kb, 4Kb or 8Kb, and can be used for sending an address corresponding to a read-write command according to a preset period.
As shown in FIG. 3, physical Block0 includes data bit P0-0, data bit P1-0, data bit P2-0 … … data bit PN-0, physical Block1 includes data bit P0-1, data bit P1-1, data bit P2-1 … … data bit PN-1, and so on. The physical blocks correspond to the same Page to form a Page stripe, and each Page stripe is provided with a check bit, such as a check bit P0-X, a check bit P1-X, and a check bit P2-X … … check bit PN-X as shown in the figure. For example, the same physical pages of physical blocks Block0, Block1 … …, Block n form page stripe 1, page stripe 1 includes data bits P1-0 of physical Block0 corresponding to the physical page, data bits P1-1 … … of physical Block1 corresponding to the physical page, and parity bits P1-X of physical Block n corresponding to the physical page.
It can be understood that data is written into each physical Block in parallel according to the sequence of page stripes, and the check bits P0-X, P1-X, P2-X … … and PN-X are respectively used for error correction by adopting a redundancy algorithm when data of the corresponding page stripes have errors.
In the present embodiment, the main controller 20 includes a Flash controller 201, a processor 202, a buffer 203, and an interface 204. In this embodiment, one processor 202 is taken as an example.
The Flash controller 201 is connected with Flash10, and the Flash controller 201 is used for accessing a Flash10 at the back end and managing various parameters and data I/O of Flash 10; or, the interface and protocol used for providing access, realize the correspondent SAS/SATAtarget agreement end or NVMe agreement end, obtain I/O order and decode and produce the internal private data result that Host sends out and wait for carrying out; or, the core processing module is used for taking charge of the FTL (Flash translation layer).
The buffer 203, which is a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules (e.g., the modules shown in fig. 11) corresponding to the flash memory medium optimization method in the embodiment of the present invention. The processor 202 implements the flash media optimization method in embodiments of the present invention by running non-volatile software programs, instructions, and modules stored in the buffer 203.
The buffer 203 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the flash medium optimizing device, and the like. In addition, the buffer 203 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the cache 203 may optionally include memory located remotely from the processor 202, which may be connected to the flash media optimization device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more modules are stored in the buffer 203, and when executed by the one or more processors 202, perform the flash media optimization method in any of the method embodiments of the present invention, e.g., perform the method steps of fig. 4-10, to implement the functions of the modules and units in fig. 11.
In summary, the general process of reading and writing data by the nonvolatile memory device 100 is as follows:
In some embodiments, the data flow when the nonvolatile memory device 100 reads and writes data is: flash10 ← → FIFO (First Input First Output, First in First out) buffer 203 in the main controller 20 ← → page buffer region of Flash Chip ← → actual physical memory location of Flash Chip.
The product can execute the method provided by the embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method. For technical details that are not described in detail in this embodiment, reference may be made to the method provided by the embodiment of the present invention.
Referring to fig. 4, a flowchart of a method for optimizing a flash memory medium according to an embodiment of the present invention is shown. As shown in fig. 4, the flash memory medium includes a plurality of physical blocks, and the flash memory medium optimization method includes:
s11: a first proportion of physical blocks from the number of physical blocks is selected as a reference physical block.
As shown in fig. 5, the selecting a physical block of a first ratio from the plurality of physical blocks as a reference physical block includes:
s111: and dividing the physical block into a plurality of number sections according to the number of the physical block.
In this embodiment, each of the physical blocks has a number. As described above, the capacity of a single physical block is generally 128Kb, 256Kb or 512Kb, and the number N of physical blocks in the flash memory medium can be obtained according to the capacity of the flash memory medium and the capacity of the single physical block, and the physical block numbers are sequentially numbered as 0, 1, 2 and 3 … … N-1, and the physical block numbers indicate the physical structure of the flash memory medium to some extent.
According to a preset division rule, the physical block is divided into a plurality of number segments, for example, according to an equal difference division rule, the physical blocks with the numbers of 0, 1, 2 and 3 … … N-1 are divided into the physical blocks with the number segments of 0-500, 501-1000 and 1001-2000 … …. In some embodiments, the number of physical blocks in the plurality of number segments may be different, and since the quality of the physical block before the number is better and the quality of the physical block after the number is worse, in order to improve the optimization efficiency of the physical block, the physical blocks numbered 0, 1, 2, and 3 … … N-1 may be divided into physical blocks numbered 0 to 499, 500 to 1499, and 1500 to 2999 … …. That is, the more the number of the physical blocks of the numbered segment after the number is increased, if the value of the first preset proportion corresponding to each numbered segment is equal, the more the number of the reference physical blocks selected from the numbered segment is compared with the number of the reference physical blocks selected from the numbered segment before the number is increased, and the more accurate the reference performance parameter after the repeated erasing and writing in advance is performed on the reference physical blocks.
S112: and respectively selecting physical blocks with a first preset proportion from each serial number section to obtain the physical blocks with the first proportion.
It should be noted that, the value of the first ratio is small, so that a small number of physical blocks obtained from a plurality of physical blocks of the flash memory medium are used as reference physical blocks, and the performance of most other physical blocks (i.e., remaining physical blocks) can be optimized. Preferably, the value of the first proportion is 0.1% -1%.
In this embodiment, the values of the first preset ratios corresponding to each number segment are equal. If the value of the first preset proportion corresponding to each number segment is 0.2%, randomly selecting 1 physical block from the physical blocks of each number segment 0-500, 501-1000, 1001-2000 … … or selecting 1 physical block according to the use parameters of the physical blocks, wherein the selected 1 physical block of each number segment 0-500, 501-1000, 1001-2000 … … is the reference physical block of the corresponding number segment. For example, if the physical block with the number 52 in the number segments 0-500 is selected, the physical block with the number 52 is a reference physical block in the physical blocks with the number segments 0-500, which is preferentially used for optimizing the performance of the remaining physical blocks in the number segments 0-500. The use parameter of the physical block may be a use frequency, a remaining service life, a last use time, and the like of the physical block.
It can be understood that, in order to select a physical block from each of the number segments to obtain the physical block of the first ratio, the value of the first preset ratio corresponding to each number segment may not be equal, and is not limited to the way that the value of the first preset ratio corresponding to each number segment is equal. For example, for the physical blocks of the number segments 0 to 500, 501 to 1000, 1001 to 2000 … … or the physical blocks of the number segments 0 to 499, 500 to 1499, 1500 to 2999 … …, the physical blocks of different proportions (e.g., the value of the first preset proportion corresponding to the number segments 0 to 500 is 0.1%, the value of the first preset proportion corresponding to the number segments 501 to 1000 is 0.21%, the value of the first preset proportion corresponding to the number segments 1001 to 2000 is 0.17%, etc.) may be respectively selected as the reference physical blocks of the corresponding number segments, so that the number of the reference physical blocks selected from the physical blocks of each number segment may be different.
In other embodiments, the physical block is divided into a plurality of number segments according to an arithmetic division rule, for example, the physical blocks with numbers of 0, 1, 2, and 3 … … N-1 are divided into physical blocks with numbers of 0 to 500, 501 to 1000, and 1001 to 2000 … …, and the value of the first preset proportion corresponding to each number segment is gradually increased as the number segment of the physical block is closer. Because the quality of the physical blocks of the more posterior numbering sections is worse and worse, the number of the reference physical blocks selected from the more posterior numbering sections can be increased by increasing the value of the first preset proportion of the more posterior numbering sections, and the accuracy of the reference performance parameters of the numbering sections can be increased by repeatedly erasing the reference physical blocks with more numbers in advance.
In some optional implementations of this embodiment, as shown in fig. 6, the selecting a physical block of a first ratio from the plurality of physical blocks as a reference physical block includes:
s113: and acquiring the original bit error rate of each physical block.
The original bit error rate is the bit error rate before ECC is used, which reflects the most original reliability state of Nand Flash, and the higher the original bit error rate is, the worse the reliability of Nand Flash is reflected. For example, data 01, 10, 11, 01 are written sequentially, and the data obtained when read are: 00. 10, 10 and 01, transmitting 8-bit data in total, and turning 2 bits to cause data transmission errors, wherein the original bit error rate is equal to (2bit/8bit) × 100% and is equal to 25%.
S114: and dividing the physical blocks into physical blocks with a plurality of threshold sections according to the original bit error rate.
The flash memory medium has an original bit error rate index before the flash memory medium leaves a factory, namely, each physical block has a corresponding original bit error rate. In this embodiment, the dividing the physical blocks into physical blocks of threshold segments according to the raw bit error rate includes: sequencing the original bit error rate from large to small; and dividing the original bit error rate which is sequenced from large to small into a plurality of threshold sections according to at least one error rate threshold value.
Taking 10 physical blocks as an example, the corresponding original bit error rates thereof are ordered from large to small as follows: 0.85, 0.71, 0.69, 0.36, 0.26, 0.25, 0.18, 0.15, 0.11 and 0.08, and setting the bit error rate threshold value as follows: 0.1, 0.3 and 0.8, then the original bit error rate 0.08 is less than the bit error rate threshold 0.1, the corresponding physical block is divided into the threshold section with the original bit error rate less than 0.1, the original bit error rates 0.11, 0.15, 0.18, 0.25 and 0.26 are greater than the bit error rate threshold 0.1 and less than the bit error rate threshold 0.3, the corresponding physical block is divided into the threshold section with the original bit error rate greater than 0.1 and less than 0.3, the original bit error rates 0.71, 0.69 and 0.36 are greater than the bit error rate threshold 0.3 and less than the bit error rate threshold 0.8, the corresponding physical block is divided into the threshold section with the original bit error rate greater than 0.3 and less than 0.8, the original bit error rate 0.85 is greater than the bit error rate threshold 0.8, and the corresponding physical block is divided into the threshold section with the original bit error rate greater than 0.8.
It can be understood that when the flash memory medium is not used or is used for a short time, the original bit error rate difference corresponding to each threshold segment inside the flash memory medium is not large.
S115: and respectively selecting physical blocks with a second preset proportion from each threshold segment to obtain the physical blocks with the first proportion.
Generally, the number of physical blocks included in each of the threshold segments is not equal, and to obtain a first proportion of physical blocks from a plurality of physical blocks, the same proportion of physical blocks may be selected from each of the threshold segments, or a respective proportion of physical blocks may be selected from each of the threshold segments, for example, 0.1% of physical blocks from the first threshold segment, 0.15% of physical blocks from the second threshold segment, 0.3% of physical blocks from the second threshold segment, etc. are selected from each of the threshold segments, i.e. the value of the second preset proportion is not uniquely determined with respect to each of the threshold segments.
Preferably, the number of the physical blocks of the threshold segment with the higher original bit error rate may be allocated more, and if the values of the second preset proportion corresponding to each threshold segment are equal, the number of the reference physical blocks selected from the threshold segment is larger than the number of the reference physical blocks selected from the threshold segment with the earlier number, and the reference performance parameter after the threshold segment is repeatedly erased in advance is more accurate.
In other embodiments, the physical block is divided into a plurality of threshold segments according to an arithmetic division rule, that is, the number of physical blocks in each threshold segment is equal, and as the original bit error rate of the threshold segment of the physical block is higher and higher, the value of the second preset proportion corresponding to each threshold segment is gradually increased. Because the quality of the physical blocks of the threshold segment with higher original bit error rate is worse and worse, the number of the reference physical blocks selected from the threshold segment with higher original bit error rate can be increased by increasing the value of the second preset proportion of the threshold segment with higher original bit error rate, so that the accuracy of the reference performance parameters of the threshold segment can be increased by repeatedly erasing the reference physical blocks with more number in advance.
S12: and executing erasing/writing operation on the reference physical block for preset times.
In this embodiment, the FTL performs erase/write operations on the reference physical block by a preset number of times through FTL algorithm assignment.
As mentioned above, the unit of reading and writing the flash memory medium is Page, the size of Page is generally 4KB or 8KB, but the reading and writing of data by the operating system is performed according to the sector size of the hard disk drive, which is 512Byte bytes, and the flash memory medium is erased by physical blocks, and cannot be written without erasing, which results in that the file system currently used by the operating system cannot manage the nonvolatile storage device at all, and needs to replace more advanced and complex files to solve the problem, which results in increasing the burden of the operating system. In order not to burden the operating system, the non-volatile storage device virtualizes the operation of the flash media as a disk independent sector operation in a software manner, which is referred to as an FTL, which exists between the file system and the flash media.
The FTL algorithm is a mapping from LBA (Logical Block Address) to PBA (physical Block Address). When the file system sends an instruction to write or update a specific logical page, the FTL actually writes the data into a different free physical page and updates the mapping table (LBA and PBA associated data), and marks "old data" contained in this page as "invalid" (the updated data has been written into a new PBA, and the data of the old address naturally fails). Therefore, the performance of FTL switching directly affects the performance of the nonvolatile memory device, and the FTL algorithm is also one of the determining factors affecting the lifetime and stability of the nonvolatile memory device. Preferably, the performing the erase/write operation on the reference physical block for the preset number of times includes: and reducing the preset times according to the accumulated erasing/writing times of the reference physical block.
The bit error rate increases and the life of the flash memory medium decreases as the number of erasing/writing operations increases, so that different preset times of erasing/writing operations are performed on the reference physical block in different use stages of the flash memory medium. For example, in the initial use stage, the flash memory medium is not subjected to repeated erasing and writing, the performance is good, and the preset times of erasing/writing operation on the selected reference physical block is 500 times; after the time T1 is used, increasing the accumulated erasing/writing operation times of the reference physical block, reducing the preset times according to the accumulated erasing/writing operation times, and executing the preset times of 300 erasing/writing operations on the selected reference physical block; and after the time T2 is used, the accumulated erasing/writing operation times of the reference physical blocks continue to increase, the preset times are reduced according to the accumulated erasing/writing operation times, and the preset times of erasing/writing operation on the selected reference physical blocks are executed for 100 times.
In some embodiments, the performing a preset number of erase/write operations on the reference physical block includes: allocating a reference physical block and a residual physical block to perform erasing/writing operations for a corresponding number of times, wherein the erasing/writing operations on the reference physical block precede the erasing/writing operations on the residual physical block; adjusting the times of erasing/writing operations performed on the reference physical block and the remaining physical blocks; judging whether the difference value of the times of executing erasing/writing operation of the reference physical block and the residual physical blocks is less than a preset time threshold value or not; if yes, go to step S13; if not, continuing to allocate the reference physical block and the residual physical blocks to execute the corresponding times of erasing/writing operations.
For example, in the initial use stage, the flash memory medium is not subjected to repeated erasing and writing, the performance is good, the selected reference physical block is distributed to execute 500 erasing/writing operations, the rest physical blocks execute 200 erasing/writing operations, and the difference value of the erasing/writing operations executed by the reference physical block and the rest physical blocks is 300 times; after using T1 time, allocating the selected reference physical block to execute 400 erasing/writing operations, and the rest physical blocks to execute 200 erasing/writing operations, wherein the difference value of the erasing/writing operations executed by the reference physical block and the rest physical blocks is 200 times; after using T2 time, allocating the selected reference physical block to execute 110 erasing/writing operations, and the rest physical blocks to execute 100 erasing/writing operations, wherein the difference of the erasing/writing operations executed by the reference physical block and the rest physical blocks is 10 times; if the preset number threshold is 20, the difference between the numbers of times of performing the erase/write operations on the reference physical block and the remaining physical blocks is smaller than the preset number threshold, and the process proceeds to step S13.
It should be noted that, compared with performing the erase/write operation on the remaining physical blocks for a preset number of times before performing the erase/write operation on the remaining physical blocks, that is, performing the erase/write operation on the reference physical blocks repeatedly in advance, the erase/write operation is performed on the remaining physical blocks.
S13: and acquiring the reference performance parameters of the reference physical block after the erasing/writing operation is performed for the preset times.
In this embodiment, the reference performance parameter includes at least one of a bit error rate, an offset voltage distribution, and a delay parameter, where the delay parameter includes a read delay parameter, a write delay parameter, and an erase delay parameter.
And when the reference performance parameter comprises the bit error rate, acquiring the bit error rate of the reference physical block after executing the erasing/writing operation for the preset times according to the cumulative erasing/writing operation times of the reference physical block and a relation curve graph of the bit error rate and the cumulative erasing/writing operation times of the reference physical block. When the reference performance parameters comprise offset voltage distribution, calculating a difference value between the current charge amount of the storage unit corresponding to each reference physical block after executing erasing/writing operation for a preset number of times and the reference charge amount of the storage unit corresponding to each reference physical block; and acquiring offset voltage distribution of the reference physical blocks after executing erasing/writing operation for preset times according to the reference charge quantity of the storage unit corresponding to each reference physical block, the reference voltage distribution and the difference value. When the reference performance parameters comprise time delay parameters, recording the time of receiving a read operation instruction, a write operation instruction or an erase operation instruction by the reference physical block after executing the preset times of erase/write operations and the time of starting executing the read operation, the write operation or the erase operation by the reference physical block according to a time node trigger, and calculating the read time delay, the write time delay and the erase time delay of the reference physical block after executing the preset times of erase/write operations.
It should be understood that the specific implementation provided in this embodiment is only for explaining the present invention, and is not used to limit the manner of obtaining the reference performance parameter of the reference physical block after performing the erase/write operation for the preset number of times.
S14: and adjusting the performance parameters of the rest physical blocks according to the reference performance parameters.
As shown in fig. 7, the bit error rate is calculated by the following formula: RBER/(D + P), wherein RBER is the bit error rate, D is user data, and P is a check bit; when the reference performance parameter includes the bit error rate, the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameter includes:
s141: and judging whether the bit error rate is greater than a preset threshold value.
S142: and if so, increasing the value of the check bit.
S143: and adjusting the bit error rate of the residual physical block to be the bit error rate after verification.
If the bit error rate of the obtained reference physical block after the erasing/writing operation is performed for the preset times is high, the quality of the flash memory medium is low, and the phenomenon of bit inversion is easy to occur in the transmission process, so that the reliability and the correctness of data transmission are reduced. Since the bit error rate increases with the increase of the number of erasing/writing operations, if the remaining physical blocks are corrected with their original bit error rates, the transmission data cannot be reliably restored. And providing the reference performance parameters of the reference physical block after the erasing/writing operation is performed for the preset times to the residual physical block to serve as the bit error rate parameters of the residual physical block, so that the performance of the residual physical block is improved, and the problem of poor flash memory medium quality caused by the fact that the residual physical block uses the original bit error rate for error correction all the time is solved.
Furthermore, according to one of the calculation methods of the bit error rate, RBER is D/(D + P), wherein RBER is the bit error rate, D is user data, and P is a check bit, the value of the check bit P is increased, the bit error rate RBER of the reference physical block after executing the erasing/writing operation for the preset number of times can be reduced, and the reduced bit error rate RBER is provided for the remaining physical block, so that the remaining physical block can reliably correct the transmission data according to the bit error rate RBER, and the correctness of the reading and writing data of the flash memory medium is improved.
As shown in fig. 8, when the reference performance parameter includes the offset voltage distribution, the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameter includes:
s144: and adjusting the reading reference voltage of the rest physical blocks according to the offset voltage distribution.
For example, a certain memory cell corresponds to reference voltage 1, reference voltage 2 and reference voltage 3, the written data is 01, the voltage value is between [ reference voltage 2, reference voltage 3], then if the nonvolatile memory device is powered on occasionally, and the memory cell is not read or written during the power-on period, electrons on the memory cell will leak gradually, the voltage will decrease gradually, when the change lasts long enough, the voltage of the memory cell will certainly be less than reference voltage 2, when reading data, since the voltage value of the memory cell is between [ reference voltage 1, reference voltage 2], it is determined that the data stored in the memory cell is 10, and thus a data error occurs.
The offset voltage distribution is a plurality of reference voltages of the reference physical block after the erasing/writing operation is performed for a preset number of times, and specifically includes: although the nonvolatile memory device is powered on occasionally and the memory cell is not read or written during power-on, the reference voltage 1a, the reference voltage 2a and the reference voltage 3a are repeatedly erased in advance to obtain offset voltage distribution and provide the offset voltage distribution to the remaining physical blocks as read reference voltages thereof, so that when data is read, the voltage value of the memory cell is still between [ the reference voltage 2a and the reference voltage 3a ], the data stored in the memory cell is judged to be 01, and the data is read correctly, thereby improving the accuracy of reading data of the remaining physical blocks and optimizing the performance of the remaining physical blocks.
As shown in fig. 9, when the delay parameter includes a write delay parameter, the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameter includes:
s145: detecting whether the reference physical block completes a write operation.
S146: and if so, allocating the I/O of the reference physical block to the remaining physical blocks with the same write delay parameters as the reference physical block.
After obtaining the basic performance parameters of the physical blocks and dividing the physical blocks into at least two reference levels according to the basic performance parameters (please refer to the method embodiment described below), the write delay parameters of the reference physical blocks after performing erase/write operations for a preset number of times are obtained and provided to the remaining physical blocks of the same level. The CPU of the terminal equipment performs write I/O scheduling on the reference physical block through the write delay parameter, and when the reference physical block of the I/O port completes write operation, the I/O port is allocated to the rest physical blocks with the same write delay parameter, so that the physical blocks are prevented from completing the idle task in advance or not completing the task and allocating a new task, and the service quality of the system can be improved.
According to the flash memory medium optimization method provided by the embodiment of the invention, the physical blocks with the first proportion are selected from the plurality of physical blocks of the flash memory medium to be used as the reference physical blocks, the erasing/writing operation is performed on the reference physical blocks for the preset times, the reference performance parameters of the reference physical blocks after the erasing/writing operation is performed for the preset times are obtained, and the performance parameters of the rest physical blocks are adjusted according to the reference performance parameters.
Referring to fig. 10, a flowchart of a method for optimizing a flash memory medium according to another embodiment of the present invention is shown. Please refer to the above embodiments where the same as the above method embodiment, which is not described herein, as shown in fig. 10, the difference from the above method embodiment is that after selecting a physical block with a first ratio from the plurality of physical blocks as a reference physical block, the method for optimizing a flash memory medium further includes:
s21: and acquiring basic performance parameters of the plurality of physical blocks.
In this embodiment, the basic performance parameters include a raw bit error rate, a reference voltage distribution, and a delay parameter.
S22: dividing the physical blocks into at least two reference levels according to the basic performance parameter.
For example, basic performance parameters of the reference physical block are obtained, and the reference physical block is classified according to the original bit error rate, the reference voltage distribution and the delay parameters of the reference physical block. Specifically, a reference physical block with low original bit error rate, reference voltage distribution in a standard range and low delay parameter is set as the highest level and is marked as a strong physical block; setting a reference physical block with higher original bit error rate, longer reference voltage distribution deviation standard range and higher delay parameter as a medium level, and marking the reference physical block as a mid physical block; and setting a reference physical block with high original bit error rate, long reference voltage distribution deviation standard range and high delay parameter as a lowest level, and marking the reference physical block as a weak physical block. Similarly, according to the above classification method, the remaining physical blocks are set to different levels and identified as strong physical blocks, mid physical blocks, and weak physical blocks.
In this embodiment, the adjusting the performance parameter of the remaining physical block according to the reference performance parameter includes:
s147: identifying a reference level of the reference physical block.
S148: and adjusting the performance parameters of the residual physical blocks in the same level according to the reference level and the reference performance parameters.
Specifically, after the erasing/writing operation is performed on the reference physical block for the preset number of times, the reference performance parameter of the reference physical block identified as the strong physical block is provided to the remaining physical blocks also identified as the strong physical block; providing the reference performance parameter of the reference physical block identified as mid physical block to the remaining physical blocks also identified as mid physical blocks; the reference performance parameters of the reference physical blocks identified as the weak physical blocks are provided to the remaining physical blocks also identified as the weak physical blocks.
The embodiment of the invention provides a flash memory medium optimization method, which comprises the steps of selecting a physical block with a first proportion from a plurality of physical blocks of a flash memory medium as a reference physical block, executing erasing/writing operation on the reference physical block for preset times, obtaining reference performance parameters of the reference physical block after executing the erasing/writing operation for the preset times, and adjusting the performance parameters of the rest physical blocks according to the reference performance parameters.
Fig. 11 is a schematic structural diagram of an optimization apparatus for flash memory media according to an embodiment of the present invention. The flash media optimization apparatus 300 includes a selecting module 301, an erasing/writing module 302, a first obtaining module 303, and a parameter adjusting module 304.
The selecting module 301 is configured to select a first ratio of physical blocks from the plurality of physical blocks as a reference physical block. The erase/write module 302 is configured to perform erase/write operations on the reference physical block for a preset number of times. The first obtaining module 303 is configured to obtain a reference performance parameter of the reference physical block after performing erase/write operations for a preset number of times. The parameter adjusting module 304 is configured to adjust the performance parameters of the remaining physical blocks according to the reference performance parameter.
The reference performance parameter comprises at least one of a bit error rate, an offset voltage distribution and a delay parameter, wherein the delay parameter comprises a read delay parameter, a write delay parameter and an erase delay parameter.
The bit error rate calculation formula is as follows: RBER/(D + P), wherein RBER is the bit error rate, D is user data, and P is a check bit; when the reference performance parameter includes the bit error rate, the parameter adjusting module 304 includes a determining unit 3041, a verifying unit 3042, and an error rate adjusting unit 3043.
The determining unit 3041 is configured to determine whether the bit error rate is greater than a preset threshold. The check unit 3042 is configured to increase the value of the check bit when the bit error rate is greater than the preset threshold. The bit error rate adjusting unit 3043 is configured to adjust the bit error rate of the remaining physical block to a checked bit error rate.
When the reference performance parameter includes the offset voltage distribution, the parameter adjusting module 304 further includes a voltage adjusting unit 3044.
The voltage adjusting unit 3044 is configured to adjust the read reference voltages of the remaining physical blocks according to the offset voltage distribution.
When the delay parameter includes a write delay parameter, the parameter adjusting module 304 further includes a detecting unit 3045 and an allocating unit 3046.
The detecting unit 3045 is configured to detect whether the reference physical block completes a write operation. The allocating unit 3046 is configured to, when the reference physical block completes the write operation, allocate I/O of the reference physical block to the remaining physical blocks having the same write latency parameter as the reference physical block.
Fig. 12 is a schematic structural diagram of an optimized flash memory device according to another embodiment of the present invention. As shown in fig. 12, the flash memory medium optimizing device 400 includes the flash memory medium optimizing device 300 according to the above device embodiments, and please refer to the above embodiments for the same parts, which are not described in detail herein. The difference is that the flash media optimizing device 400 further comprises a second obtaining module 401 and a ranking module 402.
The second obtaining module 401 is configured to obtain basic performance parameters of the physical blocks.
The level dividing module 402 is configured to divide the physical blocks into at least two reference levels according to the basic performance parameter.
In this embodiment, the parameter adjusting module 304 is specifically configured to: identifying a reference level of the reference physical block; and adjusting the performance parameters of the residual physical blocks in the same level according to the reference level and the reference performance parameters.
It should be noted that, for the information interaction, execution process and other contents between the modules and units in the apparatus, the specific contents may refer to the description in the embodiment of the method of the present invention because the same concept is based on the embodiment of the method of the present invention, and are not described herein again.
The embodiment of the invention provides a flash memory medium optimizing device, which selects a physical block with a first proportion from a plurality of physical blocks of a flash memory medium as a reference physical block, executes erasing/writing operations for a preset number of times on the reference physical block, acquires a reference performance parameter of the reference physical block after executing the erasing/writing operations for the preset number of times, and adjusts the performance parameter of the rest physical block according to the reference performance parameter.
The above-described embodiments of the apparatus or device are merely illustrative, wherein the unit modules described as separate parts may or may not be physically separate, and the parts displayed as module units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
Through the above description of the embodiments, it is clear to those skilled in the art that the flash media optimization apparatus can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. Moreover, since the concept of the flash memory medium optimizing device is the same as that of the flash memory medium optimizing method described in each embodiment, the content of each embodiment may be referred to in the embodiment of the flash memory medium optimizing device under the condition that the content does not conflict with each other, and details are not described herein.
Embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer-executable instructions for execution by one or more processors, e.g., to perform the method steps of fig. 4-10 described above, to implement the functions of the modules and units of fig. 12.
Embodiments of the present invention provide a computer program product comprising a computer program stored on a non-volatile computer-readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform a flash media optimization method in any of the above-described method embodiments, e.g., to perform the method steps of fig. 4-10 described above, to implement the functions of the modules and units in fig. 12.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A method for optimizing a flash memory medium, the flash memory medium comprising a plurality of physical blocks, the method comprising:
selecting a physical block with a first proportion from the plurality of physical blocks as a reference physical block;
performing erase/write operations for a preset number of times on the reference physical block;
acquiring a reference performance parameter of a reference physical block after executing erasing/writing operation for a preset number of times;
adjusting the performance parameters of the rest physical blocks according to the reference performance parameters;
the selecting a first proportion of physical blocks from the plurality of physical blocks as a reference physical block comprises:
acquiring the original bit error rate of each physical block;
dividing the physical blocks into physical blocks with a plurality of threshold sections according to the original bit error rate;
and respectively selecting physical blocks with a second preset proportion from each threshold segment to obtain the physical blocks with the first proportion.
2. The method of claim 1, wherein after selecting a first proportion of the physical blocks from the plurality of physical blocks as reference physical blocks, the method further comprises:
acquiring basic performance parameters of the physical blocks;
dividing the physical blocks into at least two reference levels according to the basic performance parameters;
then, the adjusting the performance parameter of the remaining physical block according to the reference performance parameter includes:
identifying a reference level of the reference physical block;
and adjusting the performance parameters of the residual physical blocks in the same level according to the reference level and the reference performance parameters.
3. The method of claim 2, wherein the base performance parameters include raw bit error rate, reference voltage distribution, and delay parameters.
4. The method of claim 3, wherein each of the physical blocks has a number;
the selecting a first proportion of physical blocks from the plurality of physical blocks as a reference physical block comprises:
dividing the physical block into a plurality of number sections according to the number of the physical block;
and respectively selecting physical blocks with a first preset proportion from each serial number section to obtain the physical blocks with the first proportion.
5. The method of any of claims 1-4, wherein the reference performance parameter comprises at least one of a bit error rate, an offset voltage profile, and a delay parameter, wherein the delay parameter comprises a read delay parameter, a write delay parameter, and an erase delay parameter.
6. The method of claim 5, wherein the bit error rate is calculated by the formula: RBER/(D + P), wherein RBER is the bit error rate, D is user data, and P is a check bit;
when the reference performance parameter includes the bit error rate, the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameter includes:
judging whether the bit error rate is greater than a preset threshold value or not;
if so, increasing the value of the check bit;
and adjusting the bit error rate of the residual physical block to be the bit error rate after verification.
7. The method of claim 5, wherein when the reference performance parameter comprises the offset voltage distribution, the adjusting the performance parameter of the remaining physical blocks according to the reference performance parameter comprises:
and adjusting the reading reference voltage of the rest physical blocks according to the offset voltage distribution.
8. The method of claim 5, wherein when the delay parameter comprises a write delay parameter, the adjusting the performance parameters of the remaining physical blocks according to the reference performance parameter comprises:
detecting whether the reference physical block completes a write operation;
and if so, allocating the I/O of the reference physical block to the remaining physical blocks with the same write delay parameters as the reference physical block.
9. A non-volatile storage device, comprising:
a flash memory medium; and the number of the first and second groups,
the main controller is connected with the flash memory medium;
wherein the main controller comprises:
at least one processor; and
a buffer connected to the at least one processor; wherein the content of the first and second substances,
the cache stores instructions executable by the at least one processor to enable the at least one processor to perform the flash media optimization method of any one of claims 1-8.
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