CN110687746B - Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device - Google Patents
Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device Download PDFInfo
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- CN110687746B CN110687746B CN201911101708.5A CN201911101708A CN110687746B CN 110687746 B CN110687746 B CN 110687746B CN 201911101708 A CN201911101708 A CN 201911101708A CN 110687746 B CN110687746 B CN 110687746B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 42
- 230000008569 process Effects 0.000 claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 238000012360 testing method Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000012546 transfer Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 238000012795 verification Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012634 optical imaging Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention provides an exposure auxiliary graph, a mask plate and a manufacturing method of a semiconductor device. The technical scheme of the invention increases the process window, so that the main pattern on the mask can be completely transferred to the wafer.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to an exposure auxiliary graph, a mask plate and a manufacturing method of a semiconductor device.
Background
The photoetching technology is a vital technology in the semiconductor manufacturing technology, and can realize the transfer of a pattern from a mask plate to the surface of a silicon wafer to form a semiconductor device meeting the design requirement. However, the process of transferring a pattern from a reticle to a silicon wafer surface by photolithography has more or less distortion, and the distortion becomes more and more severe especially as the line width is continuously reduced. Phenomena such as Corner Rounding (Corner Rounding) or Line End Shortening (OPE) are caused by Optical Proximity Effect (OPE) caused by nonlinear filtering of an Optical imaging system. In order to eliminate the influence of the Optical Proximity effect, the exposure pattern on the actual mask is different from the desired lithography pattern, and the exposure pattern needs to be processed by Optical Proximity Correction (OPC); in addition, as the line width is continuously reduced, while the exposure pattern on the mask is subjected to the optical proximity correction process, a Sub-resolution auxiliary pattern (SRAF) needs to be arranged around the exposure pattern. The auxiliary patterns are only arranged on the mask plate, and are not transferred to the silicon wafer after actual exposure, so that the auxiliary patterns only have the functions of increasing the Depth of Focus (DOF for short) of adjacent exposure patterns and increasing a process window.
Then, the specific setting of the auxiliary graphics as the additional non-transferred graphics is important. At present, the auxiliary pattern mainly comprises independent lines or holes, and the size of the obtained process window is small, so that the process requirements of smaller and smaller line widths cannot be met. As shown in fig. 1, an auxiliary pattern 12 is disposed around an exposed main pattern 11 on a mask 10, and the auxiliary pattern 12 includes a plurality of lines, but the lines are independent from each other, so that a depth of focus during exposure is small, a process window is small, and the main pattern 11 on the mask 10 cannot be completely transferred onto a wafer.
Therefore, how to optimize the assistant feature to increase the process window is a problem that needs to be solved.
Disclosure of Invention
The invention aims to provide an exposure auxiliary graph, a mask plate and a manufacturing method of a semiconductor device, so that a process window is enlarged, and a main graph on the mask plate can be completely transferred onto a wafer.
In order to achieve the above object, the present invention provides an exposure auxiliary pattern for completely transferring a main pattern on a mask onto a wafer, comprising at least one circle of auxiliary patterns disposed around the main pattern, wherein the shape of at least one circle of auxiliary patterns closest to the main pattern corresponds to the aperture shape during exposure.
Optionally, at least one ring of auxiliary patterns closest to the main pattern forms a closed loop or a non-closed loop surrounding the main pattern.
Optionally, when the one circle of auxiliary patterns forms a non-closed loop, the one circle of auxiliary patterns includes at least one independent zigzag pattern therein.
Optionally, the circle of auxiliary patterns includes at least two independent zigzag patterns, and a distance between adjacent ends of adjacent zigzag patterns is less than 0.1 μm.
Optionally, each independent zigzag-shaped pattern includes a flat portion and a folded portion located at two ends of the flat portion and folded relative to the flat portion, and an included angle between the folded portion and the flat portion is an obtuse angle.
Optionally, the exposure auxiliary pattern includes at least two circles of auxiliary patterns arranged around the main pattern, and the auxiliary patterns of the other circles except the circle of auxiliary pattern closest to the main pattern include: a plurality of independent rectangular block patterns disposed around a circle of the auxiliary patterns closest to the main pattern.
Optionally, the width of the auxiliary pattern of each turn is smaller than the width of the main pattern.
The invention also provides a mask which is characterized by comprising the following components: the exposure auxiliary graph provided by the invention surrounds the main graph.
Optionally, the main graphic comprises at least one independent graphic.
The invention also provides a manufacturing method of the mask, which comprises the following steps:
providing a main pattern of the mask plate;
forming the exposure auxiliary pattern provided by the present invention disposed around the main pattern;
simulating a process window using the main pattern and the exposure auxiliary pattern disposed around the main pattern to optimize the main pattern and the exposure auxiliary pattern disposed around the main pattern to meet requirements;
preparing a test mask by using the main pattern optimized to meet the requirement and the exposure auxiliary pattern arranged around the main pattern;
and carrying out process verification on the test mask at the chip end to obtain the mask meeting the production requirement.
The present invention also provides a method for manufacturing a semiconductor device, comprising:
providing a wafer, wherein the surface of the wafer is covered with a photoresist layer;
photoetching the photoresist layer by using the mask provided by the invention so as to completely transfer the main pattern on the mask to the photoresist layer to form a patterned photoresist layer;
etching the wafer by taking the patterned photoresist layer as a mask so as to completely transfer the main pattern on the mask onto the wafer; and the number of the first and second groups,
and removing the patterned photoresist layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the exposure auxiliary graph comprises at least one circle of auxiliary graphs arranged around the main graph, and the shape of the circle of auxiliary graphs at least closest to the main graph corresponds to the shape of the aperture during exposure, so that the process window is enlarged, and the main graph on the mask can be completely transferred to a wafer.
2. The mask plate comprises the main pattern and the exposure auxiliary pattern provided by the invention, and the exposure auxiliary pattern is arranged around the main pattern, so that a process window is enlarged, the main pattern can be completely transferred onto a wafer, and the mask plate meets the production requirement.
3. According to the manufacturing method of the mask, the main pattern of the mask is provided, and the exposure auxiliary pattern provided by the invention and arranged around the main pattern is formed, so that a process window is enlarged; further, a process window is simulated by utilizing the main pattern and the exposure auxiliary pattern arranged around the main pattern so as to optimize the main pattern and the exposure auxiliary pattern arranged around the main pattern to meet the requirements, a test mask is prepared by utilizing the main pattern optimized to meet the requirements and the exposure auxiliary pattern arranged around the main pattern, and the process of the test mask is verified at the chip end, so that the manufactured mask meets the production requirements.
4. According to the manufacturing method of the semiconductor device, the mask is adopted to carry out photoetching on the photoresist layer on the surface of the wafer, so that the main pattern on the mask is completely transferred onto the photoresist layer to form the patterned photoresist layer; and then, taking the patterned photoresist layer as a mask, and etching the wafer to completely transfer the main pattern on the mask plate onto the wafer, so that the formed semiconductor device meets the specification requirement.
Drawings
FIG. 1 is a schematic illustration of an auxiliary graphic;
FIGS. 2a 2b are schematic views of an exposure assistant feature according to an embodiment of the present invention.
Wherein the reference numerals of figures 1 to 2b are as follows:
10-mask plate; 11-main pattern; 12-auxiliary graphics; 20-mask plate; 21-main pattern; 22-auxiliary graphics; 221-a first graphic; 222-second graphic.
Detailed Description
In order to make the objects, advantages and features of the present invention more clear, the exposure assist pattern, the mask blank and the method for manufacturing the semiconductor device according to the present invention are further described in detail with reference to fig. 1 to 2 b. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2a to 2b, as can be seen from fig. 2a to 2b, a main pattern 21 and an exposure auxiliary pattern are disposed on the mask 20, the exposure auxiliary pattern includes at least one ring of auxiliary patterns 22 disposed around the main pattern 21, and a shape of at least one ring of auxiliary patterns 22 closest to the main pattern 21 corresponds to a shape of an aperture during exposure.
The exposure assist pattern provided in the present embodiment is described in detail below with reference to fig. 2a to 2 b:
the exposure auxiliary pattern comprises at least one circle of auxiliary patterns 22 arranged around the main pattern 21, and the shape of at least one circle of auxiliary patterns 22 closest to the main pattern 21 corresponds to the aperture shape during exposure. The main pattern 21 is transferred to a photoresist layer covering the surface of the wafer after photoetching to form a patterned photoresist layer; and, after etching the wafer with the patterned photoresist layer as a mask, the main pattern 21 is transferred onto the wafer to form a desired semiconductor structure on the wafer (e.g., forming a gate, a metal interconnection line, or a conductive contact plug). In the exposure process, the auxiliary pattern 22 utilizes the phenomenon of interference and diffraction of exposure light, so that the contrast of the exposed main pattern 21 is enhanced, the process window is enlarged, and the accuracy of the boundary morphology of the exposed main pattern 21 is improved.
The width of the auxiliary pattern 22 of each circle is smaller than the width of the main pattern 21, the width of the main pattern 21 is larger than the resolution critical value of the exposure process, the width of the auxiliary pattern 22 of each circle is smaller than the resolution critical value of the exposure process, so that when the main pattern 21 is exposed, the auxiliary pattern 22 cannot be exposed, and the auxiliary pattern 22 cannot be transferred to the photoresist layer covering the surface of the wafer after photoetching.
Since the shape of the circle of auxiliary patterns 22 at least closest to the main pattern 21 corresponds to the shape of the aperture at the time of exposure, and the shape of the aperture at the time of exposure is generally a circular shape, such as a pentagonal, hexagonal, octagonal, etc., the circle of auxiliary patterns 22 at least closest to the main pattern 21 forms a closed ring or a non-closed ring surrounding the main pattern 21, so that the enhancement effect of the exposure contrast of the auxiliary patterns 22 on the main pattern 21 at the time of exposure is improved, the process window is further increased, and the main pattern 21 can be completely transferred onto the photoresist layer and the wafer. The shapes of the closed loop and the non-closed loop may include annular shapes such as pentagon, hexagon, octagon, and the like corresponding to the aperture shape at the time of exposure, and it should be noted that the aperture shape at the time of exposure and the shape of the auxiliary pattern 22 are not limited to the above-mentioned shapes.
When the loop of auxiliary patterns 22 forms a non-closed loop shape, at least one independent zigzag pattern is included in the loop of auxiliary patterns 22. That is, when the number of turns of the auxiliary pattern 22 is one turn, the auxiliary pattern 22 of the one turn includes at least one independent zigzag pattern; when the number of turns of the auxiliary pattern 22 is at least two turns, the auxiliary pattern 22 of any one turn includes at least one independent zigzag pattern. And, when the one-turn (i.e., the same turn) auxiliary pattern 22 is an independent zigzag pattern, the distance between both ends of the zigzag pattern is less than 0.1 μm; when at least two independent zigzag patterns are included in the one turn (i.e. the same turn) of the auxiliary patterns 22, the distance between the adjacent ends of the adjacent zigzag patterns (distance L shown in fig. 2 a) is less than 0.1 μm, so that the shape of the auxiliary patterns 22 corresponds to the shape of the aperture as much as possible, and thus the auxiliary patterns 22 can enhance the exposure contrast to the main patterns 21 as much as possible during exposure, and the process window is increased. It should be noted that the distance between two ends of the zigzag pattern and the distance between adjacent ends of the adjacent zigzag patterns are not limited to the above ranges, and can be adjusted according to the size of the required process window.
Each of the independent polygonal line-shaped patterns includes a flat portion and a folded portion located at both ends of the flat portion and folded with respect to the flat portion, and the angle between the folded portion and the flat portion is an obtuse angle, as shown in fig. 2a, and the angle between the folded portion and the flat portion is an obtuse angle α, so that the independent polygonal line-shaped pattern surrounds the main pattern 21.
When the exposure auxiliary pattern includes at least two circles of auxiliary patterns 22 arranged around the main pattern 21, the auxiliary patterns 22 of the other circles except for one circle of auxiliary patterns 22 closest to the main pattern 21 include: a plurality of independent rectangular block patterns disposed around a circle of the auxiliary patterns 22 closest to the main pattern 21. As shown in fig. 2a, the exposure auxiliary pattern includes two circles of auxiliary patterns 22 arranged around the main pattern 21, one circle of auxiliary patterns 22 closest to the main pattern 21 is a first pattern 221, one circle of auxiliary patterns 22 arranged around the first pattern 221 is a second pattern 222, the first pattern 221 is in a non-closed ring shape, the second pattern 222 includes a plurality of independent rectangular block patterns, a distance between adjacent ends of the adjacent rectangular block patterns is large, and an interference diffraction phenomenon during exposure is not obvious from the first pattern 221. As shown in fig. 2b, the second pattern 222 may also be a closed ring or a non-closed ring having the same or similar shape as the first pattern 221, and compared to the second pattern 222 in fig. 2a, under the combined action of the second pattern 222 and the first pattern 221 in fig. 2b, the interference diffraction phenomenon during exposure is more obvious, the enhancement effect on the contrast of the exposed main pattern 21 is better, and the formed process window is larger, so that the main pattern 22 can be more completely transferred onto the photoresist layer and the wafer.
In addition, the number of laps of the auxiliary patterns 22 is mainly determined by the distance between the adjacent main patterns 21, and the larger the distance between the adjacent main patterns 21 is, the more the number of laps of the auxiliary patterns 22 may be. Also, the distance between adjacent turns and the width of the auxiliary pattern 22 per turn also have an influence on the number of turns of the auxiliary pattern 22.
In summary, the exposure auxiliary pattern provided by the present invention is used for completely transferring the main pattern on the mask onto the wafer, and includes at least one circle of auxiliary patterns arranged around the main pattern, and the shape of at least one circle of auxiliary patterns closest to the main pattern corresponds to the aperture shape during exposure. The exposure auxiliary pattern of the invention enlarges the process window, thereby completely transferring the main pattern on the mask plate to the wafer.
An embodiment of the present invention provides a mask, including: the exposure auxiliary graph provided by the invention is arranged around the main graph. The main pattern may include at least one independent pattern, and the shape of the independent pattern may be defined according to a desired semiconductor structure to be formed on a wafer (e.g., forming a gate electrode, a metal interconnection line, or a conductive contact plug, etc.). When the main pattern includes at least two independent patterns, a distance between adjacent independent patterns can set the exposure auxiliary pattern provided by the present invention.
Because the exposure auxiliary graph comprises at least one circle of auxiliary graph arranged around the main graph, and the shape of the circle of auxiliary graph at least closest to the main graph corresponds to the shape of the aperture during exposure, the exposure contrast of the main graph can be enhanced by the exposure auxiliary graph during exposure, a process window is increased, and then the main graph can be completely transferred to a photoresist layer and the wafer during photoetching and etching, so that the mask can meet the production requirement.
An embodiment of the present invention provides a method for manufacturing a mask, including:
first, a main pattern of a reticle is provided, which may include at least one isolated pattern whose shape may be defined according to a desired semiconductor structure to be formed on a wafer (e.g., forming a gate, a metal interconnect, or a conductive contact plug, etc.). When the main pattern includes at least two independent patterns, a distance between adjacent independent patterns can set the exposure auxiliary pattern provided by the present invention.
Then, the exposure auxiliary pattern provided by the present invention is formed to surround the main pattern. Because the exposure auxiliary graph includes that at least round encircles the auxiliary graph that main graph set up, and at least the nearest the shape of the round auxiliary graph of main graph corresponds with the light ring shape when exposing, makes when exposing the exposure auxiliary graph can strengthen the exposure contrast of main graph, the process window obtains the increase, and then makes the main graph can completely transfer to the photoresist layer with on the wafer.
Then, a process window is simulated by using the main pattern and the exposure auxiliary pattern arranged around the main pattern, so as to optimize the main pattern and the exposure auxiliary pattern arranged around the main pattern to meet the requirement. The shape, size (width, etc.), position, etc. of the auxiliary pattern in the exposure auxiliary pattern may be modified and adjusted according to the size of the process window obtained by simulation, so that the size of the process window obtained after modification and adjustment meets the requirements.
Then, a test mask is prepared using the main pattern optimized to meet the requirements and the exposure assist pattern disposed around the main pattern. And then carrying out process verification on the test mask at the chip end to obtain the mask meeting the production requirement. The test mask is adopted to carry out photoetching and etching on the wafer, whether the main pattern on the test mask can be completely transferred to the photoresist layer on the surface of the wafer and the wafer is detected, if the main pattern on the test mask can be completely transferred to the photoresist layer on the surface of the wafer and is repeatedly used, the test mask can achieve the effect, and the mask meeting the production requirement is obtained.
In summary, the method for manufacturing a mask according to the present invention includes: providing a main pattern of the mask plate; forming the exposure auxiliary pattern provided by the present invention disposed around the main pattern; simulating a process window using the main pattern and the exposure auxiliary pattern disposed around the main pattern to optimize the main pattern and the exposure auxiliary pattern disposed around the main pattern to meet requirements; preparing a test mask by using the main pattern optimized to meet the requirement and the exposure auxiliary pattern arranged around the main pattern; and carrying out process verification on the test mask at the chip end to obtain the mask meeting the production requirement. The manufacturing method of the mask plate provided by the invention has the advantages that the process window is enlarged, and the manufactured mask plate meets the production requirements.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: firstly, providing a wafer, wherein the surface of the wafer is covered with a photoresist layer; then, photoetching the photoresist layer by using the mask provided by the invention to completely transfer the main pattern on the mask onto the photoresist layer to form a patterned photoresist layer; then, taking the patterned photoresist layer as a mask, and etching the wafer to completely transfer the main pattern on the mask onto the wafer; and then, removing the patterned photoresist layer to form the semiconductor device meeting the specification requirement.
The above description is only for the purpose of describing the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are intended to fall within the scope of the appended claims.
Claims (11)
1. An exposure auxiliary graph is used for completely transferring a main graph on a mask plate onto a wafer, and is characterized by comprising at least one circle of auxiliary graphs arranged around the main graph, and the shape of the circle of auxiliary graphs at least closest to the main graph corresponds to the shape of an aperture in exposure.
2. The exposure auxiliary pattern according to claim 1, wherein at least one circle of auxiliary patterns closest to the main pattern constitutes a closed loop or a non-closed loop surrounding the main pattern.
3. The exposure auxiliary pattern according to claim 2, wherein when the one-turn auxiliary pattern forms a non-closed loop shape, the one-turn auxiliary pattern includes at least one independent zigzag pattern.
4. The exposure auxiliary pattern according to claim 3, wherein the one turn of auxiliary pattern includes at least two independent zigzag patterns, and a distance between adjacent ends of adjacent zigzag patterns is less than 0.1 μm.
5. The exposure assist pattern according to claim 3, wherein each of the independent zigzag patterns includes a flat portion and folded portions at both ends of the flat portion and folded with respect to the flat portion, and an included angle between the folded portion and the flat portion is an obtuse angle.
6. The exposure auxiliary pattern according to claim 1, comprising at least two circles of auxiliary patterns disposed around the main pattern, the auxiliary pattern of the other circle than the one circle of auxiliary pattern closest to the main pattern comprising: a plurality of independent rectangular block patterns disposed around a circle of the auxiliary patterns closest to the main pattern.
7. The exposure assist pattern according to claim 1, wherein a width of the assist pattern of each turn is smaller than a width of the main pattern.
8. A reticle, comprising: a main pattern and the exposure auxiliary pattern of any one of claims 1 to 7, the exposure auxiliary pattern being disposed around the main pattern.
9. The reticle of claim 8, wherein the primary pattern comprises at least one independent pattern.
10. A method for manufacturing a mask is characterized by comprising the following steps:
providing a main pattern of the mask plate;
forming an exposure assist pattern as defined in any one of claims 1 to 7 disposed around the main pattern;
simulating a process window using the main pattern and the exposure auxiliary pattern disposed around the main pattern to optimize the main pattern and the exposure auxiliary pattern disposed around the main pattern to meet requirements;
preparing a test mask by using the main pattern optimized to meet the requirement and the exposure auxiliary pattern arranged around the main pattern;
and carrying out process verification on the test mask at the chip end to obtain the mask meeting the production requirement.
11. A method of manufacturing a semiconductor device, comprising:
providing a wafer, wherein the surface of the wafer is covered with a photoresist layer;
photoetching the photoresist layer by using the mask plate of claim 8 or 9 to completely transfer the main pattern on the mask plate onto the photoresist layer to form a patterned photoresist layer;
etching the wafer by taking the patterned photoresist layer as a mask so as to completely transfer the main pattern on the mask onto the wafer; and the number of the first and second groups,
and removing the patterned photoresist layer.
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| CN201911101708.5A CN110687746B (en) | 2019-11-12 | 2019-11-12 | Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device |
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| CN201911101708.5A CN110687746B (en) | 2019-11-12 | 2019-11-12 | Exposure auxiliary graph, mask plate and manufacturing method of semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003021353A1 (en) * | 2001-08-31 | 2003-03-13 | Infineon Technologies Ag | Photolithographic mask |
| JP2005084393A (en) * | 2003-09-09 | 2005-03-31 | Noritsu Koki Co Ltd | Film mask |
| CN104517802A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device production method |
| CN107168010A (en) * | 2016-03-08 | 2017-09-15 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of lithography mask version |
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2019
- 2019-11-12 CN CN201911101708.5A patent/CN110687746B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003021353A1 (en) * | 2001-08-31 | 2003-03-13 | Infineon Technologies Ag | Photolithographic mask |
| JP2005084393A (en) * | 2003-09-09 | 2005-03-31 | Noritsu Koki Co Ltd | Film mask |
| CN104517802A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device production method |
| CN107168010A (en) * | 2016-03-08 | 2017-09-15 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of lithography mask version |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |