CN110677158A - FPGA (field programmable Gate array) coding method and device and storage medium - Google Patents

FPGA (field programmable Gate array) coding method and device and storage medium Download PDF

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CN110677158A
CN110677158A CN201910868906.8A CN201910868906A CN110677158A CN 110677158 A CN110677158 A CN 110677158A CN 201910868906 A CN201910868906 A CN 201910868906A CN 110677158 A CN110677158 A CN 110677158A
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马克祥
田辉
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China Electronics Technology Group Corp CETC
Electronic Science Research Institute of CTEC
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping

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Abstract

The invention discloses a method, a device and a storage medium for FPGA encoding, which can effectively eliminate the error floor problem of the traditional decoding algorithm while obtaining better decoding speed by estimating the number of flip bits suitable for each iteration according to the weight of an accompanying vector.

Description

FPGA (field programmable Gate array) coding method and device and storage medium
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for encoding an FPGA (field programmable gate array) and a storage medium.
Background
The LDPC code has good decoding performance approaching to the Shannon limit, and Gallager designs a BF algorithm for decoding the LDPC code after proposing the LDPC code, and the main code pattern of the 5G physical layer is already recommended at present. The LDPC code utilizes parallel computing platforms such as FPGA and the like to construct a parallel coder to realize quick decoding. In order to obtain better decoding performance, various decoding algorithms of the LDPC code are widely studied.
At present, the commonly used LDPC coding methods are Weighted bit flipping algorithms (Weighted BF, WBF) and Modified Weighted bit flipping algorithms (MWBF, Modified WBF), but both of the methods have a pseudo-zero value phenomenon, thereby affecting the performance of the FPGA platform.
Disclosure of Invention
The invention provides a method and a device for FPGA coding and a computer readable storage medium, which aim to solve the problem that the performance of an FPGA platform is influenced by a pseudo-zero value appearing in an LDPC code in the prior art.
In a first aspect, the present invention provides a method for FPGA coding, including:
step one, according to
Figure BDA0002202119570000011
Calculating the check value w of each check node mmIf the check value wmIf 0, the check value w is setmF, wherein, ynA channel received value of a bit node n, f is a minimum value of a digital recognition precision of the system, B (M) is a bit node set of a bit node M, M belongs to [1, M ∈]，n∈[1,N]M and N are both natural numbers;
step two, according to the check value w of each check node mmCalculating the adjoint vector weight σm；
If σ ismWhen it is 0, the decoding is stopped and the decoded output value z is outputk；
Otherwise, calculating the variable node number q ═ eta/dcAnd executing a third step, wherein k is the iteration number, eta is the column weight of the check matrix, and dcIs the column weight of the codeword;
step three, calculating the quality factor of each bit node n
Figure BDA0002202119570000021
Where A (n) is a check node set of bit nodes n, smIs the check value of the mth check node, α is a constant;
step four, turning over the initial hard decision values of q variable nodes with the minimum quality factors, and calculating the channel receiving value y of the bit node n according to the initial hard decision valuesnAnd re-executing the step one.
Preferably, according toCalculating the check value w of each check node mmBefore, still include:
calculating an initial hard decision value z for each variable node nn＝(1-sgn(yn) 2) and calculates a channel reception value y of the bit node n based on the initial hard decision valuen。
Preferably, if the iteration number k is greater than a preset iteration number threshold value, the direct output is carried outCurrent decoded output value zk。
In a second aspect, the present invention provides an apparatus for FPGA coding, the apparatus comprising:
a first computing unit for computing based on
Figure BDA0002202119570000023
Calculating the check value w of each check node mmIf the check value wmIf 0, the check value w is setm＝f；
A second calculation unit for calculating the weight σ of the adjoint vectormIf σ ismWhen it is 0, the decoding is stopped and the decoded output value z is outputkOtherwise, calculating the variable node number q ═ eta/dcAnd calculating the quality factor of each bit node n
Figure BDA0002202119570000024
And turning over the initial hard decision values of q variable nodes with the minimum quality factors, and calculating the channel receiving value y of the bit node n according to the initial hard decision valuesnTriggering the re-execution of the first computing unit;
wherein, ynA channel received value of a bit node n, f is a minimum value of a digital recognition precision of the system, B (M) a bit node set of a bit node M, M belongs to [1, M ∈]，n∈[1,N]M and N are both natural numbers k is the number of iterations, η is the column weight of the test matrix, dcIs the column weight of the codeword, A (n) is the check node set of the bit node n, smIs the check value of the mth check node, and α is a constant.
Preferably, the apparatus further comprises: a third calculation unit for calculating an initial hard decision value z of each variable node nn＝(1-sgn(yn) 2) and calculates a channel reception value y of the bit node n based on the initial hard decision valuen；
Preferably, the second calculating unit is further configured to determine whether the iteration number k is greater than a preset iteration number threshold, and if so, directly output the current decoding output value zkOtherwise, the first calculation unit is triggered to be executed again.
In a third aspect, the present invention provides a computer-readable storage medium storing a signal-mapped computer program which, when executed by at least one processor, implements the FPGA encoding method of any one of the above.
The invention has the following beneficial effects:
according to the invention, the proper number of the turning bits of each iteration is estimated according to the weight of the accompanying vector, so that the problem of error floor of the traditional decoding algorithm is effectively eliminated while the better decoding speed is obtained.
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Fig. 1 is a schematic flowchart of a method for encoding an FPGA according to a first embodiment of the present invention;
FIG. 2 is a graph showing the performance comparison of the EG (255, 173) codes provided by the first embodiment of the present invention under the decoding of the MWBF (hard), FLWBF (hard), and SIWBF (hard) algorithms;
FIG. 3 is a diagram illustrating the performance comparison of the EG (1023, 781) codes provided by the first embodiment of the present invention under decoding of the MWBF (hard), FLWBF (hard), and SIWBF (hard) algorithms;
fig. 4 is a schematic structural diagram of an FPGA encoding apparatus according to a first embodiment of the present invention.
Detailed Description
In order to solve the problem that the decoding flat layer is caused by the pseudo zero value phenomenon in the decoding process of the existing Weighted bit flipping algorithm (Weighted BF, WBF) and the improved Weighted bit flipping algorithm (MWBF, Modified WBF), the invention effectively solves the problem of the pseudo zero value by correcting the weight value of the check formula, and re-estimates the number of the flipping bits suitable for each iteration according to the accompanying vector, so that the improved algorithm is realized when hardware is utilized, and the problem of the error flat layer of the traditional decoding algorithm is effectively eliminated while the better decoding speed is obtained. The present invention will be described in further detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
A first embodiment of the present invention provides a method for encoding an FPGA, and referring to fig. 1, the method includes:
s101, according to
Figure BDA0002202119570000041
Calculating the check value w of each check node mmIf the check value wmIf 0, the check value w is setmF, wherein, ynA channel received value of a bit node n, f is a minimum value of a digital recognition precision of the system, B (M) is a bit node set of a bit node M, M belongs to [1, M ∈]，n∈[1,N]M and N are both natural numbers;
s102, calculating the weight sigma of the adjoint vectormIf σ ismIf 0, the step advances to S103, otherwise, the step proceeds to S104;
s103, stopping decoding and outputting a decoded output value zk；
S104, calculating the number q of variable nodes as eta/dcAnd executing S105, wherein k is the number of iterations, η is the column weight of the check matrix, dcIs the column weight of the codeword;
s105, calculating the quality factor of each bit node n
Figure BDA0002202119570000042
Where A (n) is a check node set of bit nodes n, smIs the check value of the mth check node, α is a constant;
s106, turning over the initial hard decision values of q variable nodes with the minimum quality factors, and calculating the channel receiving value y of the bit node n according to the initial hard decision valuesnAnd S101 is re-executed.
According to the embodiment of the invention, the proper number of the turnover bits for each iteration is estimated according to the weight of the accompanying vector, so that the problem of error floor of the traditional decoding algorithm is effectively eliminated while the better decoding speed is obtained.
In specific practice, the examples of the present invention are according to
Figure BDA0002202119570000043
Calculating the check value w of each check node mmBefore, still include: calculating each variableInitial hard decision value z for node nn＝(1-sgn(yn) 2) and calculates a channel reception value y of the bit node n based on the initial hard decision valuen。
Specifically, the embodiment of the present invention uses a binary (N, k) LDPC codeword as a research object, and is denoted as c ═ c0,c1,…,cN-1]The modulated information sequence is x ═ x0,x1,…,xN-1]，xn＝2cn-1,n∈[1,N]. After channel passing, the information sequence becomes y ═ y0,y1,…,yN-1]，yn＝xn+vn,n∈[0,N-1]，vnIs gaussian white noise. The hard judgment vector of the k step iterative decoding is defined as zk(0≤k≤Kmax). Eta is an associated vector sk＝zk×HTWeight of (A), KmaxIs the number of iterations of the decoding. w is amThe reliability metric value of the bit node connected to it is provided for check node m. A (n) ═ m: hmn1 represents the set of check nodes connected to the bit node n, the sum of the reliability metrics provided to the bit node n by this set of check nodes being denoted as phin。B(m)＝{n:hmn1 denotes a set of bit nodes connected to the check node m. Quality factor E of bit node nnThe method is used for measuring the reliability of the bit node, so as to determine whether the hard judgment result of the bit node needs to be turned over in the decoding process.
The calculation of the turning function is particularly critical, the size of the turning function value determines whether the bit is turned, and the correct turning of the bit directly determines whether the decoding is correct. Theoretical analysis proves that the quality factors of the bit nodes can not be correctly updated and evolved by using the check information of each iteration due to the pseudo-zero phenomenon in the decoding process of the WBF algorithm and the MWBF algorithm, namely smWhen taking different values, if wm0 will result in phinThe value of (d) is always 0, thereby affecting the inverse decoding of the bit node and even causing the decoding failure of the whole codeword. Therefore, the embodiment of the invention eliminates the phenomenon of 'pseudo zero value' by limiting the minimum value of the verification reliability. In addition, to improve translation of algorithmsThe code convergence rate is high, and q bits with the largest quality factor are selected to be simultaneously turned over to realize the quick decoding of the LDPC code.
The process according to the invention will be described in detail below by way of a specific example:
step 1: k is 0; computing an initial hard decision value z for each variable noden＝(1-sgn(yn))/2. Calculating a check value of each check node m by using the formula 1;
Figure BDA0002202119570000051
step 2: calculating the accompanying vector weight wmIf w ismStops decoding and outputs z when equals 0kOtherwise, calculating q ═ η/dcIn the formula dcIs the column weight of the codeword.
Step 3: k is K +1, if K > KmaxDecoding fails and z is outputk；
I.e. if the number of iterations K is greater than a preset threshold number of iterations KmaxThen directly output the current decoding output value zk。
Step 4: for each variable node n, its quality factor E is calculatednThe calculation formula is as follows:
step 5: the hard decision value of the variable node having the q smallest quality factors is flipped and then goes to Step 2.
Analysis shows that when a 'pseudo zero value' occurs in a bit node quality factor of a weighted bit flipping algorithm, the check information of each iteration cannot be updated and evolved correctly, so that a decoding value of a corresponding bit node is trapped in a current state and cannot be converged to a correct value, and further decoding failure is caused. Therefore, the embodiment of the invention eliminates the phenomenon of 'pseudo zero value' by checking the reliability and taking the quantization precision as a reference to round up. That is, when the check reliability of a check equation is zero, the quantization precision is directly taken as a value. When the method is realized by using hardware equipment such as FPGA (field programmable gate array) and the like, all verification reliability is initialized to be realized in a quantization precision mode, so that the hardware resource overhead caused by introducing judgment logic is reduced.
In addition, in order to improve the decoding convergence speed of the algorithm, the invention realizes the quick decoding of the LDPC code by selecting q bits with the largest quality factor and simultaneously carrying out inversion. Simulation finds that when q is too large, the algorithm is fast in convergence but poor in decoding performance; when the q value is too small, the simulation performance of the algorithm decoding is good but the convergence is slow. Because the number of error bits is positively correlated with the weight of the syndrome vector of the check equation in the actual decoding process, the invention utilizes the weight of the syndrome vector to calculate the number of bits which need to be turned over in each iteration.
By comparing and analyzing the simulation performance of the existing WBF algorithm and the inventive WBF algorithm, the code words used by simulation are respectively: EG (255, 173) and EG (1023, 781) codes, abbreviated as code 1 and code 2, respectively, for convenience of subsequent description. The test data is BPSK modulated and transmitted over an AWGN channel. The maximum number of iterations for the decoder is 100. 100 frames of erroneous data stop decoding performance statistics were observed per SNR point. The test data is BPSK modulated and transmitted over AWGN channel with a noise mean of 0 and a variance of N0/2. Specifically, the results are shown in tables 1 and 2.
TABLE 1 EG (255, 173) codes in FLWBF (hard), SIWBF (hard) algorithms
Iteration number comparison under decoding
Figure BDA0002202119570000071
TABLE 2 EG (1023, 781) codes in FLWBF (hard), SIWBF (hard) algorithms
Iteration number comparison under decoding
Fig. 1 and 2 show decoding performance when code 1 and code 2 use mwbf (hard), flwbf (hard), S IWBF (hard) algorithm, quantization precision of 3, 5, and 7 bits, respectively. As can be seen from fig. 1 and 2, in WBF decoding, code 1 and code 2 use mwbf (hard) decoding with 7-bit quantization accuracy, and a 10-3 level error floor occurs at 4.5 dB. Under the same conditions, the flwbf (hard) and S IWBF (hard) algorithms do not find the decoding floor phenomenon.
In each snr scenario, the flwbf (hard) algorithm has a smaller average number of iterations than the S IWBF (hard) algorithm with the same quantization accuracy. For code 1, the flwbf (hard) algorithm reduces the number of iterations by nearly 2 times compared to the S IWBF (hard) algorithm with 5 and 7 bit quantization accuracy. For code 2, the flwbf (hard) algorithm reduces the number of iterations by nearly a factor of 5 compared to the S IWBF (hard) algorithm with 5 and 7 bit quantization accuracy.
Generally, compared with the traditional WBF algorithm and MWBF algorithm, the invention can effectively reduce the error floor when the algorithm hardware is realized, and the decoding speed of the LDPC code can be improved by the fourth call.
A second embodiment of the present invention provides an FPGA coding apparatus, and referring to fig. 4, the apparatus includes:
a first computing unit for computing based onCalculating the check value w of each check node mmIf the check value wmIf 0, the check value w is setm＝f；
A second calculation unit for calculating the weight σ of the adjoint vectormIf σ ismWhen it is 0, the decoding is stopped and the decoded output value z is outputkOtherwise, calculating the variable node number q ═ eta/dcAnd calculating the quality factor of each bit node n
Figure BDA0002202119570000082
And turning over the initial hard decision values of q variable nodes with the minimum quality factors, and calculating the channel receiving value y of the bit node n according to the initial hard decision valuesnTriggering the re-execution of the first computing unit;
wherein, ynFor the channel reception value of bit node n, f is the digital identification of the systemMinimum value of bit precision, B (M) set of bit nodes M, M ∈ [1, M ∈]，n∈[1,N]M and N are both natural numbers k is the number of iterations, η is the column weight of the test matrix, dcIs the column weight of the codeword, A (n) is the check node set of the bit node n, smIs the check value of the mth check node, and α is a constant.
According to the embodiment of the invention, the proper number of the turnover bits for each iteration is estimated according to the weight of the accompanying vector, so that the problem of error floor of the traditional decoding algorithm is effectively eliminated while the better decoding speed is obtained.
In specific implementation, the apparatus according to the embodiment of the present invention further includes:
a third calculation unit for calculating an initial hard decision value z of each variable node nn＝(1-sgn(yn) 2) and calculates a channel reception value y of the bit node n based on the initial hard decision valuen；
The embodiment of the invention uses binary (N, k) LDPC code words as research objects, and the code words are recorded as c ═ c0,c1,…,cN-1]The modulated information sequence is x ═ x0,x1,…,xN-1]，xn＝2cn-1,n∈[1,N]. After channel passing, the information sequence becomes y ═ y0,y1,…,yN-1]，yn＝xn+vn,n∈[0,N-1]，vnIs gaussian white noise. The hard judgment vector of the k step iterative decoding is defined as zk(0≤k≤Kmax). Eta is an associated vector sk＝zk×HTWeight of (A), KmaxIs the number of iterations of the decoding. w is amThe reliability metric value of the bit node connected to it is provided for check node m. A (n) ═ m: hmn1 represents the set of check nodes connected to the bit node n, the sum of the reliability metrics provided to the bit node n by this set of check nodes being denoted as phin。B(m)＝{n:hmn1 denotes a set of bit nodes connected to the check node m. Quality factor E of bit node nnThe method is used for measuring the reliability of the bit node, so as to determine whether the hard judgment result of the bit node needs to be turned over in the decoding process.
The calculation of the turning function is particularly critical, the size of the turning function value determines whether the bit is turned, and the correct turning of the bit directly determines whether the decoding is correct. Theoretical analysis proves that the quality factors of the bit nodes can not be correctly updated and evolved by using the check information of each iteration due to the pseudo-zero phenomenon in the decoding process of the WBF algorithm and the MWBF algorithm, namely smWhen taking different values, if wm0 will result in phinThe value of (d) is always 0, thereby affecting the inverse decoding of the bit node and even causing the decoding failure of the whole codeword. Therefore, the embodiment of the invention eliminates the phenomenon of 'pseudo zero value' by limiting the minimum value of the verification reliability. In addition, in order to improve the decoding convergence speed of the algorithm, q bits with the largest quality factor are selected to be simultaneously turned over to realize the quick decoding of the LDPC code.
In a specific implementation, the second calculating unit according to the embodiment of the present invention is further configured to determine whether the iteration number k is greater than a preset iteration number threshold, and if so, directly output the current decoding output value zkOtherwise, the first calculation unit is triggered to be executed again.
The relevant content of the embodiments of the present invention can be understood by referring to the method embodiments, which are not described in detail herein.
A third embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for coherent pulsed laser ranging, which when executed by at least one processor, implements the method of:
step one, according to
Figure BDA0002202119570000091
Calculating the check value w of each check node mmIf the check value wmIf 0, the check value w is setmF, wherein, ynA channel received value of a bit node n, f is a minimum value of a digital recognition precision of the system, B (M) is a bit node set of a bit node M, M belongs to [1, M ∈]，n∈[1,N]M and N are both natural numbers;
step two, calculating the weight sigma of the adjoint vectorm；
If σ ismWhen it is 0, the decoding is stopped and the decoded output value z is outputk；
Otherwise, calculating the variable node number q ═ eta/dcAnd executing a third step, wherein k is the iteration number, eta is the column weight of the check matrix, and dcIs the column weight of the codeword;
step three, calculating the quality factor of each bit node n
Figure BDA0002202119570000101
Where A (n) is a check node set of bit nodes n, smIs the check value of the mth check node, α is a constant;
step four, turning over the initial hard decision values of q variable nodes with the minimum quality factors, and calculating the channel receiving value y of the bit node n according to the initial hard decision valuesnAnd re-executing the step one.
The relevant content of the embodiments of the present invention can be understood by referring to the method embodiments, which are not described in detail herein.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, and the scope of the invention should not be limited to the embodiments described above.

Claims (7)

1. An FPGA encoding method, comprising:
step one, according to
Figure FDA0002202119560000011
Calculating the check value w of each check node mmIf the check value wmIf 0, the check value w is setmF, wherein, ynA channel received value of a bit node n, f is a minimum value of a digital recognition precision of the system, B (M) is a bit node set of a bit node M, M belongs to [1, M ∈]，n∈[1,N]M and N are both natural numbers;
step (ii) ofTwo, calculating the weight sigma of the adjoint vectorm；
If σ ismWhen it is 0, the decoding is stopped and the decoded output value z is outputk；
Otherwise, calculating the variable node number q ═ eta/dcAnd executing a third step, wherein k is the iteration number, eta is the column weight of the check matrix, and dcIs the column weight of the codeword;
step three, calculating the quality factor of each bit node n
Figure FDA0002202119560000012
Where A (n) is a check node set of bit nodes n, smIs the check value of the mth check node, α is a constant;
step four, turning over the initial hard decision values of q variable nodes with the minimum quality factors, and calculating the channel receiving value y of the bit node n according to the initial hard decision valuesnAnd re-executing the step one.
2. The method of claim 1, wherein the method is based on
Figure FDA0002202119560000013
Calculating the check value w of each check node mmBefore, still include:
calculating an initial hard decision value z for each variable node nn＝(1-sgn(yn) 2) and calculates a channel reception value y of the bit node n based on the initial hard decision valuen。
3. The method according to claim 1 or 2,
if the cycle number k is larger than the preset cycle number threshold, directly outputting the current decoding output value zk。
4. An apparatus for FPGA coding, comprising:
a first computing unit for computing based on
Figure FDA0002202119560000014
Calculating the check value w of each check node mmIf the check value wmIf 0, the check value w is setm＝f；
A second calculation unit for calculating the weight σ of the adjoint vectormIf σ ismWhen it is 0, the decoding is stopped and the decoded output value z is outputkOtherwise, calculating the number of variable nodes q = eta/dcAnd calculating the quality factor of each bit node n
Figure FDA0002202119560000021
And turning over the initial hard decision values of q variable nodes with the minimum quality factors, and calculating the channel receiving value y of the bit node n according to the initial hard decision valuesnTriggering the re-execution of the first computing unit;
wherein, ynA channel received value of a bit node n, f is a minimum value of a digital recognition precision of the system, B (M) a bit node set of a bit node M, M belongs to [1, M ∈]，n∈[1,N]M and N are both natural numbers k is the number of iterations, η is the column weight of the test matrix, dcIs the column weight of the codeword, A (n) is the check node set of the bit node n, smIs the check value of the mth check node, and α is a constant.
5. The apparatus of claim 4, further comprising:
a third calculation unit for calculating an initial hard decision value z of each variable node nn＝(1-sgn(yn) 2) and calculates a channel reception value y of the bit node n based on the initial hard decision valuen。
6. The apparatus according to claim 4 or 5,
the second calculating unit is further used for judging whether the cycle number k is larger than a preset cycle number threshold value, and if so, directly outputting the current decoding output value zkOtherwise, the first calculation unit is triggered to be executed again.
7. A computer-readable storage medium, characterized in that it stores a signal-mapped computer program which, when executed by at least one processor, carries out the steps of the FPGA-coded method of any one of claims 1 to 3.
CN201910868906.8A 2019-09-16 2019-09-16 FPGA (field programmable Gate array) coding method and device and storage medium Pending CN110677158A (en)

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