CN110676355A

CN110676355A - Method for manufacturing light-emitting element

Info

Publication number: CN110676355A
Application number: CN201910870352.5A
Authority: CN
Inventors: 何金原; 吴宗典; 刘竹育
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2019-02-25
Filing date: 2019-09-16
Publication date: 2020-01-10
Anticipated expiration: 2039-09-16
Also published as: TW202032808A; TWI673888B; CN110676355B

Abstract

A manufacturing method of a light-emitting element comprises the following steps. A first semiconductor layer, a light emitting layer and a second semiconductor layer are sequentially formed on the growth substrate. A sacrificial layer is formed on the second semiconductor layer. Forming an opening in the sacrificial layer to expose a portion of the second semiconductor layer, wherein a sidewall of the opening forms an oblique angle with the second semiconductor layer, and the angle of the oblique angle ranges from 45 ° to 90 °. A first bonding layer is formed with its convex portion overlapping the opening. A carrier substrate is provided. Forming a second bonding layer and bonding the second bonding layer and the first bonding layer. And forming a first patterned semiconductor layer and a second patterned semiconductor layer. The sacrificial layer is removed to expose the convex portion and the bonding portion formed at the portion of the first insulating layer contacting the convex portion. The junction contacts the second patterned semiconductor layer.

Description

Method for manufacturing light-emitting element

Technical Field

The present invention relates to a method for fabricating a light emitting device, and more particularly, to a method for fabricating a light emitting device vertically stacked on a bonding portion.

Background

Light Emitting Diodes (LEDs) have advantages such as long life, small size, high shock resistance, low heat generation, and low power consumption, and thus have been widely used as indicators or light sources in home and various appliances. In recent years, light emitting diodes have been developed to have multi-color and high brightness, and thus their application fields have been expanded to large outdoor display boards, traffic signals, and related fields. In the future, the light emitting diode may even become a main illumination light source with power saving and environmental protection functions.

Generally, the led is fabricated on a wafer, and then transferred to the display panel by mass transfer (mass transfer) technology. Therefore, how to provide more leds on the same chip for transferring is an urgent issue to reduce the manufacturing cost and save the manufacturing time.

Disclosure of Invention

The method for manufacturing the light-emitting element of the present invention includes the following steps. First, a first semiconductor layer, a light emitting layer and a second semiconductor layer are sequentially formed on a growth substrate. A sacrificial layer is formed on the second semiconductor layer. Forming an opening in the sacrificial layer to expose a portion of the second semiconductor layer, wherein a sidewall of the opening forms an oblique angle with the second semiconductor layer, and the angle of the oblique angle ranges from 45 ° to 90 °. A first insulating layer is formed on the sacrificial layer and contacts the second semiconductor layer through the opening. A first bonding layer is formed on the first insulating layer, wherein the first bonding layer has a flat portion and a convex portion and covers the first insulating layer. A carrier substrate is provided. Forming a second bonding layer on the carrier substrate. The second bonding layer and the first bonding layer are bonded. And removing the growth substrate in a laser stripping mode. And removing part of the first semiconductor layer and part of the second semiconductor layer to form a first patterned semiconductor layer and a second patterned semiconductor layer respectively. A second insulating layer is formed to cover the first and second semiconductor layers. The second insulating layer has a first contact hole and a second contact hole. And forming a first electrode and electrically connecting the first patterned semiconductor layer through the first contact hole. And forming a second electrode and electrically connecting the second patterned semiconductor layer through the second contact hole. And removing the sacrificial layer to form a joint part on the convex part and the part of the first insulating layer contacting the convex part, wherein the joint part contacts the second patterned semiconductor layer.

The method for manufacturing the light-emitting element of the present invention includes the following steps. First, a first semiconductor layer, a light emitting layer and a second semiconductor layer are sequentially formed on a growth substrate. And removing part of the first semiconductor layer and part of the second semiconductor layer to form a first patterned semiconductor layer and a second patterned semiconductor layer respectively. A second insulating layer is formed to cover the first and second semiconductor layers. The second insulating layer has a first contact hole and a second contact hole. And forming a first electrode and electrically connecting the first patterned semiconductor layer through the first contact hole. And forming a second electrode and electrically connecting the second patterned semiconductor layer through the second contact hole. And forming a sacrificial layer on the growth substrate to cover the second patterned semiconductor layer. Forming an opening in the sacrificial layer to expose a portion of the second patterned semiconductor layer, wherein a sidewall of the opening forms an oblique angle with the second patterned semiconductor layer, and the oblique angle is in a range of 45 ° to 90 °. A first insulating layer is formed on the sacrificial layer and contacts the second patterned semiconductor layer through the opening. A first bonding layer is formed on the first insulating layer, wherein the first bonding layer has a flat portion and a convex portion and covers the first insulating layer. A carrier substrate is provided. Forming a second bonding layer on the carrier substrate. Bonding the second and first bonding layers. The growth substrate is removed. And removing the sacrificial layer to form a joint part on the convex part and the part of the first insulating layer contacting the convex part, wherein the joint part contacts the second patterned semiconductor layer.

Based on the above, in the method for manufacturing a light emitting device according to an embodiment of the invention, since the light emitting devices can be vertically stacked on the bonding portions, the bonding portions do not occupy the surface of the carrier substrate, so as to increase the number and density of the light emitting devices on the carrier substrate. When the number of the light emitting elements which can be fixed on the same bearing substrate is increased, the manufacturing cost can be reduced, the time for changing the wafer in the transposition manufacturing process can be reduced, the required number of times of alignment is reduced, and the error generated by alignment correction is reduced. Overall, the manufacturing cost can be reduced and the manufacturing time can be saved. In addition, the joint part is directly manufactured on the second patterned semiconductor layer. Therefore, when the material forming the light-emitting element is transferred onto the carrier substrate, the material does not need to be aligned with the anchor point on the carrier substrate. Therefore, the invention can reduce the times of alignment correction and reduce the error generated by alignment correction. In addition, the opening can define the size of the joint part contacting the light-emitting element, so that the connection reliability of the light-emitting element and the joint part can be improved.

One of the objectives of the present invention is to increase the number of light emitting devices on a carrier substrate.

One of the objectives of the present invention is to increase the density of light emitting devices on a carrier substrate.

One of the objectives of the present invention is to reduce the error generated by the alignment correction.

One of the objectives of the present invention is to improve the connection reliability between the light emitting device and the bonding portion.

One of the objectives of the present invention is to reduce the manufacturing cost.

One of the objectives of the present invention is to save the manufacturing time.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Drawings

Fig. 1A to fig. 1K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to an embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of a light emitting device according to another embodiment of the invention.

Fig. 3A to 3K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to still another embodiment of the invention.

Fig. 4 is a schematic cross-sectional view of a light-emitting device according to still another embodiment of the invention.

Wherein, the reference numbers:

10. 10 ', 10A': light emitting element

100: growth substrate

110. 110A: a first patterned semiconductor layer

110 ', 110A': first semiconductor layer

120. 120A: light emitting pattern layer

120 ', 120A': luminescent layer

130. 130A: second patterned semiconductor layer

130 ', 130A': a second semiconductor layer

140. 140A: sacrificial layer

141. 141A: side wall

142. 142A: opening of the container

150: a first insulating layer

152: a second insulating layer

154: part of the first insulating layer contacting the convex portion

160: the first bonding layer

162: flat part

164: convex part

170. 170A: a first electrode

172. 172A, 182A: metal pad

180. 180A: second electrode

190: joint part

200: bearing substrate

220: a second bonding layer

240: bonding structure

A1: first area

A2: second area

O1: first contact hole

O2: second contact hole

θ: angle of inclination

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

in order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.

In the drawings, the thickness of various elements and the like are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physically and/or electrically connected.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

As used herein, "about," "substantially," or "approximately" includes the stated value and the average value within an acceptable range of deviation of the stated value, taking into account the particular number of measurements in question and the errors associated with the measurements (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The present invention describes exemplary embodiments with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1A to fig. 1K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to an embodiment of the invention. The following describes a method for fabricating the light emitting device 10 (shown in fig. 1K) according to an embodiment. Referring to fig. 1A, first, a growth substrate 100 is provided. In the present embodiment, the growth substrate 100 is, for example, a Sapphire substrate (Sapphire substrate), but the invention is not limited thereto.

Next, a first semiconductor layer 110 ', a light emitting layer 120 ' and a second semiconductor layer 130 ' are sequentially formed on the growth substrate 100. For example, in the embodiment, the first semiconductor layer 110 ' includes an N-type semiconductor layer, the second semiconductor layer 130 ' includes a P-type semiconductor layer, and the light emitting layer 120 ' includes a Multiple Quantum Well (MQW) structure, but the invention is not limited thereto. The N-type semiconductor layer is made of, for example, N-type gallium nitride (N-GaN) doped with a group IVA element (e.g., silicon), and the P-type semiconductor layer is made of, for example, P-type gallium nitride (P-GaN) doped with a group IIA element (e.g., magnesium). The multiple quantum Well structure includes a plurality of quantum Well layers (Well) and a plurality of quantum Barrier layers (Barrier) alternately arranged in a repeating manner. Further, the material of the light emitting layer 120 ' includes, for example, a plurality of layers of indium gallium nitride (InGaN/GaN) and a plurality of layers of gallium nitride (InGaN/GaN) that are alternately stacked, and the ratio of indium or gallium in the light emitting layer 120 ' is designed to enable the light emitting layer 120 ' to emit light in different wavelength ranges. The first semiconductor layer 110 ', the light emitting layer 120 ', and the second semiconductor layer 130 ' may be formed by Metal-organic Chemical Vapor Deposition (MOCVD), for example. It should be noted that the materials and the forming manners of the first semiconductor layer 110 ', the light emitting layer 120 ' and the second semiconductor layer 130 ' are only examples, and the invention is not limited thereto.

Referring to fig. 1B, a sacrificial layer 140 is formed on the second semiconductor layer 130'. In the present embodiment, the material of the sacrificial layer 140 includes a photoresist material or an organic glue material. The organic adhesive material includes epoxy resin, polyurethane or acrylic resin, but the invention is not limited thereto. In the embodiment, the thickness of the sacrificial layer 140 is, for example, 1 to 3 micrometers, but the invention is not limited thereto.

Referring to fig. 1C, an opening 142 is formed in the sacrificial layer 140 to expose a portion of the second semiconductor layer 130'. The method of forming the opening 142 includes removing a portion of the sacrificial layer 140 to form the opening 142 by photolithography, laser removal, or cutting, but the invention is not limited thereto. In the present embodiment, the opening 142 is defined to penetrate the sacrificial layer 140 and has a space at the interface between the sacrificial layer 140 and the second semiconductor layer 130'. In addition, the diameter of the opening 142 is the same as the diameter of a portion of the second semiconductor layer 130' exposed at the interface of the sacrificial layer 140. The diameter of the opening 142 is 2 to 4 micrometers, but not limited thereto. In the present embodiment, the cross-sectional shape of the opening 142 is, for example, a taper (taper), but not limited thereto. The sidewalls 141 of the opening 142 form an inclination angle θ with the second semiconductor layer 130'. The angle range of the inclination angle θ is 45 ° to 90 °, but not limited thereto. Under the above arrangement, the bonding portion 190 (as shown in fig. 1K) defined by the opening 142 may have a suitable size to be firmly bonded to the light emitting device 10 without affecting other devices on the light emitting device 10.

Referring to fig. 1D, a first insulating layer 150 is formed on the sacrificial layer 140. In the present embodiment, the first insulating layer 150 contacts the second semiconductor layer 130' through the opening 142. In other words, the opening 142 defines an orthographic projection area of the first insulating layer 150 contacting the second semiconductor layer 130' in a direction perpendicular to the growth substrate 100. For example, the diameter of the opening 142 is 4 micrometers, and the area of the first insulating layer 150 contacting the second semiconductor layer 130' is 16 micrometers square, but the invention is not limited thereto. In the present embodiment, the material of the first insulating layer 150 is, for example, an inorganic material, including silicon oxide, silicon nitride, or a combination thereof, but the invention is not limited thereto. The method for forming the first insulating layer 150 includes, but is not limited to, Chemical Vapor Deposition (CVD).

Referring to fig. 1E, a first bonding layer 160 is formed on the first insulating layer 150. The first bonding layer 160 covers the first insulating layer 150 and the opening 142. Specifically, the first bonding layer 160 has a flat portion 162 and a convex portion 164. The convex portion 164 is defined as a portion of the first bonding layer 160 overlapping the opening 142. The flat portion 162 is defined as the first bonding layer 160 except for the convex portion 164. From another perspective, the flat portion 162 covers a portion of the first insulating layer 150 that does not overlap the opening 142, and the convex portion 164 covers a portion of the first insulating layer 150 that overlaps the opening 142. In the present embodiment, since the opening 142 may be tapered, the protrusion 164 filled in the opening 142 may have a taper corresponding to the opening 142, but the invention is not limited thereto. The thickness of the flat portion 162 of the first bonding layer 160 is, for example, 1 μm, but the invention is not limited thereto. In the present embodiment, the material of the first bonding layer 160 is, for example, an organic material. The organic material includes Benzocyclobutene (BCB), but is not limited thereto. In some embodiments, the material of the first bonding layer 160 may also be a non-insulating material, such as a metal or a metal alloy.

Referring to fig. 1F, a carrier substrate 200 is provided. The material of the carrier substrate 200 may include glass, quartz, plastic, opaque/reflective material (e.g., conductive material, metal, wafer, ceramic, or other suitable material) or other suitable material. Since the light emitting device 10 is, for example, a light emitting diode, the carrier substrate 200 can be a wafer, but the invention is not limited thereto.

Then, a second bonding layer 220 is formed on the carrier substrate 200. The thickness of the second bonding layer 220 is, for example, 1 μm, but the invention is not limited thereto. The material of the second bonding layer 220 may be similar to the material of the first bonding layer 160, such as an organic material. The organic material includes Benzocyclobutene (BCB), but is not limited thereto. In some embodiments, the material of the second bonding layer 220 may also include a metal or a metal alloy.

Referring to fig. 1G, the second bonding layer 220 and the first bonding layer 160 are then bonded. Before the above-mentioned bonding step, the growth substrate 100 is inverted to face the first bonding layer 160 toward the second bonding layer 220 on the carrier substrate 200. Next, the first bonding layer 160 is pressed onto the second bonding layer 220. The bonding method includes, but is not limited to, a pressure method, a heating method, or a pressure-heating method. In the present embodiment, after applying pressure and heat, the first bonding layer 160 and the second bonding layer 220 can be pressed together to form the integrated bonding structure 240. In other words, the first bonding layer 160 and the second bonding layer 220 are two separate layers before bonding. After bonding, the first bonding layer 160 and the second bonding layer 220 can be fused into a bonding structure 240 of a film layer.

Referring to fig. 1G and fig. 1H, the growth substrate 100 is then removed before the step of removing portions of the first semiconductor layer 110 'and the second semiconductor layer 130' is performed. The method for removing the growth substrate 100 includes separating the growth substrate 100 from the first semiconductor layer 110' by a laser lift off method, but the invention is not limited thereto.

Referring to fig. 1H and fig. 1I, an etching process (etching process) is performed on the first semiconductor layer 110 'and the second semiconductor layer 130' to remove a portion of the first semiconductor layer 110 'and a portion of the second semiconductor layer 130'. For example, a portion of the first semiconductor layer 110 ', a portion of the second semiconductor layer 130 ' and a portion of the light emitting layer 120 ' may be removed by plasma etching (plasma etching). In some embodiments, boron trichloride (BCl) may also be used₃) And/or chlorine (Cl)₂) As an Etching reaction gas, the first semiconductor layer 110 ', the second semiconductor layer 130 ' and the light emitting layer 120 ' are etched by Reactive-Ion Etching (RIE), but the invention is not limited thereto.

In this embodiment, after removing a portion of the first semiconductor layer 110 'and a portion of the second semiconductor layer 130', the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130 may be formed, respectively. In other words, the first semiconductor layer 110' is etched to form the first patterned semiconductor layer 110. The second semiconductor layer 130' is etched to form the second patterned semiconductor layer 130. In addition, the light emitting layer 120' is etched to form the light emitting pattern layer 120, and is located between the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130. In the present embodiment, the orthographic projection of the first patterned semiconductor layer 110 is smaller than the orthographic projection of the second patterned semiconductor layer 130 in the direction perpendicular to the carrier substrate 200. For example, the cross-section of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130 may be stepped, but the invention is not limited thereto. In the present embodiment, the first patterned semiconductor layer 110 is an N-type semiconductor layer, and the second patterned semiconductor layer 130 is a P-type semiconductor layer, but not limited thereto.

As shown in fig. 1I, a second insulating layer 152 is formed on the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130. The second insulating layer 152 covers the first patterned semiconductor layer 110 and the second patterned semiconductor layer 130. In the present embodiment, the material of the second insulating layer 152 may include silicon oxide, silicon nitride, or other suitable materials.

Then, a photolithography process is used to pattern and develop the second insulating layer 152. A plurality of contact holes (vias) are formed in the second insulating layer 152 by etching. The contact holes serve as windows through which the patterned

semiconductor layers

110 and 130 are electrically connected to electrodes. The etching method may be Dry etching (Dry etch) or wet etching (Wetetch), but the invention is not limited thereto. In the present embodiment, the plurality of contact holes include a first contact hole O1 and a second contact hole O2. The first contact hole O1 is located on the first patterned semiconductor layer 110. The second contact hole O2 is located on the second patterned semiconductor layer 130.

Referring to fig. 1J, a first electrode 170 is then formed on the second insulating layer 152. The first electrode 170 is electrically connected to the first patterned semiconductor layer 110 through the first contact hole O1. Next, a second electrode 180 is formed on the second insulating layer 152. The second electrode 180 is electrically connected to the second patterned semiconductor layer 130 through the second contact hole O2. In the present embodiment, the first electrode 170 and the second electrode 180 are formed by, for example, forming a conductive layer by Physical Vapor Deposition (PVD), and then performing photolithography and etching processes, but not limited thereto. The first electrode 170 may be a transparent electrode, a reflective electrode, or a combination thereof. For example, the transparent electrode may be made of metal oxide, such as: indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, or other suitable oxide, or a stacked layer of at least two of the foregoing; the reflective electrode may be made of metal or other suitable materials, but the invention is not limited thereto. The second electrode 180 is made of metal, but the invention is not limited thereto, and in other embodiments, the second electrode 180 may also be made of other conductive materials, such as: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, graphene, stacked layers of metallic materials, or stacked layers of other conductive materials.

In the present embodiment, the light emitting device 10 includes a first electrode 170, a first patterned semiconductor layer 110, a light emitting pattern layer 120, a second patterned semiconductor layer 130, a second electrode 180, and a second insulating layer 152. The second patterned semiconductor layer 130 is located between the first electrode 170, the second electrode 180 and the carrier substrate 200. For example, the first electrode 170 and the second electrode 180 face away from the carrier substrate 200. Under the above arrangement, the light emitting element 10 can be referred to as a light-emitting diode (LED). For example, the light emitting device 10 is a lateral light emitting diode chip (lateral LED chip).

In the present embodiment, the carrier substrate 200 is, for example, a wafer for carrying a plurality of light emitting devices 10. For clarity of the drawings and convenience of description, only one light emitting device 10 is illustrated on the carrier substrate 200. One skilled in the art should understand that thousands of light emitting devices 10 can be carried on the carrier substrate 200 for the conventional mass transfer technology.

Referring to fig. 1J and fig. 1K, the sacrificial layer 140 is removed. The method for removing the sacrificial layer 140 includes, but is not limited to, etching. In the present embodiment, after removing the sacrificial layer 140, the protruding portion 164 and the portion 154 of the first insulating layer 150 contacting the protruding portion 164 may form a joint portion 190. In detail, after removing the sacrificial layer 140, the protruding portion 164 overlapping the opening 142 and the first insulating layer 150 in the opening 142 contacting the second patterned semiconductor layer 130 and the protruding portion 164 may be defined as the joint portion 190. From another perspective, joint 190 includes protrusion 164 and portion 154 of first insulating layer 150 that contacts protrusion 164. Wherein the portion 154 of the first insulating layer 150 contacting the convex portion 164 may abut and contact the second patterned semiconductor layer 130. That is, the junction 190 contacts the second patterned semiconductor layer 130. In the present embodiment, the bonding portion 190 may be applied as an anchor (anchor) for fixing the light emitting element 10 on the carrier substrate 200. The first insulating layer 150 and/or the portion 154 of the first insulating layer 150 may be used as a separation layer to reduce the probability of damage to the light emitting device 10 in a subsequent process of mass transfer.

It is noted that, in the present embodiment, the bonding portion 190 serving as an anchor may overlap the second patterned semiconductor layer 130 in a direction perpendicular to the carrier substrate 200. In other words, the second patterned semiconductor layer 130 is vertically stacked on the junction 190. Under the above arrangement, compared to the conventional contact structure (teter) in which the anchor points are disposed at the side of the light emitting device to be fixed to the surface of the chip, the bonding portion 190 of the present embodiment is fixed at the bottom of the light emitting device 10 and overlaps the second patterned semiconductor layer 130. As such, the joint 190 does not occupy an additional surface of the carrier substrate 200. Thus, the omitted extra surface can be used to carry more light emitting elements 10. Therefore, the present invention can increase the number of the light emitting devices 10 and increase the density of the light emitting devices 10 on the carrier substrate 200.

In addition, the portion 154 of the first insulating layer 150 of the bonding portion 190 and the protruding portion 164 of the first bonding layer 160 are directly formed on the second semiconductor layer 130' (as shown in fig. 1E). Therefore, when the second semiconductor layer 130 ', the light emitting layer 120 ' and the first semiconductor layer 110 ' are transferred onto the carrier substrate 200 (as shown in fig. 1G), they do not need to be aligned with the anchor points on the carrier substrate 200. In addition, it is not necessary to perform alignment correction after the above-mentioned transposing process to form anchor points on the sides of the light-emitting device 10. Therefore, the invention can reduce the times of alignment correction and reduce the error generated by alignment correction.

In addition, referring to fig. 1J and fig. 1K, since the diameter of the opening 142 of the present embodiment is defined as the same as the diameter of the portion of the surface of the second patterned semiconductor layer 130 (the second semiconductor layer 130' after etching) exposed by the opening 142. In addition, the joint 190 may be defined by the opening 142. Therefore, the diameter of the portion of the junction 190 contacting the interface of the second patterned semiconductor layer 130 is the same as the diameter of the opening 142. In other words, an orthographic area of an interface where the bonding portion 190 contacts the second patterned semiconductor layer 130 is the same as an orthographic area of the opening 142 in a direction perpendicular to the carrier substrate 200. Then, the ratio of the orthographic projection area (e.g., the first area a1) of the opening 142 on the carrier substrate 200 to the orthographic projection area (e.g., the second area a2) of the second patterned semiconductor layer 130 on the carrier substrate 200 is in a range from 1:2 to 1: 625. That is, the forward projection area of the bonding portion 190 contacting the light emitting element 10 is smaller than the forward projection area of the light emitting element 10. For example, the first area a1 is smaller than the second area a 2. Under the above arrangement, the bonding portion 190 can be fixed to the light emitting element 10 without affecting the configuration of the

electrodes

170, 180 or other elements on the light emitting element 10. In addition, within the above ratio range, the bonding portion 190 can further achieve a tensile force of less than 1 kilogram force (kgw) with the light emitting device 10. Therefore, the connection reliability between the light emitting device 10 and the bonding portion 190 can be improved, and the subsequent bulk transfer process is not affected.

In addition, in some embodiments, the light emitting elements 10 can be applied to manufacture a display panel (not shown). For example, the light emitting elements 10 can be fixed on the carrier substrate 200 by the bonding portions 190. Next, a plurality of light emitting elements 10 are transferred onto an array substrate (not shown) by a bulk transfer process to fabricate a light emitting diode display panel (LED display panel). The mass transfer process may include pick and place (pick and place) technology to pick up the light emitting device 10 through the connector, align the light emitting device, and place the light emitting device on the array substrate.

It is noted that, since the light emitting devices 10 of the present invention can be vertically stacked on the bonding portion 190, the number and density of the light emitting devices 10 can be increased on a single carrier substrate 200 (e.g., a wafer). When the number of the light emitting devices 10 that can be fixed on the same carrier substrate 200 is increased, the manufacturing cost can be reduced, the time for replacing the chip in the transposing process can be reduced, and the number of times of alignment required can be reduced, so as to reduce the error caused by the alignment correction. Overall, the manufacturing cost can be reduced and the manufacturing time can be saved. In addition, since the light emitting devices 10 are vertically stacked on the bonding portions 190, the space saved on the carrier substrate 200 allows the arrangement of the light emitting devices 10 to be more flexible. For example, the arrangement pattern of the light emitting elements 10 can be designed according to the requirements of the pixels of the display panel. Therefore, the manufacturing time of the display panel using the light emitting device 10 is further saved, and the display quality is further improved.

In short, since the light emitting devices 10 can be vertically stacked on the bonding portions 190, the bonding portions 190 do not occupy the surface of the carrier substrate 200, so as to increase the number and density of the light emitting devices 10 on the carrier substrate 200. When the number of the light emitting devices 10 that can be fixed on the same carrier substrate 200 is increased, the manufacturing cost can be reduced, the time for replacing the chip in the transposing process can be reduced, and the number of times of alignment required can be reduced, so as to reduce the error caused by the alignment correction. Overall, the manufacturing cost can be reduced and the manufacturing time can be saved. In addition, the bonding portion 190 is directly formed on the second patterned semiconductor layer 130. Therefore, when the material forming the light emitting device 10 is transferred onto the carrier substrate 200, it is not necessary to align with the anchor point on the carrier substrate 200. In addition, it is not necessary to perform alignment correction after the above-mentioned transposing process to form anchor points on the sides of the light-emitting device 10. Therefore, the invention can reduce the times of alignment correction and reduce the error generated by alignment correction. In addition, the connection reliability between the bonding portion 190 and the light emitting device 10 can be improved without affecting the subsequent bulk transfer process.

The following embodiments follow the reference numerals and part of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and for the part of the description where the same technical contents are omitted, reference may be made to the foregoing embodiments, and the description in the following embodiments is not repeated.

Fig. 2 is a schematic cross-sectional view of a light emitting device according to another embodiment of the invention. Referring to fig. 1K and fig. 2, a light emitting device 10' of the present embodiment is similar to the light emitting device 10 of fig. 1K, and the main difference is: the method of fabricating the light emitting device 10' further includes forming a plurality of metal pads 172, 182 electrically connected to the first electrode 170 and the second electrode 180, respectively, before the step of removing the sacrificial layer 140. In the present embodiment, the metal pad 172 is disposed on the first patterned semiconductor layer 110 and covers the first electrode 170. The metal pad 182 is disposed on the second patterned semiconductor layer 130 and covers the second electrode 180. The top surface of metal pad 172 is aligned with the top surface of metal pad 182, but not limited thereto. The metal pads 172, 182 are made of metal, but the invention is not limited thereto, and in other embodiments, the metal pads 172, 182 may also be made of other conductive materials, such as: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, graphene, stacked layers of metallic materials, or stacked layers of other conductive materials. Thus, the light emitting device 10' can further improve the electrical quality. In addition, the light emitting device 10' can also achieve similar technical effects as the above embodiments.

Fig. 3A to 3K are schematic cross-sectional views illustrating a manufacturing process of a light emitting device according to still another embodiment of the invention. The light emitting device 10A illustrated in fig. 3A to 3K is similar to the light emitting device 10 illustrated in fig. 1A to 1K, wherein materials and formation methods of the same or similar layers may be similar, and thus are not repeated. In the following embodiments, the light-emitting element 10A is a flip-chip LED chip (flip-chip LED chip) which is simply described.

Referring to fig. 3A, a growth substrate 100 is provided. Next, a first semiconductor layer 110A ', a light emitting layer 120A ', and a second semiconductor layer 130A ' are sequentially formed on the growth substrate 100. In the embodiment, the first semiconductor layer 110A ' includes an N-type semiconductor layer, the second semiconductor layer 130A ' includes a P-type semiconductor layer, and the light emitting layer 120A ' includes a Multiple Quantum Well (MQW) structure, but the invention is not limited thereto.

Referring to fig. 3B, an etching process (etching process) is then performed on the first semiconductor layer 110A 'and the second semiconductor layer 130A' to remove a portion of the first semiconductor layer 110A 'and a portion of the second semiconductor layer 130A'. In addition, the light emitting layer 120A' is also etched, but the invention is not limited thereto.

In this embodiment, after removing a portion of the first semiconductor layer 110A 'and a portion of the second semiconductor layer 130A', the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A may be formed, respectively. In other words, the first semiconductor layer 110A' is etched to form the first patterned semiconductor layer 110A. The second semiconductor layer 130A' is etched to form a second patterned semiconductor layer 130A. In addition, the light emitting layer 120A' is etched to form a light emitting pattern layer 120A between the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A. In the present embodiment, the orthographic projection of the second patterned semiconductor layer 130A is smaller than the orthographic projection of the first patterned semiconductor layer 110A in the direction perpendicular to the growth substrate 100. For example, the cross-section of the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A may be stepped, but the invention is not limited thereto. In the present embodiment, the first patterned semiconductor layer 110A is an N-type semiconductor layer, and the second patterned semiconductor layer 130A is a P-type semiconductor layer, but not limited thereto.

As shown in fig. 3B, a second insulating layer 152 is formed on the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A. The second insulating layer 152 covers the first patterned semiconductor layer 110A and the second patterned semiconductor layer 130A. In the present embodiment, the material of the second insulating layer 152 may include silicon oxide, silicon nitride, or other suitable materials.

Then, a photolithography process is used to pattern and develop the second insulating layer 152. A plurality of contact holes are formed in the second insulating layer 152 by etching. In the present embodiment, the plurality of contact holes include a first contact hole O1 and a second contact hole O2. The first contact hole O1 is located on the second patterned semiconductor layer 130A. The second contact hole O2 is located on the first patterned semiconductor layer 110A.

Referring to fig. 3C, a first electrode 170A is formed on the second insulating layer 152. The first electrode 170A is electrically connected to the first patterned semiconductor layer 110A through the second contact hole O2. Next, a second electrode 180A is formed on the second insulating layer 152. The second electrode 180 is electrically connected to the second patterned semiconductor layer 130A through the first contact hole O1. In the present embodiment, the second electrode 180A may be a transparent electrode, a reflective electrode, or a combination thereof. The material of the first electrode 170A is metal, but the invention is not limited thereto. The top surface of the first electrode 170A is aligned with the top surface of the second electrode 180A, but the invention is not limited thereto.

In the present embodiment, the light emitting device 10A includes a first electrode 170A, a first patterned semiconductor layer 110A, a light emitting pattern layer 120A, a second patterned semiconductor layer 130A, a second electrode 180A, and a second insulating layer 152. The first electrode 170A and the second electrode 180A face a side away from the growth substrate 100. Under the above arrangement, the light emitting device 10A is a light emitting diode chip with a flip-chip structure.

Referring to fig. 1D, a sacrificial layer 140A is then formed on the growth substrate 100, and the sacrificial layer 140A covers the second patterned semiconductor 130A and the first patterned semiconductor 110A. In the embodiment, the thickness of the sacrificial layer 140A is, for example, 1 to 3 micrometers, but the invention is not limited thereto.

Referring to fig. 1E, an opening 142A is formed in the sacrificial layer 140A to expose a portion of the second patterned semiconductor layer 130A'. In the present embodiment, the opening 142A is defined as a space penetrating the sacrificial layer 140A and having an interface between the sacrificial layer 140A and the second patterned semiconductor layer 130A'. In addition, the diameter of the opening 142A is the same as the diameter of a portion of the second patterned semiconductor layer 130A' exposed at the interface of the sacrificial layer 140A. The diameter of the opening 142A is 2 to 4 micrometers, but not limited thereto. In the present embodiment, the cross-sectional shape of the opening 142A is, for example, a taper (taper), but not limited thereto. The sidewall 141A of the opening 142A forms an inclination angle θ with the second patterned semiconductor layer 130A'. The angle range of the inclination angle θ is 45 ° to 90 °, but not limited thereto. Under the above arrangement, the bonding portion 190 (as shown in fig. 3K) defined by the opening 142A can have a suitable size to be firmly bonded to the light emitting device 10A without affecting other devices on the light emitting device 10A.

Referring to fig. 3F, a first insulating layer 150 is then formed on the sacrificial layer 140A. In the present embodiment, the first insulating layer 150 contacts the second patterned semiconductor layer 130A' through the opening 142A. In other words, the opening 142A may define an orthographic projection area of the first insulating layer 150 contacting the second patterned semiconductor layer 130A' in a direction perpendicular to the growth substrate 100. On the other hand, the orthographic area of the first insulating layer 150 contacting the second patterned semiconductor layer 130A' is the same as the orthographic area of the opening 142A.

Referring to fig. 3G, a first bonding layer 160 is formed on the first insulating layer 150. The first bonding layer 160 covers the first insulating layer 150 and the opening 142A. Specifically, the first bonding layer 160 has a flat portion 162 and a convex portion 164. The convex portion 164 is defined as a portion of the first bonding layer 160 overlapping the opening 142A. The flat portion 162 is defined as the first bonding layer 160 except for the convex portion 164. From another perspective, the flat portion 162 covers a portion of the first insulating layer 150 that does not overlap the opening 142A, and the convex portion 164 covers a portion of the first insulating layer 150 that overlaps the opening 142A. In the embodiment, since the opening 142A may be tapered, the protrusion 164 filled in the opening 142A may have a taper corresponding to the opening 142A, but the invention is not limited thereto. The thickness of the flat portion 162 of the first bonding layer 160 is, for example, 1 μm, but the invention is not limited thereto.

Referring to fig. 3H, a carrier substrate 200 is provided. Next, a second bonding layer 220 is formed on the carrier substrate 200. The thickness of the second bonding layer 220 is, for example, 1 μm, but the invention is not limited thereto.

Referring to fig. 3I, the second bonding layer 220 and the first bonding layer 160 are then bonded. Before the above-mentioned bonding step, the growth substrate 100 is inverted to face the first bonding layer 160 toward the second bonding layer 220 on the carrier substrate 200. Next, the first bonding layer 160 is pressed onto the second bonding layer 220. In the present embodiment, the first bonding layer 160 and the second bonding layer 220 are two separate layers before bonding. After bonding, the first bonding layer 160 and the second bonding layer 220 can be fused into a bonding structure 240 of a film layer, but not limited thereto.

Referring to fig. 3I and 3J, the growth substrate 100 is then removed. The method for removing the growth substrate 100 includes separating the growth substrate 100 from the first patterned semiconductor layer 110A by a laser lift off method, but the invention is not limited thereto.

Referring to fig. 3J and fig. 3K, the sacrificial layer 140A is removed. In the present embodiment, after removing the sacrificial layer 140A, the protrusion 164 and the portion 154 of the first insulating layer 150 contacting the protrusion 164 may form a joint 190. In detail, after removing the sacrificial layer 140A, the protruding portion 164 overlapping the opening 142A and the first insulating layer 150 in the opening 142A contacting the second patterned semiconductor layer 130A and the protruding portion 164 may be defined as the bonding portion 190. From another perspective, joint 190 includes protrusion 164 and portion 154 of first insulating layer 150 that contacts protrusion 164. Wherein the portion 154 of the first insulating layer 150 contacting the convex portion 164 may abut and contact the second patterned semiconductor layer 130A. That is, the junction 190 contacts the second patterned semiconductor layer 130A. In the present embodiment, the bonding portion 190 may be applied as an anchor (anchor) for fixing the light emitting element 10A on the carrier substrate 200. The first insulating layer 150 and/or the portion 154 of the first insulating layer 150 may be used as a separation layer to reduce the probability of damage to the light emitting device 10A in a subsequent process of mass transfer. In the present embodiment, the light emitting element 10A may be vertically stacked on the bonding portion 190. Therefore, the light emitting device 10A can achieve similar technical effects as the above embodiments.

In the present embodiment, a ratio of an orthographic area of the opening 142A on the carrier substrate 200 (e.g., the first area a1) to an orthographic area of the second patterned semiconductor layer 130A on the carrier substrate 200 (e.g., the second area a2) is in a range from 1:2 to 1: 625. That is, the forward projection area of the joint portion 190 contacting the light emitting element 10A is smaller than the forward projection area of the light emitting element 10A. For example, the first area a1 is smaller than the second area a 2. Under the above arrangement, the bonding portion 190 can be fixed to the light emitting element 10A without affecting the arrangement of the

electrodes

170A, 180A or other elements on the light emitting element 10A. In addition, within the above ratio range, the bonding portion 190 can further achieve a tensile force of less than 1 kilogram force (kgw) with the light emitting device 10A. Thereby, the connection reliability of the light emitting element 10A and the bonding portion 190 can be improved.

In addition, in the present embodiment, the first electrode 170A and the second electrode 180A are located between the first patterned semiconductor layer 110A and the carrier substrate 200. In other words, the light-emitting element 10A is fixed to the bonding portion 190 in a flip-chip structure. Thus, in the subsequent bulk transfer process, the substrate can be directly disposed on an array substrate (not shown) by a pick-and-place technique, so as to be applied to the fabrication of a display panel. Therefore, an additional wire bonding process is not needed, the manufacturing cost is further reduced, and the manufacturing time is saved.

Fig. 4 is a schematic cross-sectional view of a light-emitting device according to still another embodiment of the invention. Referring to fig. 3K and fig. 4, the light emitting device 10A' of the present embodiment is similar to the light emitting device 10A of fig. 3K, and the main difference is: the method for manufacturing the light emitting device 10A' further includes forming a plurality of

metal pads

172A, 182A electrically connected to the first electrode 170A and the second electrode 180A, respectively, before the step of forming the sacrificial layer 140A. In the embodiment, the metal pad 172A is disposed on the first patterned semiconductor layer 110A and covers the first electrode 170A. The metal pad 182A is disposed on the second patterned semiconductor layer 130A and covers the second electrode 180A. The top surface of metal pad 172A is aligned with the top surface of metal pad 182A, but not limited thereto. The

metal pads

172A, 182A are made of metal, but the invention is not limited thereto, and in other embodiments, the

metal pads

172A, 182A may also be made of other conductive materials, such as: alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, graphene, stacked layers of metallic materials, or stacked layers of other conductive materials. Thus, the light emitting device 10A' can further improve the electrical quality. In addition, the light emitting device 10A' can also achieve similar technical effects as the above embodiments.

In summary, in the method for manufacturing a light emitting device according to an embodiment of the invention, since the light emitting devices can be vertically stacked on the bonding portions, the bonding portions do not occupy the surface of the carrier substrate, so as to increase the number and density of the light emitting devices on the carrier substrate. When the number of the light emitting elements which can be fixed on the same bearing substrate is increased, the manufacturing cost can be reduced, the time for changing the wafer in the transposition manufacturing process can be reduced, the required number of times of alignment is reduced, and the error generated by alignment correction is reduced. Overall, the manufacturing cost can be reduced and the manufacturing time can be saved. In addition, the joint part is directly manufactured on the second patterned semiconductor layer. Therefore, when the material forming the light-emitting element is transferred onto the carrier substrate, the material does not need to be aligned with the anchor point on the carrier substrate. Therefore, the invention can reduce the times of alignment correction and reduce the error generated by alignment correction. In addition, the opening can define the area of the joint part contacting the light-emitting element, and the ratio range of the orthographic projection area of the opening to the orthographic projection area of the light-emitting element can enable the tensile force between the joint part and the light-emitting element to be less than 1 kilogram force (kgw). Therefore, the connection reliability between the light emitting device and the bonding portion can be improved without affecting the subsequent bulk transfer process. In addition, the space saved on the bearing substrate can further lead the arrangement mode of the light-emitting elements to have more margin, thereby further saving the manufacturing time of a display panel applying the light-emitting elements and further improving the display quality.

The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for manufacturing a light emitting element, comprising:

sequentially forming a first semiconductor layer, a light emitting layer and a second semiconductor layer on a growth substrate;

forming a sacrificial layer on the second semiconductor layer;

forming an opening in the sacrificial layer to expose a portion of the second semiconductor layer, wherein a sidewall of the opening and the second semiconductor layer form an angle of inclination, and the angle of inclination is in a range from 45 ° to 90 °;

forming a first insulating layer on the sacrificial layer and contacting the second semiconductor layer through the opening;

forming a first bonding layer on the first insulating layer, wherein the first bonding layer has a flat portion and a convex portion, the flat portion covers the first insulating layer, and the convex portion overlaps the opening;

providing a bearing substrate;

forming a second bonding layer on the carrier substrate;

bonding the second bonding layer and the first bonding layer;

removing part of the first semiconductor layer and part of the second semiconductor layer to form a first patterned semiconductor layer and a second patterned semiconductor layer respectively;

forming a second insulating layer covering the first patterned semiconductor layer and the second patterned semiconductor layer, the second insulating layer having a first contact hole and a second contact hole;

forming a first electrode and electrically connecting the first patterned semiconductor layer through the first contact hole;

forming a second electrode and electrically connecting the second patterned semiconductor layer through the second contact hole; and

removing the sacrificial layer to form a joint part on the convex part and the part of the first insulating layer contacting with the convex part, wherein the joint part contacts with the second patterned semiconductor layer.

2. The method of claim 1, wherein the growth substrate is removed before the step of removing a portion of the first semiconductor layer and a portion of the second semiconductor layer.

3. The method of claim 1, wherein the second patterned semiconductor layer is disposed between the first electrode and the second electrode and the carrier substrate.

4. The method of claim 1, wherein the first patterned semiconductor layer is an N-type semiconductor layer and the second patterned semiconductor layer is a P-type semiconductor layer.

5. The method of claim 1, wherein a ratio of an area of the opening in an orthographic projection of the carrier substrate to an area of the second patterned semiconductor layer in an orthographic projection of the carrier substrate in a direction perpendicular to the carrier substrate is in a range from 1:2 to 1: 625.

6. The method of claim 1, further comprising forming a plurality of metal pads electrically connected to the first electrode and the second electrode, respectively, before the step of removing the sacrificial layer.

7. A method for manufacturing a light emitting element, comprising:

forming a second electrode and electrically connecting the second patterned semiconductor layer through the second contact hole;

forming a sacrificial layer on the growth substrate to cover the second patterned semiconductor layer;

forming an opening in the sacrificial layer to expose a portion of the second patterned semiconductor layer, wherein a sidewall of the opening and the second patterned semiconductor layer form an inclined angle, and the angle of the inclined angle ranges from 45 ° to 90 °;

forming a first insulating layer on the sacrificial layer and contacting the second patterned semiconductor layer through the opening;

providing a bearing substrate;

forming a second bonding layer on the carrier substrate;

bonding the second bonding layer and the first bonding layer;

removing the growth substrate; and

8. The method of claim 7, wherein the first electrode and the second electrode are disposed between the first patterned semiconductor layer and the carrier substrate.

9. The method of claim 7, wherein the first patterned semiconductor layer is an N-type semiconductor layer and the second patterned semiconductor layer is a P-type semiconductor layer.

10. The method of claim 7, further comprising forming a plurality of metal pads electrically connected to the first electrode and the second electrode, respectively, before the step of forming the sacrificial layer.