CN110676318A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN110676318A CN110676318A CN201911110750.3A CN201911110750A CN110676318A CN 110676318 A CN110676318 A CN 110676318A CN 201911110750 A CN201911110750 A CN 201911110750A CN 110676318 A CN110676318 A CN 110676318A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present disclosure provides a semiconductor device and a method of fabricating the same, the device including a substrate; a first insulating layer formed on the substrate; a first semiconductor layer formed on the first insulating layer; the side surface of the first semiconductor layer obliquely intersects with the upper surface of the first insulating layer; a second semiconductor layer formed on a side surface of the first semiconductor layer, a third semiconductor layer formed on a side surface of the second semiconductor layer, a fourth semiconductor layer formed on the first to third semiconductor layers, and a two-dimensional charge carrier gas formed at interfaces of the fourth semiconductor layer and the first to third semiconductor layers. The present disclosure helps to achieve one of the following effects: the device has simple structure, simple process, low cost and excellent electrical property.
Description
Technical Field
The present disclosure relates to the field of power semiconductor devices, and more particularly, to a transistor having high electron mobility and a method of fabricating the same.
Background
Group III nitride semiconductors are an important new semiconductor material, mainly including AlN, GaN, InN, and compounds of these materials such as AlGaN, InGaN, AlInGaN, and the like. The III nitride semiconductor has great prospect in the field of power semiconductors by utilizing the advantages of direct band gap, wide forbidden band, high breakdown electric field intensity and the like of the III nitride semiconductor and optimizing the design of device structures and processes. One important device type of the group III nitride semiconductor is a high electron mobility transistor, and it is desirable to develop a high electron mobility transistor having high performance such as high withstand voltage, high power, and low on-resistance.
The existing high electron mobility transistor has the problems of complex structure, complex process, high cost and the like, and the structure in the high electron mobility transistor, such as a nucleating layer, can be strip-shaped, and the strip-shaped structure is easy to have some gaps or uneven surface in the growth process; the epitaxial semiconductor layer structure of the high electron mobility transistor is generally layered, and the problems of overlarge internal stress and the like easily exist; and such a layered structure is disadvantageous for realizing a device structure having a specific function. In view of the above, the present disclosure provides a novel semiconductor device structure and a method for manufacturing the same, which aims to overcome the above-mentioned drawbacks and provide a semiconductor device with simple structure, simple process, low cost and excellent electrical performance.
Disclosure of Invention
A brief summary of the disclosure is provided below in order to provide a basic understanding of some aspects of the disclosure. It should be understood that this summary is not an exhaustive overview of the disclosure. It is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a first insulating layer formed on the first surface of the substrate; forming the substrate with an exposed opening portion on the first insulating layer; forming a monocrystalline nucleation layer on the substrate exposed by the opening, and forming a polycrystalline or amorphous nucleation material on the first insulating layer; and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a silicon substrate; forming a first insulating layer on a first surface of the silicon substrate; forming the substrate with an exposed opening portion on the first insulating layer; forming a groove on the substrate corresponding to the opening; forming a single crystal nucleation layer within the trench; forming a polycrystalline or amorphous nucleation material on the first insulating layer; and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
Further, the single crystal nucleation layer is single crystal AlN and the polycrystalline or amorphous nucleation material is polycrystalline or amorphous AlN.
Further, the first insulating layer is SiO2Layer or Si3N4And (3) a layer.
Further, the first semiconductor layer is a nitride semiconductor layer.
Further, the substrate is selected from sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3Or monocrystalline silicon.
Further wherein the depth of the trench is 0.2-10 microns deep.
Further wherein the depth of the trench is about 1 micron.
Further, an insulating protection layer is formed on the two side walls of the groove and the opening.
Further, wherein the insulating protective layer is SiO2And an insulating protective layer.
Further wherein the semiconductor device is a high mobility transistor, the opening corresponds to a drain of the high mobility transistor.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a first insulating layer formed on the first surface of the substrate; forming the substrate with an exposed opening portion on the first insulating layer; forming a nucleation layer on the substrate exposed by the opening; forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer; a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center; the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; forming a second semiconductor layer on the first semiconductor layer second surface and the third surface; forming a third semiconductor layer on the second semiconductor layer second surface and the third surface; a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a silicon substrate; forming a first insulating layer on a first surface of the silicon substrate; forming the substrate with an exposed opening portion on the first insulating layer; a groove formed on the substrate corresponding to the opening; a single crystal nucleation layer formed within the trench; forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer; taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode; the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; forming a second semiconductor layer on the first semiconductor layer second surface and the third surface; forming a third semiconductor layer on the second semiconductor layer second surface and the third surface; a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
According to another aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a nucleation layer formed on the first surface of the substrate in a full-covering mode; a first insulating layer formed on a first surface of the nucleation layer; forming the nucleation layer with an exposed portion of an opening on the first insulating layer; a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center; the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; forming a second semiconductor layer on the first semiconductor layer second surface and the third surface; forming a third semiconductor layer on the second semiconductor layer second surface and the third surface; a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
Further wherein a two-dimensional charge carrier gas is formed at interfaces between the fourth semiconductor layer and the first, second, and third semiconductor layers.
Further wherein a fifth semiconductor layer that is either unintentionally doped or lowly doped is further included between the fourth semiconductor layer and the first, second and third semiconductor layers, a two-dimensional charge carrier gas being formed at the interface between the fourth semiconductor layer and the fifth semiconductor layer.
Further, the doping concentration of the low-doped fifth semiconductor layer is<2E18/cm3。
Further wherein the angle is between 30-75 degrees.
Further wherein the second semiconductor layer is a P-type buried layer.
Further, the doping concentration of the P-type buried layer is 1E17-5E19/cm3。
Further, wherein the first surface of the first semiconductor layer, the first surface of the second semiconductor layer, and the first surface of the third semiconductor layer are approximately in the same plane.
Further wherein the fourth semiconductor is selected from AlGaN, InAlGaN, or InAlN.
Further, a first electrode, a second electrode, and a third electrode are formed on the first surface of the fourth semiconductor.
Further, the range of the first end of the second semiconductor layer projected onto the first surface of the substrate is overlapped with the range of the second electrode projected onto the substrate; or the range of the first end of the second semiconductor layer projected to the substrate is positioned in the range of the second electrode projected to the first surface of the substrate.
Further, the range of the second end of the second semiconductor layer projected onto the first surface of the substrate is overlapped with the range of the first electrode projected onto the substrate; or the projection range of the second end of the second semiconductor layer to the substrate is positioned in the projection range of the first electrode to the first surface of the substrate.
Further, the semiconductor device further comprises a fourth electrode which forms ohmic contact with the second semiconductor layer.
Further, there is a second insulating layer formed over the fourth semiconductor and under the second electrode.
Further, the nucleation layer is formed on the substrate, and the buffer layer is formed on the nucleation layer.
Further, the second semiconductor layer includes at least two sub-layers, wherein the first sub-layer has a weak P-type doping concentration relative to the second sub-layer, and the second sub-layer has a strong P-type doping concentration relative to the first sub-layer.
Further, the first sublayer is closer to the third electrode than the second sublayer.
Further wherein the second semiconductor layer has a doping concentration sufficient to deplete 95% to 100% of the two-dimensional charge carrier gas in at least a portion of the region overlapping the projected area of the second electrode in the absence of a device bias voltage.
Further, when the bias voltage of the second electrode is 0, the two-dimensional charge carrier gas corresponding to at least a partial region of the second electrode is lower than 5E +11/cm2。
Further, the doping concentration of the second semiconductor layer is uniform, or the doping concentration of the second semiconductor layer is gradually decreased or is gradually decreased along the direction from the second electrode to the third electrode; or the doping concentrations in the first sublayer and the second sublayer are uniform, or the doping concentrations in the first sublayer and the second sublayer decrease in a gradient or step-wise manner along the direction from the second electrode to the third electrode.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: step 100: providing a substrate; step 200: forming a first insulating layer on a first surface of the substrate; step 300: forming an opening in the first insulating layer to expose a portion of the substrate; step 400: depositing a nucleation material to fill the opening to form a nucleation layer; step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer; step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer; step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: step 100: providing a substrate; step 200: forming a nucleation layer on the first surface of the substrate in a covering mode; step 300: forming a first insulating layer on the nucleation layer; step 400: forming an opening in the first insulating layer to expose a portion of the nucleation layer; step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer; step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material and the third semiconductor material on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer; step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: step 100: providing a silicon substrate; step 200: forming a first insulating layer on a first surface of the silicon substrate; step 300: forming an opening in the first insulating layer to expose a portion of the silicon substrate; step 400: etching the exposed silicon substrate to form a groove on the silicon substrate; step 500: depositing a nucleation material to fill the trench to form a nucleation layer; step 600: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer; step 700: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer; step 800: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer; step 900: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
Further wherein the angle is between 30-75 degrees.
Further, the doping concentration of the P-impurity is 1E17-5E19/cm 3.
Further, the method also comprises the step 1000: forming a first region and a second region doped with N + by a doping process, which form ohmic contact with the two-dimensional charge carrier gas and simultaneously form ohmic contact with the second semiconductor layer, and then forming a first electrode and a third electrode on the fourth semiconductor layer corresponding to the first and second regions, respectively, and forming a second electrode between the first electrode and the third electrode.
Further, the range of the first end of the second semiconductor layer projected to the first surface of the substrate is overlapped with the range of the second electrode projected to the first surface of the substrate; or the projection range of the first end of the second semiconductor layer to the substrate is positioned in the projection range of the second electrode to the first surface of the substrate.
Further, the range of the second end of the second semiconductor layer projected to the first surface of the substrate is overlapped with the range of the first electrode projected to the first surface of the substrate; or the range of the second end of the second semiconductor layer projected to the first surface of the substrate is positioned in the range of the first electrode projected to the first surface of the substrate.
Further, wherein the opening is formed at a position corresponding to the formation of the third electrode.
And further forming an insulating protection layer on the side walls of the groove and the opening and the bottom surface of the groove through a deposition process, and removing the insulating protection layer on the bottom surface of the groove through an anisotropic etching process to expose the substrate.
Further, the nucleated AlN material is filled in the growth atmosphere of the chlorine-containing gas, so that the nucleating material AlN is hardly deposited on the first surface of the first insulating layer, and the nucleating layer is formed only at the openings and/or the grooves.
And further, etching a through hole reaching the second part of the second semiconductor layer on the second surface of the substrate, and depositing an electrode material in the through hole to form a fourth electrode.
And further etching the first surface of the fourth semiconductor layer to form a through hole reaching the second part of the second semiconductor layer, and depositing an electrode material in the through hole to form a fourth electrode.
Further, a second insulating material layer is formed on the fourth semiconductor layer in a covering mode, or a second insulating material layer is formed on the fourth semiconductor layer and then the second insulating material at the second electrode area is reserved.
Further, the method also comprises the step of depositing a buffer layer on the nucleation layer before forming the first semiconductor layer.
And further adjusting the doping amount of introduced P-type impurities on the second surface and the third surface of the first semiconductor layer, and sequentially epitaxially forming a first sublayer with weak P-type doping concentration and a second sublayer with strong P-type doping concentration of the second semiconductor layer.
Further wherein the doping concentration of the first sublayer is <5E18/cm 3; the doping concentration of the second sublayer is 1E17-5E19/cm 3.
Further, the doping concentration in each of the first sublayer and the second sublayer is uniform, or decreases in a gradient along the direction from the second electrode to the third electrode or decreases in a step along the direction from the second electrode to the third electrode.
According to another aspect of the present disclosure, there is provided an electronic device including the semiconductor device in the present disclosure.
Further, the electronic device is a power supply device, a mobile phone, or a power amplifier in a communication system.
The scheme of the disclosure can at least help to realize one of the following effects: the semiconductor device can reduce grid leakage current, has high threshold voltage, high power and high reliability, can realize low on-resistance and normally-off state of the device, and can provide stable threshold voltage, so that the semiconductor device has good switching characteristic and is safer in use.
The structure and the preparation process of the semiconductor device are simple, and the production cost can be effectively reduced.
Drawings
The above and other objects, features and advantages of the present disclosure will be more readily understood from the following detailed description of the present disclosure with reference to the accompanying drawings. The drawings are only for the purpose of illustrating the principles of the disclosure. The dimensions and relative positioning of the elements in the figures are not necessarily drawn to scale. In the drawings:
fig. 1-2 show a schematic cross-sectional view of a semiconductor device structure according to a first embodiment;
fig. 3 shows a schematic cross-sectional view of a semiconductor device structure according to a second embodiment;
fig. 4 shows a schematic cross-sectional view of a semiconductor device structure according to a third embodiment;
fig. 5 shows a schematic cross-sectional view of a semiconductor device structure according to a fourth embodiment;
fig. 6 shows a schematic cross-sectional view of a semiconductor device structure according to a fifth embodiment;
fig. 7 shows a schematic cross-sectional view of a semiconductor device structure according to a sixth embodiment;
fig. 8 to 15 show schematic cross-sectional views of a method of manufacturing a semiconductor device according to a seventh embodiment;
fig. 16 to 19 are schematic cross-sectional views showing a method of manufacturing a semiconductor device of an eighth embodiment.
Detailed Description
Exemplary disclosures of the present disclosure will be described hereinafter with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an implementation of the present disclosure are described in the specification. It will be appreciated, however, that in the development of any such actual implementation of the disclosure, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
Here, it should be further noted that, in order to avoid obscuring the present disclosure by unnecessary details, only device structures closely related to the scheme according to the present disclosure are shown in the drawings, and other details not so related to the present disclosure are omitted.
It is to be understood that the disclosure is not limited to the described embodiments, as described below with reference to the drawings. Herein, features between different implementations may be replaced or borrowed where feasible, and one or more features may be omitted in one implementation.
Specifically, the semiconductor device of the present disclosure is a compound semiconductor device including a nitride semiconductor material, also referred to as a nitride semiconductor device. The nitride semiconductor device includes a transistor in which a nitride semiconductor material is used. Further, the transistor is a GaN transistor including a GaN semiconductor material. In particular, the GaN transistor is a normally-off transistor GaN-HEMT.
First embodiment
A semiconductor device according to a first embodiment is described with reference to fig. 1 to 2.
As shown in fig. 1, in the first embodiment, the semiconductor device, such as an exemplary normally-off HEMT device, includes a substrate 100, and a material of the substrate 100 may be selected according to actual needs, and the specific form of the substrate 100 is not limited in this embodiment. Alternatively, the substrate 100 may be sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3Or single crystal silicon or the like; further, said Al2O3The substrate may be (0001) -plane Al2O3(ii) a Further the single crystal silicon substrate may be a (111) plane silicon substrate. On the first surface 1001 of the substrate 100, there is a first insulating layer 102, illustratively, the first insulating layer 102 is SiO2Layer or Si3N4And (3) a layer. An opening formed in the first insulating layer 102 exposes the substrate 100, and a nucleation layer 103 is formed on the substrate exposed by the opening. An optional opening on the first insulating layer 102 is formed at a location corresponding to formation of a source electrode or a drain electrode of a subsequent semiconductor device.
Preferably, when an opening on the first insulating layer 102 is formed at a position corresponding to the formation of a subsequent semiconductor device drain electrode, a first semiconductor layer 104 (channel layer) is formed on the first surface 1021 of the first insulating layer 102 and on the first surface of the nucleation layer 103.
Alternatively, as shown in fig. 2, a nucleation layer 103 'is blanket formed on a first surface 1001 of the substrate 100, and a first insulating layer 102 is formed on the nucleation layer 103'. Illustratively, the first insulating layer 102 is SiO2Layer or Si3N4. An opening is formed in the first insulating layer 102 to expose the nucleation layer 103'. A first semiconductor layer 104 (channel layer) is formed on the first surface 1021 of the first insulating layer 102 and the exposed first surface 1031 'of the nucleation layer 103'. The first semiconductor layer 104 may be a nitride, illustratively an intrinsic GaN layer(i-GaN) or an unintentionally doped GaN layer. The GaN layers are oriented substantially parallel to the epitaxial direction of the first surface 1001 of the substrate 100.
Wherein the second surface 1042 and the third surface 1043 of the first semiconductor layer 104 are at an angle to the first surface 1021 of the first insulating layer 102. Alternatively, the angle is between 30 and 75 degrees, so that the projections of the upper and lower ends thereof on the insulating layer 102 can be located in different regions.
A second semiconductor layer 105 is formed on the second surface 1042 and the third surface 1043 of the first semiconductor layer 104. Illustratively, the second semiconductor layer 105 is a P-type buried layer having a doping concentration of, illustratively, 1E17-5E19/cm3. Further, the second semiconductor layer 105 is a P-type doped GaN layer.
A third semiconductor layer 106 is formed on the second surface 1052 and the third surface 1053 of the second semiconductor layer 105. The first surface 1041 of the first semiconductor layer 104, the first surface 1051 of the second semiconductor layer 105, and the first surface 1061 of the third semiconductor layer 106 are approximately in the same plane. The materials of the first semiconductor layer 104 and the third semiconductor layer 106 may be the same or different.
A fourth semiconductor layer 107 formed on the first semiconductor layer 104, the second semiconductor layer 105, and the third semiconductor layer 106. Optionally, the fourth semiconductor layer 107 may be an AlGaN layer, an InAlGaN layer, an InAlN layer, or the like. The first semiconductor layer 104, the second semiconductor layer 105, and the third semiconductor layer 106 have a smaller forbidden bandwidth than the fourth semiconductor layer 107, so that a two-dimensional charge carrier gas, for example, a two-dimensional electron gas 2DEG, is formed between the fourth semiconductor layer 107 and the interfaces of the first semiconductor layer 104, the second semiconductor layer 105, and the third semiconductor layer 106.
A second electrode 202 is formed on the first surface 1051 of the second semiconductor layer 105 and the first surface 1071 of the fourth semiconductor 107 corresponding to the fourth semiconductor 107, and the second electrode 202 is a gate electrode. The gate electrode forms a schottky contact with the fourth semiconductor layer 107 to reduce off-state leakage current. Optionally, a range of the first end of the second semiconductor layer 105 away from the first surface 1001 of the substrate projected onto the first surface 1001 of the substrate overlaps with a range of the second electrode 202 projected onto the substrate. Preferably, the range in which the first end of the second semiconductor layer 105 projects to the first surface 1001 of the substrate may be located within the range in which the second electrode 202 projects to the substrate.
The second semiconductor layer 105 can precisely control the process parameters such as the epitaxial time and the like during the lateral epitaxy, so that the very thin width of the second semiconductor layer 105 can be controlled. Since the resistance of the depletion region is usually relatively high, reducing the width of the depletion region can effectively reduce the on-resistance of the device, and is also beneficial to reducing the size of the device and improving the area utilization rate of the wafer.
The second semiconductor layer 105, such as its thickness, length, width, P-type doping concentration, etc., can be set specifically according to device parameters. The two-dimensional charge carrier gas at its interface with the fourth semiconductor layer 107 may illustratively be made less than 5E11/cm2 at a gate bias of 0, it being understood that the second semiconductor layer 105 is depleted of only a portion of the two-dimensional charge carrier gas in the region where the second electrode 202 projects to overlap, and is not depleted of the other region of the two-dimensional charge carrier gas. Thereby leading to a higher threshold voltage, a lower on-resistance and a normally-off state of the device, which in turn leads to a good switching characteristic of the device.
A first electrode 201 and a third electrode 203 formed on the fourth semiconductor layer 107. The first and third electrode materials may be TiN, Ni, ITO, Au, etc. The first electrode 201 may be a source electrode that forms an ohmic contact with the two-dimensional charge carrier gas. The second electrode 203 may be a drain electrode that forms an ohmic contact with the two-dimensional charge carrier gas. Wherein the extent of the projection of the second end of the second semiconductor layer 105 near the first surface 1001 of the substrate to the first surface 1001 of the substrate may be located within the extent of the projection of the first electrode to the substrate; or the extent of the projection of the second end of the second semiconductor layer 105 onto the first surface 1001 of the substrate overlaps with the extent of the projection of the first electrode onto the substrate.
In this embodiment mode, it is preferable that the nucleation layer is formed at a position corresponding to formation of a drain electrode of a subsequent semiconductor device, with respect to a position corresponding to formation of a source electrode of a subsequent semiconductor device where the nucleation layer is formed. In this embodiment, the second surface 1042 and the third surface 1043 where the first semiconductor layer 104 intersects with the first surface 1021 of the first insulating layer 102 are inclined, so that the corresponding surface of the second semiconductor layer 105 is also inclined. By the specific projection relationship among the end faces of the first electrode 201, the second electrode 202, and the second semiconductor layer 105 designed in this embodiment, the second semiconductor layer 105 can be formed obliquely, and at the same time, a normally-off semiconductor device can be realized more preferably by the second semiconductor layer 105, and the potential of the semiconductor device can be controlled.
Second embodiment
As shown in fig. 3, in a second embodiment, the semiconductor device, an exemplary, e.g., normally-off HEMT device, includes a silicon substrate 100. A first insulating layer 102 formed on the first surface of the substrate 100, the first insulating layer 102 illustratively being SiO2Layer or Si3N4. Forming an opening on the first insulating layer 102 at a position corresponding to the subsequent third electrode 203 or at a position corresponding to the subsequent first electrode 201 exposes the substrate 100, preferably at a position corresponding to the subsequent third electrode 203. The exposed substrate 100 is then etched to form a trench 0.2-10 microns deep, typically about 1 micron deep, in the substrate 100. Forming an insulating protective layer 1003, illustratively SiO, on both sidewalls of the trench of the substrate 100 and the opening of the first insulating layer 1022And an insulating protective layer. A nucleation layer 103 is formed on the substrate where the trench bottom is exposed. The material of the nucleation layer 103 is AlN. A first semiconductor layer 104 (channel layer) is formed on the first surface 1021 of the first insulating layer 102 and on the first surface of the nucleation layer 103. Wherein the second and third surfaces of the first semiconductor layer 104 are at an angle to the first surface of the first insulating layer 102. Optionally, the angle is between 30 and 75 degrees. Other constructional features and first embodimentThe scheme is the same and is not described in detail herein.
In this embodiment, the groove is formed in the substrate 100, so that the distance between the third electrode and the substrate 100 is increased, and the leakage current is effectively reduced. In addition, the arrangement of the insulating protection layers on the side walls of the two sides of the groove can further reduce leakage current.
Third embodiment
Referring to fig. 4, on the basis of the first embodiment or the second embodiment, there is further provided a fourth electrode 204, and the fourth electrode 204 is a bulk electrode which forms an ohmic contact with the second end of the second semiconductor layer 105 to control the electric potential of the semiconductor device. The fourth electrode 204 may be a separate electrode to independently control the potential; or the fourth electrode 204 may be connected to the first electrode 201.
Fourth embodiment
Referring to fig. 5, on the basis of the first to third embodiments, the second insulating layer 108 is formed under the second electrode 202. The second insulating layer 108 serves to reduce gate leakage current.
Fifth embodiment
Referring to fig. 6, on the basis of the first embodiment or the second embodiment, before forming the first semiconductor layer, a buffer layer 300 is formed on the nucleation layer to improve crystal quality and reduce leakage current between the third electrode and the substrate.
Sixth embodiment
Referring to fig. 7, on the basis of the first embodiment or the second embodiment, the second semiconductor layer 105 may be divided into at least two sub-layers. Wherein the first sublayer 1055 has a lower P-type doping concentration relative to the second sublayer 1056, with the particular doping concentration being tailored according to the particular device parameters to be insufficient to fully deplete two-dimensional electrons at the channel in the absence of device bias, such as <5E18/CM3 for example. The second sublayer 1056 has a higher P-type doping concentration relative to the first sublayer 1055, and the particular doping concentration of the second sublayer is designed according to particular device parameters to be sufficient to substantially completely deplete the two-dimensional charge carrier gas projected onto the second electrode in the absence of device bias, as exemplified by 1E17-5E19/CM 3. Preferably, the first sub-layer is closer to the third electrode 203 than the second sub-layer for adjusting the electric field distribution. It is to be understood that the number of the sub-layers is not limited to two, and may be provided in plural.
Further alternatively, the second semiconductor layer 105 may be a single semiconductor layer as described in the first and second embodiments, and the doping concentration of the single semiconductor layer decreases in a single-sided gradient or a single-sided step along the direction from the second electrode 202 to the third electrode 203. It will be further appreciated that the doping concentration in each of the first and second sublayers may be uniform or may exhibit regular or irregular variations, such as a one-sided gradient or a one-sided step decrease, along the direction from the second electrode 202 to the third electrode 203.
Seventh embodiment
A manufacturing method for manufacturing the semiconductor device of the first embodiment will now be exemplarily described with reference to fig. 8 to 15.
A substrate 100 is provided, and the material of the substrate 100 is selected as described in the first embodiment, which is not described herein. A first insulating layer 102 is formed on the first surface 1001 of the substrate 100. Optionally, the first insulating layer 102 is formed by a deposition process; optionally, when the substrate 100 is a silicon substrate, the first insulating layer 102 is SiO2When forming a layer, the first insulating layer 102 may be formed by an oxidation process. An opening is formed in the first insulating layer 102 to expose the substrate 100, and the opening in the first insulating layer 102 may be formed at a position corresponding to formation of a first electrode of a subsequent semiconductor device or at a position corresponding to formation of a third electrode.
When the opening on the first insulating layer 102 is formed at a position corresponding to the formation of the first electrode of the subsequent semiconductor device, the high electron mobility transistor exhibits a symmetrical structure, i.e., the first electrode 201 (source electrode) has the second electrode 202 (gate electrode) and the third electrode 203 (drain electrode) on both sides, because the first electrode 201 (source electrode) is used as a reference point in the high electron mobility transistor. The distance from the first electrode 201 (source electrode) to the second electrode 202 (gate electrode) is much smaller than the distance from the second electrode 202 (gate electrode) to the third electrode 203 (drain electrode). It is advantageous to fabricate various fine and complicated structures at the first electrode 201 and the second electrode 202 by epitaxy, while crystal quality of the nucleation layer region is poor due to a low voltage of the first electrode region (source region), and thus, the effect can be minimized due to the low voltage of the source region when the nucleation layer is formed corresponding to the first electrode (source electrode) formation.
When the opening on the first insulating layer 102 is formed at a position corresponding to the formation of the third electrode 203 of the subsequent semiconductor device, it is avoided that when the potential of the P-type buried layer is controlled by the high electron mobility transistor through lateral epitaxy from the first electrode region, the P-type buried layer needs to be extended to the position of the third electrode 203 (drain electrode) through a complex modulation doping lateral epitaxy structure, and ohmic contact and potential control of the P-type buried layer are realized near the third electrode 203 (drain electrode), thereby reducing the complex structure of the device, lowering the cost and simplifying the process.
Specifically, a nucleation layer 103 is formed on the substrate 100 exposed by the opening. The material of the nucleation layer is selected to be the material of the growth core of the first semiconductor layer 104. Illustratively, in Al2O3On the substrate, gallium nitride can be used as a nucleation material, and due to its excellent selectivity, polycrystalline or amorphous gallium nitride can be decomposed at high temperature in an atmosphere containing hydrogen, so that the nucleation layer 103 can be exposed to the Al2O3Is selectively grown on the substrate without growing on the first insulating layer 102. Illustratively, on a silicon substrate, the material of the nucleation layer 103 may be AlN, which is typically removed by etching or grinding or the like on the first surface 1021 of the first insulating layer 102 after being deposited on the first insulating layer 102 to fill the opening, so as to form the nucleation layer 103 in the opening. Further, on the silicon substrate, the material of the nucleation layer 103 may be AlN, which is assisted by an atmosphere with a chlorine-containing gas in the first regionThere is no significant nitride growth on the first surface 1021 of the insulating layer 102, or little deposition of the nucleation material AlN on the first surface 1021 of the first insulating layer 102, forming the nucleation layer 103 only at the openings. So that the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102 may be dispensed with, thereby saving processing costs. Further, the material of the nucleation layer 103 on the silicon substrate may be AlN, which is polycrystalline or amorphous by process adjustment to form an AlN layer on the first surface 1021 of the first insulating layer 102, and the nucleation layer formed by the nucleation material on the surface of the substrate of the opening is single-crystal AlN. It is thus possible to achieve in subsequent lateral epitaxy that the first semiconductor layer 103 nucleates growth only from the nucleation layer of the opening and not on the polycrystalline or amorphous AlN layer on the insulating layer, so that the polycrystalline AlN or amorphous layer also functions as an insulator, and the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102 is not necessary, thereby saving processing costs.
Alternatively, a nucleation layer 103 'is blanket formed on the first surface 101 of the substrate 100, and a first insulating layer 102 is deposited on the nucleation layer 103'. An opening is formed in the first insulating layer 102 to expose the nucleation layer 103'.
A first semiconductor layer 104 (e.g., intrinsic i-GaN or unintentionally doped GaN layer) is formed by lateral epitaxy on the first surface of the first insulating layer 102 and the exposed first surface of the nucleation layer 103'. The second and third surfaces of the first semiconductor layer 104 formed by lateral epitaxy are at an angle to the first surface of the first insulating layer 102. Optionally, the angle is between 30 and 90 degrees.
A second semiconductor layer is formed on the second surface and the third surface of the first semiconductor layer 104 by doping P-impurities in a lateral epitaxial process. Illustratively, the doping concentration of the second semiconductor layer is 1E17-5E19/cm 3.
And continuing to form a third semiconductor material on the second semiconductor layer in a lateral epitaxy mode through a lateral epitaxy process. The third semiconductor material covers the first to third surfaces of the second semiconductor layer. Portions of the upper surfaces of the third semiconductor material and the second semiconductor layer are removed to form the discrete third semiconductor layer 106 and the second semiconductor layer 105, illustratively by a grinding process, until the first surface of the first semiconductor layer is exposed.
A fourth semiconductor layer 107 is formed on the third semiconductor layer 106, and optionally, the fourth semiconductor layer 107 is an AlGaN layer, an InAlGaN layer, an InAlN layer, or the like. The first semiconductor layer 104, the second semiconductor layer 105, and the third semiconductor layer 106 have a smaller forbidden bandwidth than the fourth semiconductor layer 107, thereby forming a two-dimensional charge carrier gas, for example, 2DEG, between the fourth semiconductor layer 107 and the first semiconductor layer 104-the third semiconductor layer 106.
Illustratively, a first region and a second region (source/drain region) doped with N + are formed at corresponding positions by a doping process such as ion implantation, which form ohmic contact with the two-dimensional charge carrier gas and then form a first electrode on the first region by a process such as sputtering, evaporation, etc., and form a third electrode on the second region by a process such as sputtering, evaporation, etc. The first and third electrode materials may be TiN, Ni, ITO, Au, etc., and a second electrode is formed on the fourth semiconductor layer between the first and third electrodes.
Eighth embodiment
A manufacturing method for manufacturing the semiconductor device of the second embodiment will now be exemplarily described with reference to fig. 16 to 19.
A silicon substrate 100 is provided and a first insulating layer 102 is formed on a first surface 1001 of the silicon substrate 100. Optionally, the first insulating layer 102 is formed by deposition, oxidation process, or the like; an opening is formed on the first insulating layer 102 to expose a portion of the silicon substrate 100, and the silicon substrate 100 is etched through the opening to form a trench with a depth of 0.2-10 microns, typically 1 micron, on the silicon substrate 100. Alternatively, the opening on the first insulating layer 102 may be formed at a position corresponding to formation of a third electrode of a subsequent semiconductor device. Alternatively, the opening on the first insulating layer 102 may also be formed at a position corresponding to the formation of the first electrode of the subsequent semiconductor device. An insulating protective layer, illustratively SiO2 or Si3N4, is formed on the sidewalls and bottom of the trench by an oxidation or deposition process. And then, removing the insulating protection layer on the bottom surface of the trench by an anisotropic etching process to expose the silicon substrate 100. Optionally, an AlN material is deposited on the substrate 100 exposed by the opening to fill the trench to form a nucleation layer 103 in the opening. Further, an AlN material may be deposited on the substrate 100 exposed by the opening to fill the opening under a growth atmosphere containing a chlorine-containing gas, in which case the nucleation material AlN does not significantly grow on the first surface 1021 of the first insulating layer 102, or the nucleation material AlN deposits little on the first surface 1021 of the first insulating layer 102, and the nucleation layer 103 is formed only at the opening. Thus, the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102 may be eliminated, saving processing costs. Further, the material of the nucleation layer 103 on the silicon substrate may be AlN, which is polycrystalline or amorphous to form an AlN layer on the first surface 1021 of the first insulating layer 102, and single-crystal AlN which is formed on the substrate surface of the opening. Thus, the first semiconductor layer 103 can be nucleated and grown only from the nucleation layer of the opening and not grown on the polycrystalline AlN layer on the insulating layer in the subsequent lateral epitaxy, so that the polycrystalline AlN layer also plays an insulating role, and the step of removing the nucleation material AlN on the first surface 1021 of the first insulating layer 102 is not needed, thereby saving the process cost.
Alternatively, a nucleation layer 103 'is blanket formed on the first surface 101 of the substrate 100, and a first insulating layer 102 is deposited on the nucleation layer 103'. An opening is formed in the first insulating layer 102 to expose the nucleation layer 103'.
The following formation of the respective structural features is performed with reference to the seventh embodiment, and is not described in detail here.
Ninth embodiment
On the basis of the seventh and eighth embodiments, a through hole reaching the second portion of the second semiconductor layer 105 is formed on the second surface of the substrate by etching, and an electrode material is deposited in the through hole to form a fourth electrode.
Alternatively, a via hole is etched in the first surface of the fourth semiconductor layer 107 to the second portion of the second semiconductor layer 105, and an electrode material is deposited in the via hole to form a fourth electrode.
It is to be understood that the fourth electrode is not limited to this, and may be drawn out from the side of the second semiconductor layer 105 by etching and depositing a metal material.
Tenth embodiment
In the seventh embodiment or the eighth embodiment, a second insulating material is formed over the fourth semiconductor layer 107, and the second insulating material outside the subsequent second electrode 202 region is removed to form the second insulating layer 108.
Eleventh embodiment
On the basis of the seventh or eighth embodiment, a buffer layer is deposited on the nucleation layer before the first semiconductor layer is formed.
Twelfth embodiment
The first sublayer 1055 with a lower P-type doping concentration of the second semiconductor layer 105 and the second sublayer 1056 with a higher P-type doping concentration of the second semiconductor layer 105 are sequentially formed on the second surface 1042 and the third surface 1043 of the first semiconductor layer 104 formed in the first embodiment or the second embodiment, for example, by adjusting the concentration of dopants during MOCVD epitaxy. Or the doping concentration of the second semiconductor layer 105 is gradually decreased along the direction from the second electrode 202 to the third electrode 203 by adjusting the concentration of the dopant during the MOCVD epitaxy process.
It is understood that the sub-layers may be provided as multiple layers without being limited to two layers by adjusting the concentration of dopants during epitaxy.
The doping concentration in the further individual sub-layers may also be adjusted during epitaxy to provide a uniform, regular or irregular, e.g. a unilateral gradient decreasing or a step change between the individual sub-layers, within the individual sub-layers along the direction from the second electrode 202 to the third electrode 203.
The processes of the rest parts refer to the seventh or eighth embodiment, and are not described herein again.
Thirteenth embodiment
A power supply device comprising any one of the semiconductor devices in the above embodiments. The power supply device includes a primary circuit, a secondary circuit, a transformer, and the like, wherein each of the primary circuit and the secondary circuit includes a switching element, and the switching element includes any one of the semiconductor devices in the above-described embodiments.
Fourteenth embodiment
A cellular phone comprising any of the semiconductor devices in the above embodiments. The mobile phone includes a display screen, a charging unit, and the like, wherein the charging unit includes any of the semiconductor devices in the above embodiments.
Fifteenth embodiment
An amplifier which can be used for a power amplifier in the field of a mobile phone base station, an optical communication system, or the like, may include any of the semiconductor devices in the above embodiments.
While the disclosure has been described with reference to specific embodiments, it will be apparent to those skilled in the art that these descriptions are intended in an illustrative rather than in a limiting sense. Various modifications and alterations of this disclosure will become apparent to those skilled in the art from the spirit and principles of this disclosure, and such modifications and alterations are also within the scope of this disclosure.
Claims (10)
1. A semiconductor device, comprising:
a substrate;
a first insulating layer formed on the first surface of the substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
forming a monocrystalline nucleation layer on the substrate exposed by the opening, and forming a polycrystalline or amorphous nucleation material on the first insulating layer;
and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
2. A semiconductor device, comprising:
a silicon substrate;
forming a first insulating layer on a first surface of the silicon substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
forming a groove on the substrate corresponding to the opening;
forming a single crystal nucleation layer within the trench;
forming a polycrystalline or amorphous nucleation material on the first insulating layer;
and taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode.
3. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is a high mobility transistor, and the opening corresponds to a drain of the high mobility transistor.
4. A semiconductor device, comprising:
a substrate;
a first insulating layer formed on the first surface of the substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
forming a nucleation layer on the substrate exposed by the opening;
forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer;
a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center;
the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
forming a second semiconductor layer on the first semiconductor layer second surface and the third surface;
forming a third semiconductor layer on the second semiconductor layer second surface and the third surface;
a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
5. A semiconductor device, comprising:
a silicon substrate;
forming a first insulating layer on a first surface of the silicon substrate;
forming the substrate with an exposed opening portion on the first insulating layer;
a groove formed on the substrate corresponding to the opening;
a single crystal nucleation layer formed within the trench;
forming a polycrystalline or amorphous nucleation material on the first insulating layer; or forming no nucleation material on the first insulating layer;
taking the single crystal nucleating layer as a nucleation center, and growing a first semiconductor layer in a lateral epitaxial mode;
the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
forming a second semiconductor layer on the first semiconductor layer second surface and the third surface;
forming a third semiconductor layer on the second semiconductor layer second surface and the third surface;
a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
6. A semiconductor device, comprising:
a substrate;
a nucleation layer formed on the first surface of the substrate in a full-covering mode;
a first insulating layer formed on a first surface of the nucleation layer;
forming the nucleation layer with an exposed portion of an opening on the first insulating layer;
a first semiconductor layer which is grown in a lateral epitaxial mode by taking the nucleation layer as a nucleation center;
the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
forming a second semiconductor layer on the first semiconductor layer second surface and the third surface;
forming a third semiconductor layer on the second semiconductor layer second surface and the third surface;
a fourth semiconductor layer formed on the first surfaces of the first, second, and third semiconductor layers.
7. A method of manufacturing a semiconductor device, comprising:
step 100: providing a substrate;
step 200: forming a first insulating layer on a first surface of the substrate;
step 300: forming an opening in the first insulating layer to expose a portion of the substrate;
step 400: depositing a nucleation material to fill the opening to form a nucleation layer;
step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer;
step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer;
step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
8. A method of manufacturing a semiconductor device, comprising:
step 100: providing a substrate;
step 200: forming a nucleation layer on the first surface of the substrate in a covering mode;
step 300: forming a first insulating layer on the nucleation layer;
step 400: forming an opening in the first insulating layer to expose a portion of the nucleation layer;
step 500: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
step 600: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer;
step 700: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material and the third semiconductor material on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer;
step 800: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
9. A method of manufacturing a semiconductor device, comprising:
step 100: providing a silicon substrate;
step 200: forming a first insulating layer on a first surface of the silicon substrate;
step 300: forming an opening in the first insulating layer to expose a portion of the silicon substrate;
step 400: etching the exposed silicon substrate to form a groove on the silicon substrate;
step 500: depositing a nucleation material to fill the trench to form a nucleation layer;
step 600: taking the nucleation layer as a nucleation center, growing a first semiconductor layer in a lateral epitaxial mode, wherein the second surface and the third surface of the first semiconductor layer form an angle with the first surface of the first insulating layer;
step 700: doping P-impurities into the lateral epitaxy by taking the first semiconductor layer as a nucleation center to form a second semiconductor material layer;
step 800: continuing to grow a third semiconductor material layer in a lateral epitaxial mode, and removing the second semiconductor material layer and the third semiconductor material layer on the first surface of the first semiconductor layer to form a second semiconductor layer and a third semiconductor layer;
step 900: forming a fourth semiconductor layer on the first to third semiconductor layers, and forming a two-dimensional charge carrier gas at interfaces of the fourth semiconductor layer and the first to third semiconductor layers.
10. An electronic device comprising the semiconductor device according to any one of claims 1 to 9.
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| US4952526A (en) * | 1988-04-05 | 1990-08-28 | Thomson-Csf | Method for the fabrication of an alternation of layers of monocrystalline semiconducting material and layers of insulating material |
| US20050132950A1 (en) * | 2003-12-23 | 2005-06-23 | Kim Dong J. | Method of growing aluminum-containing nitride semiconductor single crystal |
| KR101250475B1 (en) * | 2011-12-26 | 2013-04-08 | 전자부품연구원 | Heterogeneous substrate having insulating material pattern and nitride-based semiconductor device using the same |
| CN105493239A (en) * | 2013-09-27 | 2016-04-13 | 英特尔公司 | Integration of iii-v devices on Si wafers |
| CN109300976A (en) * | 2018-09-29 | 2019-02-01 | 广东省半导体产业技术研究院 | Semiconductor devices and preparation method thereof |
| CN112447836A (en) * | 2019-08-30 | 2021-03-05 | 广东致能科技有限公司 | High electron mobility transistor with high voltage endurance capability |
| CN211529957U (en) * | 2019-11-14 | 2020-09-18 | 广东致能科技有限公司 | Semiconductor device and electronic device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114759080A (en) * | 2022-06-13 | 2022-07-15 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
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