CN110675836B

CN110675836B - Scanning circuit, driving method thereof and display panel

Info

Publication number: CN110675836B
Application number: CN201910996113.4A
Authority: CN
Inventors: 左亮妹; 赵虹; 赵欣; 马宏帅; 张九占; 韩珍珍
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2019-10-18
Filing date: 2019-10-18
Publication date: 2021-08-27
Anticipated expiration: 2039-10-18
Also published as: CN110675836A

Abstract

The embodiment of the invention discloses a scanning circuit, a driving method thereof and a display panel, wherein the scanning circuit comprises a first output control module, a second output control module, a first output module, a second output module, a starting signal resetting module, a first potential signal input end, a second potential signal input end, a first clock signal input end, a second clock signal input end, a third clock signal input end, a starting signal input end, a scanning signal output end, a first node and a second node; the control end of the starting signal resetting module is electrically connected with the third clock signal input end, the input end of the starting signal resetting module is electrically connected with the first potential signal input end, and the output end of the starting signal resetting module is electrically connected with the starting signal input end, so that the starting pulse signal output by the starting signal resetting module can be timely reset, and the influence on the display effect caused by the fact that the starting pulse signal corresponding to the starting signal cannot be timely reset after the driving chip outputs the starting pulse signal is avoided.

Description

Scanning circuit, driving method thereof and display panel

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a scanning circuit, a driving method thereof and a display panel.

Background

With the development of display technology, the requirements for various driving circuits in the display panel are also higher and higher.

In a conventional display panel, a driving chip and a gate driver are generally included, and a cascaded multi-stage scanning circuit is included in the gate driver, wherein the driving chip provides a start pulse signal for a primary scanning circuit of the gate driver.

However, the conventional display panel has a problem that when the driving chip supplies the start pulse signal to the primary scanning circuit, the output signal cannot be reset in time.

Disclosure of Invention

The invention provides a scanning circuit, a driving method thereof and a display panel, which are used for realizing the timely reset of a starting signal in the scanning circuit.

In a first aspect, an embodiment of the present invention provides a scan circuit, including a first output control module, a second output control module, a first output module, a second output module, a start signal resetting module, a first potential signal input end, a second potential signal input end, a first clock signal input end, a second clock signal input end, a third clock signal input end, a start signal input end, a first node, and a second node;

the first output control module comprises a first control end, a second control end, a first input end, a second input end and an output end, the first control end of the first output control module is electrically connected with the second node, the first input end of the first output control module is electrically connected with the first clock signal input end, the output end of the first output control module is electrically connected with the first node, and the first output control module is used for controlling the communication state between the first input end of the first output control module and the output end of the first output control module according to a signal input by the first control end of the first output control module; the second control end of the first output control module is electrically connected with the first clock signal input end, the second input end of the first output control module is electrically connected with the second potential signal input end, and the first output control module is further used for controlling the communication state between the second input end of the first output control module and the output end of the first output control module according to a signal input by the second control end of the first output control module;

the second output control module comprises a first control end, a second control end, a third control end, a first input end, a second input end and an output end, the first control end of the second output control module is electrically connected with the first clock signal input end, the first input end of the second output control module is electrically connected with the starting signal input end, the output end of the second output control module is electrically connected with the second node, the second control end of the second output control module is electrically connected with the second clock signal input end, the third control end of the second output control module is electrically connected with the first node, and the second input end of the second output control module is electrically connected with the first potential signal input end; the second output control module is used for controlling the communication state between the first input end of the second output control module and the output end of the second output control module according to a signal input by the first control end of the second output control module, and controlling the communication state between the second input end of the second output control module and the output end of the second output control module according to a signal input by the second control end of the second output control module and the third control end of the second output control module;

the first output module comprises a control end, an input end and an output end, the control end of the first output module is electrically connected with the first node, the input end of the first output module is electrically connected with the first potential signal input end, the output end of the first output module is electrically connected with the scanning signal output end, and the first output module is used for being switched on or switched off according to the potential of the control end of the first output module;

the second output module comprises a control end, an input end and an output end, the control end of the second output module is electrically connected with the second node, the input end of the second output module is electrically connected with the second clock signal input end, the output end of the second output module is electrically connected with the scanning signal output end, and the second output module is used for being switched on or switched off according to the potential of the control end of the second output module;

the starting signal resetting module comprises a control end, an input end and an output end, the control end of the starting signal resetting module is electrically connected with the third clock signal input end, the input end of the starting signal resetting module is electrically connected with the first potential signal input end, and the output end of the starting signal resetting module is electrically connected with the starting signal input end.

Optionally, the first output control module includes a first transistor and a second transistor, where the first transistor and the second transistor include gates, a first pole and a second pole, the gate of the first transistor is used as the first control end of the first output control module, the first pole of the first transistor is used as the first control end of the first output control module, and the second pole of the first transistor is used as the output end of the first output control module; the grid electrode of the second transistor is used as a second control end of the first output control module, the first pole of the second transistor is used as a second input end of the first output control module, and the second pole of the second transistor is electrically connected with the second pole of the first transistor.

Optionally, the second output control module includes a third transistor, a fourth transistor, and a fifth transistor, and the third transistor, the fourth transistor, and the fifth transistor each include a gate, a first pole, and a second pole;

the grid electrode of the third transistor is used as a first control end of the second output control module, the first pole of the third transistor is used as a first input end of the second output control module, and the second pole of the third transistor is used as an output end of the second output control module;

a grid electrode of the fourth transistor is used as a second control end of the second output control module, a first pole of the fourth transistor is electrically connected with a second pole of the fifth transistor, and a second pole of the fourth transistor is electrically connected with a second pole of the third transistor;

the grid electrode of the fifth transistor is used as a third control end of the second output control module, and the first pole of the fifth transistor is used as a second input end of the second output control module.

Optionally, the first output module includes a sixth transistor and a first capacitor, a gate of the sixth transistor is used as a control end of the first output module, a first pole of the sixth transistor is used as an input end of the first output module, and a second pole of the sixth transistor is used as an output end of the first output module; two ends of the first capacitor are electrically connected with the grid electrode of the sixth transistor and the first pole respectively.

Optionally, the second output module includes a seventh transistor and a second capacitor, a gate of the seventh transistor is used as a control end of the second output module, a first pole of the seventh transistor is used as an input end of the second output module, and a second pole of the seventh transistor is used as an output end of the second output module; and two ends of the second capacitor are respectively and electrically connected with the grid electrode and the second pole of the seventh transistor.

Optionally, the start signal resetting module includes an eighth transistor, a gate of the eighth transistor is used as a control end of the start signal resetting module, a first pole of the eighth transistor is used as an input end of the start signal resetting module, and a second pole of the eighth transistor is used as an output end of the start signal resetting module.

Optionally, the eighth transistor is an IGZO transistor.

Optionally, the scanning circuit further includes a ninth transistor, and the second node is electrically connected to the control end of the second output module through the ninth transistor;

the grid electrode of the ninth transistor is electrically connected with the second potential signal input end, the first electrode of the ninth transistor is electrically connected with the second node, and the second electrode of the ninth transistor is electrically connected with the control end of the second output module.

In a second aspect, an embodiment of the present invention further provides a driving method of a scanning circuit, where the scanning circuit includes a first output control module, a second output control module, a first output module, a second output module, a start signal resetting module, a first potential signal input end, a second potential signal input end, a first clock signal input end, a second clock signal input end, a third clock signal input end, a start signal input end, a first node, and a second node;

the driving method of the scanning circuit comprises the following steps:

inputting a first pulse signal to a third clock signal input end within a first preset time before a preset pulse signal is input to a starting signal input end, wherein the first pulse signal is used for controlling the starting reset control module to be conducted, and transmitting a signal input by a first potential signal input end to the starting signal input end when the starting reset control module is conducted, wherein the potential of the signal input by the first potential signal input end is opposite to that of the preset pulse signal input by the starting signal input end;

the first preset time is less than or equal to the time length corresponding to half of the pulse width of the preset pulse signal.

An embodiment of the present invention further provides a display panel, where the display panel includes the scanning circuit provided in the first aspect as a primary scanning circuit, a first clock signal line, a second clock signal line, a third clock signal line, a first potential signal line, a second potential signal line, and a start signal line;

the display panel also comprises at least one secondary scanning circuit, wherein the secondary scanning circuit comprises a third output control module, a fourth output control module, a third output module, a fourth output module, a third potential signal input end, a fourth clock signal input end, a fifth clock signal input end, a shift signal input end, a third node and a fourth node;

a first clock signal input end of the primary scanning circuit and a fourth clock signal input end of the secondary scanning circuit are electrically connected with a first clock signal line, a second clock signal input end of the primary scanning circuit and a fifth clock signal input end of the secondary scanning circuit are both electrically connected with a second clock signal line, a third clock signal input end of the primary scanning circuit is electrically connected with a third clock signal line, a first potential signal input end of the primary scanning circuit and a third potential signal input end of the secondary scanning circuit are both electrically connected with a first potential signal line, and a second potential signal input end of the primary scanning circuit and a fourth potential signal input end of the secondary scanning circuit are both electrically connected with a second potential signal line; the starting signal input end of the primary scanning circuit is electrically connected with the starting signal wire;

the shift signal input end of a first-stage scanning circuit in the secondary scanning circuit is electrically connected with the scanning signal output end of the primary scanning circuit; and in any two adjacent stages of scanning circuits in the secondary scanning circuits, the shift signal input end of the next-stage secondary scanning circuit is electrically connected with the scanning signal output end of the previous-stage scanning circuit.

The embodiment of the invention provides a scanning circuit, a driving method thereof and a display panel, wherein the scanning circuit comprises a starting signal resetting module, the starting signal resetting module comprises a control end, an input end and an output end, the control end of the starting signal resetting module is electrically connected with a third clock signal input end, the input end of the starting signal resetting module is electrically connected with a first potential signal input end, and the output end of the starting signal resetting module is electrically connected with a starting signal input end, so that the starting pulse signal output by the starting signal resetting module can be timely reset, and the influence on the display effect caused by the fact that the driving chip cannot be timely reset after outputting the pulse signal corresponding to the starting signal is avoided.

Drawings

Fig. 1 is a schematic structural diagram of a scan circuit according to an embodiment of the present invention;

FIG. 2 is a timing diagram of a scan circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a conventional pixel circuit in the prior art;

FIG. 4 is a timing diagram illustrating operation of the pixel circuit shown in FIG. 3;

FIG. 5 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another scan circuit according to an embodiment of the present invention;

fig. 12 is a timing diagram of driving another scan circuit according to an embodiment of the present invention;

fig. 13 is a flowchart of a driving method of a scan circuit according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of a sub-scanning circuit according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional display panel has a problem that when the driving chip provides the start pulse signal to the scanning circuit, the output signal cannot be reset in time. The inventor has found that the above problem occurs because, in the conventional display panel, the driving chip generally includes a plurality of pins, the driving chip outputs the driving signal through each pin, and each pin is connected to the corresponding circuit of the display panel through a signal line. The signal line is usually bonded to the pin of the driving chip, a multi-layer insulating layer is usually included between the signal line and the pin of the driving chip, and a conductive substance (e.g., metal) needs to be connected to the signal line and the pin of the driving chip through a via penetrating through the multi-layer insulating layer. However, under the environment of high temperature and high humidity, some connecting wires inside the display screen are easy to be corroded due to the fact that water vapor is easily invaded, meanwhile, an organic layer which is difficult to remove in the process is remained between the insulating layers, the adhesion force between the insulating layers is reduced due to the organic layer under the environment of high temperature and high humidity, film separation between the insulating layers is easy to occur, and then conductive materials for connecting the signal wires and pins of the driving chip are easily induced to be separated from the pins of the driving chip, and therefore signal contact resistance is increased. The start signal of the primary scanning circuit of the gate driver (i.e., the first stage scanning circuit in the gate driver) is provided by the driving chip, and the pulse signal output by the driving chip is delayed due to the separation or loose contact between the pin of the driving chip providing the start signal and the signal line, so that the driving chip cannot reset in time after outputting the pulse signal corresponding to the start signal, thereby affecting the display effect.

In view of the above reasons, fig. 1 is a schematic structural diagram of a SCAN circuit according to an embodiment of the present invention, and referring to fig. 1, the SCAN circuit includes a first output control module 110, a second output control module 120, a first output module 130, a second output module 140, a start signal reset module 150, a first voltage signal input terminal VGH, a second voltage signal input terminal VGL, a first clock signal input terminal CK1, a second clock signal input terminal CK2, a third clock signal input terminal CK3, a start signal input terminal SIN, a SCAN signal output terminal SCAN, a first node N1, and a second node N2;

the first output control module 110 includes a first control terminal a1, a second control terminal a2, a first input terminal B1, a second input terminal B2 and an output terminal C1, the first control terminal a1 of the first output control module 110 is electrically connected to the second node N2, the first input terminal B1 of the first output control module 110 is electrically connected to the first clock signal input terminal CK1, the output terminal C1 of the first output control module 110 is electrically connected to the first node N1, and the first output control module 110 is configured to control a communication state between the first input terminal B1 of the first output control module 110 and the output terminal C1 of the first output control module 110 according to a signal input from the first control terminal a1 of the first output control module 110; the second control terminal a2 of the first output control module 110 is electrically connected to the first clock signal input terminal CK1, the second input terminal B2 of the first output control module 110 is electrically connected to the second potential signal input terminal VGL, and the first output control module 110 is further configured to control a communication state between the second input terminal B2 of the first output control module 110 and the output terminal C1 of the first output control module 110 according to a signal input from the second control terminal a2 of the first output control module 110;

the second output control module 120 includes a first control terminal D1, a second control terminal D2, a third control terminal D3, a first input terminal E1, a second input terminal E2 and an output terminal F1, the first control terminal D1 of the second output control module 120 is electrically connected to the first clock signal input terminal CK1, the first input terminal E1 of the second output control module 120 is electrically connected to the enable signal input terminal SIN, the output terminal F1 of the second output control module 120 is electrically connected to the second node N2, the second control terminal D2 of the second output control module 120 is electrically connected to the second clock signal input terminal CK2, the third control terminal D3 of the second output control module 120 is electrically connected to the first node N1, and the second input terminal E2 of the second output control module 120 is electrically connected to the first potential signal input terminal VGH; the second output control module 120 is used for controlling a communication state between the first input terminal E1 of the second output control module 120 and the output terminal F1 of the second output control module 120 according to a signal input from the first control terminal D1 of the second output control module 120, and for controlling a communication state between the second input terminal E2 of the second output control module 120 and the output terminal F1 of the second output control module 120 according to a signal input from the second control terminal D2 of the second output control module 120 and the third control terminal D3 of the second output control module 120;

the first output module 130 includes a control terminal, an input terminal, and an output terminal, the control terminal of the first output module 130 is electrically connected to the first node N1, the input terminal of the first output module 130 is electrically connected to the first potential signal input terminal VGH, the output terminal of the first output module 130 is electrically connected to the SCAN signal output terminal SCAN, and the first output module 130 is configured to be turned on or off according to a potential of the control terminal of the first output module 130;

the second output module 140 includes a control terminal, an input terminal, and an output terminal, the control terminal of the second output module 140 is electrically connected to the second node N2, the input terminal of the second output module 140 is electrically connected to the second clock signal input terminal CK2, the output terminal of the second output module 140 is electrically connected to the SCAN signal output terminal SCAN, and the second output module 140 is configured to be turned on or off according to a potential of the control terminal of the second output module 140;

the start signal reset module 150 includes a control terminal, an input terminal and an output terminal, the control terminal of the start signal reset module 150 is electrically connected to the third clock signal input terminal CK3, the input terminal of the start signal reset module 150 is electrically connected to the first potential signal input terminal VGH, and the output terminal of the start signal reset module 150 is electrically connected to the start signal input terminal SIN.

Fig. 2 is a driving timing diagram of a scan circuit according to an embodiment of the present invention, where the driving timing of the scan circuit can be used to drive the scan circuit shown in fig. 1, and referring to fig. 1 and fig. 2, the operation timing of the scan circuit includes three stages. The following description will be given taking as an example that the signal input from the first voltage signal input terminal VGH is at a high voltage level, the signal input from the second voltage signal input terminal VGL is at a low voltage level, and the signal input from the first clock signal input terminal CK1, the signal input from the second clock signal input terminal CK2, the signal input from the third clock signal input terminal CK3, and the signal input from the enable signal input terminal SIN are at a low voltage level.

In the first period t1, the enable signal input terminal SIN inputs a low-level signal, the first clock signal input terminal CK1 inputs a low-level signal, and the second clock signal input terminal CK2 inputs a high-level signal. The second control terminal a2 of the first output control module 110 is electrically connected to the first clock signal input terminal CK1, so that the second control terminal a2 of the first output control module 110 inputs a low-potential signal, the first output control module 110 controls the communication between the second input terminal B2 of the first output control module 110 and the output terminal C1 of the first output control module according to the low-potential signal input by the second control terminal a2, so that the low-potential signal input by the second input terminal B2 of the first output control module 110 is transmitted to the output terminal C1 of the first output control module 110, the output terminal C1 of the first output control module 110 is electrically connected to the first node N1, so that the first node N1 is at a low potential, the first output module 130 is turned on according to the low-potential signal of its own control terminal, and transmits the high-potential signal input by the first potential signal input terminal VGH to the output terminal of the first output module 130, the output terminal of the first output module 130 is connected to the SCAN signal output terminal SCAN, so that the SCAN signal output terminal SCAN outputs a high voltage signal.

The first control terminal D1 of the second output control module 120 is electrically connected to the first clock signal input terminal CK1, so that the second output control module 120 controls the communication between the first input terminal E1 of the second output control module 120 and the output terminal F1 of the second output control module 120 according to the low-potential signal inputted from its own first control terminal D1, and the first input terminal E1 of the second output control module 120 is electrically connected to the enabling signal input terminal SIN, so that the low-potential signal inputted from the first input terminal E1 of the second output control module 120 is transmitted to the output terminal F1 of the second control module and further transmitted to the second node N2, that is, the second node N2 is low-potential; the control terminal of the second output module 140 is electrically connected to the second node N2, so that the second output module 140 is turned on according to the low potential signal of the second node N2, which is electrically connected to its control terminal, and further outputs the high potential signal inputted from the second clock signal input terminal CK2 to the SCAN signal output terminal SCAN through the second output module 140, and the potential outputted from the SCAN signal output terminal SCAN is a high potential signal. The second control terminal D2 of the second output control module 120 is electrically connected to the second clock signal input terminal CK2, so that a high potential signal is input to the second control terminal D2 of the second output control module 120, the second output control module 120 controls the connection state between the second input terminal E2 of the second output control module 120 and the output terminal F1 of the second output control module 120 according to the second control terminal D2 and the third control terminal D3, and the connection between the second input terminal E2 and the output terminal F1 of the second output control module 120 is enabled only when the potentials input to the second control terminal D2 and the third control terminal D3 of the second output control module 120 are both low potential signals, so that the second input terminal E2 and the output terminal F1 of the second output control module 120 are disconnected during the first period t 1.

Moreover, since the second node N2 is at a low potential, the first output control module 110 controls the first input terminal B1 of the first output control module 110 and the output terminal C1 of the first output control module 110 to be conducted according to a low potential signal of the first control terminal a1 thereof, so that the low potential signal inputted from the first clock signal input terminal CK1 is transmitted to the first node N1.

With reference to fig. 1 and fig. 2, in the latter half of the first period t1, the third clock signal input terminal CK3 inputs a low-potential pulse signal, and the control terminal of the start signal reset module 150 is electrically connected to the third clock signal input terminal CK3, so that the start signal reset module 150 responds to the low-potential signal input by the control terminal thereof to be turned on, and the high-potential signal input by the first potential signal input terminal VGH is transmitted to the start signal input terminal SIN, so that the low-potential signal input by the start signal input terminal SIN can be timely reset to a high-potential signal, thereby improving the display effect, avoiding the delay of the start pulse signal output by the driver chip due to the separation or loose contact between the driver chip pin and the signal line, and causing the problem that the driver chip cannot be timely reset after outputting the pulse signal corresponding to the start signal, and affecting the display effect, that is to correct the signal input by the start signal reset module 150 in time, thereby ensuring the reliability of the scanning circuit for outputting the scanning signal.

The potential of the input signal of the first potential signal input terminal VGH is opposite to the potential of the pulse signal input by the start signal input terminal SIN, so that when the start signal reset module 150 is turned on, the pulse signal input by the start signal input terminal can be timely reset by the signal input by the first potential signal input terminal VGH. For example, in the present embodiment, the pulse signal input from the start signal input terminal SIN is at a low potential, and the potential of the input signal from the first potential signal input terminal VGH is at a high potential, but the above embodiment is not a limitation to the present invention, and in other embodiments, the pulse signal input from the start signal input terminal SIN may be at a high potential, and the potential input from the first potential signal input terminal VGH may be at a low potential.

In the second phase t2, the signal inputted from the enable signal input terminal SIN is reset to a high level signal, the first clock signal input terminal CK1 inputs a high level pulse signal, and the second clock signal input terminal CK2 inputs a low level pulse signal. The second control terminal a2 of the first output control module 110 is electrically connected to the first clock signal input terminal CK1, so that the second control terminal a2 of the first output control module 110 inputs a high-voltage signal, and the first output control module 110 controls the second input terminal B2 to be disconnected from the output terminal C1 of the first output control module 110 according to the high-voltage signal input from the second control terminal a2, so that the low-voltage signal input from the second input terminal B2 of the first output control module 110 cannot be transmitted to the output terminal C1 of the first output control module 110. Since the second output module 140 stores and maintains the potential of its own control terminal, the second node N2 maintains the low potential of the previous stage, and accordingly, the potential of the first control terminal a1 of the first output control module 110 is low potential, so that the first input terminal a1 of the first output control module 110 and the output terminal C1 of the first output control module 110 are connected, the high potential signal input by the first potential signal input terminal VGH is transmitted to the first node N1, and the first output module 130 is turned off according to the high potential input by its control terminal.

The first control terminal D1 of the second output control module 120 is electrically connected to the first clock signal input terminal CK1, so that the second output control module 120 controls the first input terminal E1 of the second output control module 120 and the output terminal F1 of the second output module 140 to be disconnected according to the high-level signal inputted from its own first control terminal D1; the second control terminal D2 of the second output control module 120 is electrically connected to the second clock signal input terminal CK2, so that a low-potential signal is input to the second control terminal D2 of the second output control module 120, and the third control terminal D3 of the second output control module 120 is at the same potential as the first node N1, i.e., at a high potential, because only when the potentials input to the second control terminal D2 and the third control terminal D3 of the second output control module 120 are both low-potential signals, the second input terminal E2 and the output terminal F1 of the second output control module 120 can be turned on, and therefore, in the second stage t2, the second input terminal E2 and the output terminal F1 of the second output control module 120 are turned off, i.e., in the second stage t2, the first input terminal E1 and the second input terminal E2 of the second output control module 120 cannot transmit signals to the output terminal F1 of the second output control module 120.

Because the control terminal of the second output module 140 is electrically connected to the second node N2, the second output module 140 keeps the low potential at the second node N2 due to the storage and holding function of the second output module 140 on the potential of its own control terminal, the second output module 140 is turned on according to the low potential signal at the second node N2 connected to its own control terminal, and then the low potential signal inputted from the second clock signal input terminal CK2 is outputted to the SCAN signal output terminal SCAN through the second output module 140, and the potential outputted from the SCAN signal output terminal SCAN is the low potential signal. That is, in the second stage t2, the SCAN signal output terminal SCAN outputs the same signal as the second clock signal input terminal CK2 inputs.

After entering the third stage t3, the first clock signal input terminal CK1 inputs a low-level signal, and the second clock signal input terminal CK2, the third clock signal input terminal CK3, and the start signal input terminal SIN all input a high-level signal. The second control terminal a2 of the first output control module 110 is electrically connected to the first clock signal input terminal CK1, so that the second control terminal a2 of the first output control module 110 inputs a low-potential signal, and the first output control module 110 controls the communication between the second input terminal B2 and the output terminal C1 according to the low-potential signal input by the second control terminal a2, so that the low-potential signal input by the second input terminal B2 of the first output control module 110 is transmitted to the output terminal C1 of the first output control module 110, and accordingly, the first node N1 is at a low potential; the first output module 130 is turned on according to the low voltage level of the control terminal thereof, and transmits the high voltage level inputted from the first voltage level input terminal VGH to the SCAN signal output terminal SCAN.

The low-level signal inputted from the first control terminal D1 of the second output control module 120 controls the communication between the first input terminal E1 of the second output control module 120 and the output terminal F1 of the second output control module 120, so that the high-level signal inputted from the start signal input terminal SIN is transmitted from the first input terminal E1 of the second output control module 120 to the output terminal F1 of the second output control module 120, and accordingly, the level of the second node N2 is high; since the signal inputted from the second control terminal D2 of the second output control module 120 is at a high level and the third control terminal of the second output control module 120 is at a low level, which is the same as the first node N1, only when the potentials inputted from the second control terminal D2 and the third control terminal D3 of the second output control module 120 are both at a low level, the second input terminal E2 and the output terminal F1 of the second output control module 120 can be turned on, so that, in the third stage t3, the second input terminal E2 of the second output control module 120 is turned off from the output terminal F1 when the first clock signal input terminal CK1 inputs a low level signal and the second clock signal input terminal CK2, the third clock signal input terminal CK3 and the scan signal input terminal all input a high level signal. The second node N2 is at a high level, so the second output module 140 is turned off according to the high signal at its own control terminal. That is, in the third stage t3, when the low potential signal is inputted to the first clock signal input terminal CK1, and the high potential signals are inputted to the second clock signal input terminal CK2, the third clock signal input terminal CK3, and the SCAN signal input terminal, the SCAN signal output terminal SCAN outputs the high potential signal, which is the same as the potential inputted to the first potential signal input terminal VGH.

In the third stage t3, when the second clock signal input terminal CK2 inputs a low-level pulse signal, the first clock signal input terminal CK1, the third clock signal input terminal CK3 and the enable signal input terminal SIN all input a high-level signal. The second control terminal a2 of the first output control module 110 is electrically connected to the first clock signal input terminal CK1, so that the second control terminal a2 of the first output control module 110 inputs a high-level signal, and the first output control module 110 controls the second input terminal B2 of the first output control module 110 to be disconnected from the output terminal C1 of the first output control module 110 according to the high-level signal input by the second control terminal a2, so that the low-level signal input by the second input terminal B2 of the first output control module 110 cannot be transmitted to the output terminal C1 of the first output control module 110. However, the first node N1 keeps low level due to the storage and holding function of the first output control module 110 on the self control terminal voltage, accordingly, the first output module 130 is turned on, and the high voltage inputted from the first voltage input terminal VGH is transmitted to the SCAN signal output terminal SCAN.

The high-level signal inputted from the first control terminal D1 of the second output control module 120 controls the first input terminal E1 of the second output control module 120 and the output terminal F1 of the second output control module 120 to be turned off; since the signal inputted from the second control terminal D2 of the second output control module 120 is low-level, and the third control terminal D3 of the second output control module 120 is the same as the first node N1, i.e. low-level, only when the potentials inputted from the second control terminal D2 and the third control terminal D3 of the second output control module 120 are both low-level signals, the connection between the second input terminal E2 and the output terminal F1 of the second output control module 120 is enabled, when a low-level pulse signal is inputted corresponding to the second clock signal input terminal CK2 in the third stage t3, the second input terminal E2 of the second output control module 120 is in time communication with the output terminal F1 when a high-level signal is inputted from the first clock signal input terminal CK1, the third clock signal input terminal CK3 and the enable signal input terminal SIN, and the high-level signal inputted from the first potential signal input terminal VGH is transmitted from the second output terminal E2 of the second output control module 120 to the output terminal F1 of the second output control module 120, further, the signal is transmitted to the second node N2, i.e., the second node N2 is high, so that the second output module 140 is turned off according to the high signal of its own control terminal. That is, in the third stage t3, when the second clock signal input terminal CK2 inputs a low level pulse signal, and when the first clock signal input terminal CK1, the third clock signal input terminal CK3 and the enable signal input terminal SIN all input high level signals, the SCAN signal output terminal SCAN outputs a high level signal, which is the same as the potential input by the first level signal input terminal VGH.

In the above embodiment, the low potential pulse signal is input to the third clock signal input terminal CK3 in the second half of the first phase t1, and specifically, the first phase t1 may be equally divided into a first sub-phase and a second sub-phase in terms of time, where the first sub-phase is a relatively earlier phase in time, the second sub-phase is a relatively later phase in time, and the low potential pulse signal is input to the third clock signal input terminal CK3 at any time in all times in the second sub-phase.

Fig. 3 is a schematic structural diagram of a conventional pixel circuit in the prior art, and fig. 4 is an operation timing diagram corresponding to the pixel circuit shown in fig. 3, and referring to fig. 3 and 4, the pixel circuit includes a data signal input terminal Vdata, a first scan signal input terminal S1(N), a second scan signal input terminal S2(N), an initialization signal input terminal Vref, a light emitting control signal input terminal em (N), a high level signal input terminal VDD, and a low level signal input terminal VSS, and a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a driving transistor DT, and other transistors and light emitting devices shown in fig. 3, wherein the light emitting devices may be organic light emitting devices. Fig. 3 illustrates an example in which each transistor is a P-type transistor. Referring to fig. 3 and 4, the signal inputted from the first scan signal input terminal S1(N) can be provided by the scan circuit provided in this embodiment, and the signal inputted from the initialization signal input terminal Vref is usually a lower potential signal. The low level signal inputted from the first scan signal input terminal S1(N) and the low level signal inputted from the emission control signal input terminal em (N) cannot overlap with each other because the overlap will make the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 turn on simultaneously, so that the signal inputted from the initialization signal input terminal Vref is transmitted to the gate of the driving transistor DT through the tenth transistor T10, the driving transistor DT turns on, and a very large current will flow between the high level signal input terminal and the VDD and low level signal input terminal VSS through the light emitting device, causing display abnormality and affecting the display life. For example, when the enable signal reset block 150 is not provided in the scan circuit, the pulse signal input from the enable signal input terminal SIN may continue to the second pulse signal input from the first clock signal input terminal CK1 or to the nth pulse signal input from the first clock signal input terminal CK1, where N >2, so that the signal input from the scan circuit to the first scan signal input terminal S1(N) may overlap with the signal input from the emission control signal input terminal em (N) of the pixel circuit.

In this embodiment, the scan circuit is configured to include the start signal reset module 150, so that the start signal is reset in time, the influence on the display effect caused by the failure of the start signal to reset in time is avoided, and the problem of large current between the high potential signal input terminal VDD and VSS in the pixel circuit is avoided.

It should be noted that the scan circuit provided in this embodiment is not only suitable for providing the scan signal to the pixel circuit shown in fig. 3, but also suitable for pixel circuits where the scan signal and the light-emitting control signal cannot overlap.

According to the scanning circuit provided by the embodiment of the invention, the scanning circuit is arranged to comprise the starting signal resetting module, the starting signal resetting module comprises the control end, the input end and the output end, the control end of the starting signal resetting module is electrically connected with the third clock signal input end, the input end of the starting signal resetting module is electrically connected with the first potential signal input end, and the output end of the starting signal resetting module is electrically connected with the starting signal input end, so that the starting pulse signal output by the starting signal resetting module can be timely reset, and the influence on the display effect caused by the fact that the display effect cannot be timely reset after the driving chip outputs the pulse signal corresponding to the starting signal is avoided.

It should be noted that, in the above embodiments, it is exemplarily shown that the signal input from the first potential signal input terminal VGH is a high potential signal, the signal input from the second potential signal input terminal VGL is a low potential signal, and the signal input from the first clock signal input terminal CK1, the signal input from the second clock signal input terminal CK2, the signal input from the third clock signal input terminal CK3, and the signal input from the enable signal input terminal SIN are all low potential signals, which is not limited to the present invention. In other embodiments, the signal inputted from the first voltage signal input terminal VGH may be a low voltage signal, the signal inputted from the second voltage signal input terminal CK2 may be a high voltage signal, and the signal inputted from the first clock signal input terminal CK1, the signal inputted from the second clock signal input terminal CK2, the signal inputted from the third clock signal input terminal CK3, and the signal inputted from the enable signal input terminal SIN are all enabled at a high voltage level. In practical application, the setting can be carried out according to the requirement.

Fig. 5 is a schematic structural diagram of another scan circuit provided in the embodiment of the present invention, and referring to fig. 5, optionally, the first output control module 110 includes a first transistor T1 and a second transistor T2, each of the first transistor T1 and the second transistor T2 includes a gate, a first pole and a second pole, the gate of the first transistor T1 is used as the first control terminal a1 of the first output control module 110, the first pole of the first transistor T1 is used as the first input terminal B1 of the first output control module 110, and the second pole of the first transistor T1 is used as the output terminal C1 of the first output control module 110; the gate of the second transistor T2 is used as the second control terminal a2 of the first output control module 110, the first pole of the second transistor T2 is used as the second input terminal B2 of the first output control module 110, and the second pole of the second transistor T2 is electrically connected to the second pole of the first transistor T1.

The first transistor T1 is turned on or off according to the potential of the second node N2 connected to the gate thereof, and transmits a signal input from the first clock signal input terminal CK1 to the first node N1 when turned on; the second transistor T2 is turned on or off according to a signal input from the first clock signal input terminal CK1, which is connected to a gate thereof, and transmits a signal input from the second potential signal input terminal VGL to the first node N1 when turned on. The first transistor T1 and the second transistor T2 may be P-type transistors or N-type transistors. For example, when the first transistor T1 and the second transistor T2 are P-type transistors, the first transistor T1 is turned on when the potential of the second node N2 is low, and the second transistor T2 is turned on when the signal input from the first clock signal input terminal CK1 is a low-potential signal. The first transistor T1 and the second transistor T2 can control the potential of the first node N1, so as to control the on or off state of the first output module 130, thereby implementing the output control of the scan signal.

In addition, the transistor is simple in structure and simple in manufacturing process. When the scanning circuit is applied to the display panel, the transistor in the scanning circuit and the transistor on the display panel can be manufactured in the same process flow, so that the process flow is saved, and the cost is reduced.

Fig. 6 is a schematic structural diagram of another scan circuit according to an embodiment of the present invention, and referring to fig. 6, optionally, the second output control module 120 includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5, and each of the third transistor T3, the fourth transistor T4, and the fifth transistor T5 includes a gate, a first pole, and a second pole;

a gate of the third transistor T3 is used as the first control terminal D1 of the second output control module 120, a first pole of the third transistor T3 is used as the first input terminal E1 of the second output control module 120, and a second pole of the third transistor T3 is used as the output terminal F1 of the second output control module 120;

a gate of the fourth transistor T4 is used as the second control terminal D2 of the second output control module 120, a first pole of the fourth transistor T4 is electrically connected to a second pole of the fifth transistor T5, and a second pole of the fourth transistor T4 is electrically connected to a second pole of the third transistor T3;

the gate of the fifth transistor T5 serves as the third control terminal D3 of the second output control module 120, and the first pole of the fifth transistor T5 serves as the second input terminal E2 of the second output control module 120.

The third transistor T3 is turned on or off according to a signal input from the first clock signal input terminal CK1 electrically connected to the gate thereof, and transmits a start signal input from the start signal input terminal SIN to the second node N2 when turned on; the fourth transistor T4 is turned on or off according to a signal input from the second clock signal input terminal CK2 electrically connected to a gate thereof, the fifth transistor T5 is turned on or off according to a potential of the first node N1 electrically connected to a gate thereof, and a signal input from the first potential signal input terminal VGH is transmitted to the second node N2 when the fourth transistor T4 and the fifth transistor T5 are simultaneously turned on. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 can control the potential of the second node N2, so as to control the on or off state of the second output module 140, thereby implementing the output control of the scan signal.

Fig. 7 is a schematic structural diagram of another scan circuit according to an embodiment of the present invention, and referring to fig. 7, optionally, the first output module 130 includes a sixth transistor T6 and a first capacitor Cst1, a gate of the sixth transistor T6 is used as a control terminal of the first output module 130, a first pole of the sixth transistor T6 is used as an input terminal of the first output module 130, and a second pole of the sixth transistor T6 is used as an output terminal of the first output module 130; both ends of the first capacitor Cst1 are electrically connected to the gate and the first pole of the sixth transistor T6, respectively.

The sixth transistor T6 is turned on or off according to the potential of the first node N1 electrically connected to the gate thereof, and transmits the potential signal inputted from the first potential signal input terminal VGH to the SCAN signal output terminal SCAN when turned on, and the first capacitor Cst1 can store the potentials of the gate and the first electrode of the sixth transistor T6. The first output module 130 including the sixth transistor T6 and the first capacitor Cst1 is arranged to effectively control the SCAN signal output terminal SCAN to output the SCAN signal.

Fig. 8 is a schematic structural diagram of another scan circuit according to an embodiment of the present invention, and referring to fig. 8, optionally, the second output module 140 includes a seventh transistor T7 and a second capacitor Cst2, a gate of the seventh transistor T7 serves as a control terminal of the second output module 140, a first pole of the seventh transistor T7 serves as an input terminal of the second output module 140, and a second pole of the seventh transistor T7 serves as an output terminal of the second output module 140; both ends of the second capacitor Cst2 are electrically connected to the gate and the second pole of the seventh transistor T7, respectively.

The seventh transistor T7 is turned on or off according to the potential of the second node N2, to which a gate is electrically connected, and transmits a signal input from the second clock signal input terminal CK2 to the SCAN signal output terminal SCAN when turned on. The second capacitor Cst2 may store the potential of the gate and the second pole of the seventh transistor T7. The second output module 140 including the seventh transistor T7 and the second capacitor Cst2 is provided to achieve effective control of the SCAN signal output terminal SCAN outputting the SCAN signal.

Fig. 9 is a schematic structural diagram of another scan circuit according to an embodiment of the present invention, and referring to fig. 9, the enable signal resetting module 150 includes an eighth transistor T8, a gate of the eighth transistor T8 is used as a control terminal of the enable signal resetting module 150, a first pole of the eighth transistor T8 is used as an input terminal of the enable signal resetting module 150, and a second pole of the eighth transistor T8 is used as an output terminal of the enable signal resetting module 150.

The eighth transistor T8 is turned on or off according to a signal inputted from the third clock signal input terminal CK3 electrically connected to the gate thereof, and transmits a signal inputted from the first potential signal input terminal VGH to the enable signal input terminal SIN when the eighth transistor T8 is turned on, so that the signal inputted from the enable signal input terminal SIN is timely reset. The start signal reset module 150 includes an eighth transistor T8, so that the signal input by the start signal input terminal SIN can be reset in time, the reliability of the scan circuit is improved, and the scan signal output by the scan circuit and the light emitting control signal in the pixel circuit are not overlapped, thereby ensuring a good display effect.

With continued reference to fig. 9, based on the above technical solution, optionally, the eighth transistor T8 is an IGZO transistor.

Specifically, the IGZO transistor has a smaller leakage current, and the eighth transistor T8 is an IGZO transistor, which can reduce the leakage current, so that the scanning circuit is more stable and reliable, and the reliability of the scanning circuit is further improved.

Fig. 10 is a schematic structural diagram of another scan circuit according to an embodiment of the present invention, and referring to fig. 10, the scan circuit further includes a ninth transistor T9, and the second node N2 is electrically connected to the control terminal of the second output module 140 through the ninth transistor T9;

a gate of the ninth transistor T9 is electrically connected to the second potential signal input terminal VGL, a first electrode of the ninth transistor T9 is electrically connected to the second node N2, and a second electrode of the ninth transistor T9 is electrically connected to the control terminal of the second output module 140.

Specifically, the gate of the ninth transistor T9 is electrically connected to the second potential signal input terminal VGL, where the signal inputted from the second potential signal input terminal VGL is a signal for turning on the ninth transistor T9, for example, when the ninth transistor T9 is a P-type transistor, the signal inputted from the second potential signal input terminal VGL is a low-level signal. The ninth transistor T9 is always in a conducting state, and may generate a voltage drop when a signal output from the output terminal of the second output control module 120 passes through the ninth transistor T9, so as to protect devices in the second output module 140, and reduce the probability that the devices in the second output module 140 are broken down and damaged.

Fig. 11 is a schematic structural diagram of another scan circuit according to an embodiment of the present invention, and referring to fig. 11, the first output control module 110 includes a first transistor T1 and a second transistor T2, the second output control module 120 includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5, the first output module 130 includes a sixth transistor T6 and a first capacitor Cst1, the second output module 140 includes a seventh transistor T7 and a second capacitor Cst2, the start signal reset module 150 includes an eighth transistor T8, and the scan circuit further includes a ninth transistor T9;

a gate of the first transistor T1 is electrically connected to the second node N2, a first pole of the first transistor T1 is electrically connected to the first clock signal input terminal CK1, and a second pole of the first transistor T1 is electrically connected to the first node N1; a gate of the second transistor T2 is electrically connected to the first clock signal input terminal CK1, a first pole of the second transistor T2 is electrically connected to the second potential signal input terminal VGL, and a second pole of the second transistor T2 is electrically connected to the first node N1;

a gate of the third transistor T3 is electrically connected to the first clock signal input terminal CK1, a pole of the third transistor T3 is electrically connected to the enable signal input terminal SIN, and a second pole of the third transistor T3 is electrically connected to the second node N2; a gate of the fourth transistor T4 is electrically connected to the second clock signal input terminal CK2, a first pole of the fourth transistor T4 is electrically connected to a second pole of the fifth transistor T5, and a second pole of the fourth transistor T4 is electrically connected to a second pole of the third transistor T3; a gate of the fifth transistor T5 is electrically connected to the first node N1, and a first pole of the fifth transistor T5 is electrically connected to the first potential signal input terminal VGH;

a gate of the sixth transistor T6 is electrically connected to the first node N1, a first pole of the sixth transistor T6 is electrically connected to the first potential signal input terminal VGH, a second pole of the sixth transistor T6 is electrically connected to the SCAN signal output terminal SCAN, and both ends of the first capacitor Cst1 are electrically connected to the gate and the first pole of the sixth transistor T6, respectively;

a gate of the seventh transistor T7 is electrically connected to the second node N2, a first pole of the seventh transistor T7 is electrically connected to the second clock signal input terminal CK2, and a second pole of the seventh transistor T7 is electrically connected to the SCAN signal output terminal SCAN;

the gate of the eighth transistor T8 is electrically connected to the third clock signal input terminal CK3, the first pole of the eighth transistor T8 is electrically connected to the first potential signal input terminal VGH, and the second pole of the eighth transistor T8 is electrically connected to the enable signal input terminal SIN.

Fig. 12 is a timing diagram of another driving of the scan circuit according to the embodiment of the present invention, and the timing diagram of fig. 12 is applicable to the scan circuit shown in fig. 11, specifically, when the eighth transistor T8 is an IGZO transistor, the eighth transistor T8 is usually an N-type transistor, and referring to fig. 11 and 12, the timing diagram of the scan circuit includes three stages, where the following eighth transistor T8 is an N-type transistor, and the other transistors except the eighth transistor T8 are P-type transistors, which are described as an example, and only different from the timing diagram shown in fig. 2 is that the signal input from the third clock signal input terminal CK3 is active at a high level. Referring to fig. 11 and 12, the operation timing of the scanning circuit shown in fig. 11 is as follows:

in the first period t1, the enable signal input terminal SIN inputs a low-level signal, the first clock signal input terminal CK1 inputs a low-level signal, and the second clock signal input terminal CK2 inputs a high-level signal. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal CK1, so that the gate of the second transistor T2 inputs a low-potential signal, the second transistor T2 is turned on, and the low-potential signal input by the first pole of the second transistor T2 is transmitted to the first node N1, so that the first node N1N1 is at a low potential, the sixth transistor T6 is turned on according to the low-potential signal of the gate thereof, and transmits the high-potential signal input by the first potential signal input terminal VGH to the SCAN signal output terminal SCAN of the sixth transistor T6, so that the SCAN signal output terminal SCAN outputs a high-potential signal.

The gate of the third transistor T3 is electrically connected to the first clock signal input terminal CK1, so that the third transistor T3 is turned on according to the low-potential signal inputted from the gate thereof, and the first pole of the third transistor T3 is electrically connected to the enable signal input terminal SIN, so that the low-potential signal inputted from the enable signal input terminal SIN is transmitted to the second node N2; the gate of the seventh transistor T7 is electrically connected to the second node N2, so that the seventh transistor T7 is turned on according to the low-level signal at the gate thereof, and the high-level signal inputted from the second clock signal input terminal CK2 is outputted to the SCAN signal output terminal SCAN through the seventh transistor T7, and the potential outputted from the SCAN signal output terminal SCAN is the high-level signal. The gate of the fourth transistor T4 is electrically connected to the second clock signal input terminal CK2, and therefore, a high potential signal is input to the gate of the fourth transistor T4, and the fourth transistor T4 is turned off according to the high potential of the gate thereof. As described above, the potential of the first node N1 is low, so the potential of the gate of the fifth transistor T5 is low, and the fifth transistor T5 is turned on according to the low potential of the gate thereof, but the high potential signal inputted from the first potential signal input terminal VGH cannot be transmitted to the second node N2 because the fourth transistor T4 is turned off at this stage.

As described above, since the second node N2 is at a low potential, the first transistor T1 is turned on according to the low potential signal of the second node N2 connected to the gate thereof, so that the low potential signal inputted from the first clock signal input terminal CK1 is transmitted to the first node N1.

With reference to fig. 1 and fig. 2, in the latter half of the first period T1, a high-level pulse signal is input from the third clock signal input terminal CK3, and the control terminal of the eighth transistor T8 is electrically connected to the third clock signal input terminal CK3, so that the eighth transistor T8 is turned on in response to the high-level signal input from the gate thereof, and the high-level signal input from the first level signal input terminal VGH is transmitted to the start signal input terminal SIN, so that the low-level signal input from the start signal input terminal SIN can be reset to the high-level signal in time, thereby improving the display effect, and avoiding the delay of the start pulse signal output by the driver chip due to the loose contact or separation between the pin of the driver chip and the signal line, which causes the problem that the driver chip cannot reset in time after outputting the pulse signal corresponding to the start signal, and affects the display effect.

In the second phase t2, the signal inputted from the enable signal input terminal SIN is reset to a high level signal, the first clock signal input terminal CK1 inputs a high level signal, and the second clock signal input terminal CK2 inputs a low level pulse signal. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal CK1, so that the gate of the second transistor T2 receives a high-voltage signal, and the second transistor T2 is turned off according to the high-voltage signal received by the gate thereof, so that the low-voltage signal received by the first electrode of the second transistor T2 cannot be transmitted to the first node N1. Due to the charge holding function of the second capacitor Cst2, the potential of the gate of the seventh transistor T7, that is, the second node N2, is held, so that the second node N2 holds the low potential at the previous stage, and accordingly, the potential of the gate of the first transistor T1 is at the low potential, so that the first transistor T1 is turned on, the high potential signal input from the first potential signal input terminal VGH is transmitted to the first node N1, and the sixth transistor T6 is turned off according to the high potential input from the control terminal thereof.

The gate of the third transistor T3 is electrically connected to the first clock signal input terminal CK1, so that the third transistor T3 is turned off according to the high signal inputted from the gate thereof, and the signal inputted from the enable signal input terminal SIN cannot be transmitted to the second node N2; the gate of the fourth transistor T4 is electrically connected to the second clock signal input terminal CK2, and thus a low potential signal is input to the gate of the fourth transistor T4, and the fourth transistor T4 is turned on; the gate of the fifth transistor T5 is at the same potential as the first node N1, i.e., at a high potential, so that the fifth transistor T5 is turned off and the high potential signal inputted from the first potential signal input terminal VGH cannot be transmitted to the second node N2.

The gate of the seventh transistor T7 maintains the low voltage level of the first node N1 due to the storage and retention of the charges by the second capacitor Cst2, so that the seventh transistor T7 is turned on, and a low voltage signal input from the second clock signal input terminal CK2 is output to the SCAN signal output terminal SCAN through the seventh transistor T7, and the voltage output from the SCAN signal output terminal SCAN is a low voltage signal. That is, in the second stage t2, the SCAN signal output terminal SCAN outputs the same signal as the second clock signal input terminal CK2 inputs.

After entering the third stage t3, the first clock signal input terminal CK1 inputs a low-level signal, the second clock signal input terminal CK2 inputs a high-level signal, and the third clock signal input terminal CK3 inputs a low-level signal. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal CK1, so that the gate of the second transistor T2 inputs a low-potential signal, the second transistor T2 is turned on, and the low-potential signal input by the first pole of the second transistor T2 is transmitted to the first node N1; the sixth transistor T6 is turned on according to the low potential of the first node N1 electrically connected to the gate thereof, and transmits the high potential inputted from the first potential signal input terminal VGH to the SCAN signal output terminal SCAN.

The third transistor T3 is turned on according to the low-potential signal inputted from the first clock signal input terminal CK1 electrically connected to the gate thereof, so that the high-potential signal inputted from the enable signal input terminal SIN is transmitted from the first pole of the third transistor T3 to the second node N2; the fourth transistor T4 is turned off according to the high voltage input from the second clock signal input terminal CK2 electrically connected to the gate thereof, the gate of the fifth transistor T5 is at the same voltage level as the first node N1, i.e., at a low voltage level, and the fifth transistor T5 is turned on. Since the second node N2 is at a high level, the seventh transistor T7 is turned off according to a high signal at its gate. In the third stage t3, when the first clock signal input terminal CK1 inputs a low voltage signal, the second clock signal input terminal CK2 inputs a high voltage signal, and the SCAN signal input terminal CK3 inputs a low voltage signal, the SCAN signal output terminal SCAN outputs a high voltage signal, which is the same as the voltage input by the first voltage signal input terminal VGH.

In the third stage t3, when the second clock signal input terminal CK2 inputs a low level pulse signal, the first clock signal input terminal CK1 and the enable signal input terminal SIN both input a high level signal, and the third clock signal input terminal CK3 inputs a low level signal. The gate of the second transistor T2 is electrically connected to the first clock signal input terminal CK1, so that the gate of the second transistor T2 inputs a high-potential signal, and the second transistor T2 is turned off, so that the low-potential signal input by the first pole of the second transistor T2 cannot be transmitted to the first node N1. However, the first node N1 is kept at the low potential due to the storage and holding of the charges by the first capacitor Cst1, accordingly, the sixth transistor T6 is turned on, and the high potential inputted from the first potential signal input terminal VGH is transmitted to the SCAN signal output terminal SCAN.

The third transistor T3 is turned off according to the second high potential signal inputted from the first clock signal input terminal CK1 electrically connected to the gate thereof; the fourth transistor T4 is turned on according to the low potential of the signal inputted from the second clock signal input terminal CK2 electrically connected to the gate thereof, the gate of the fifth transistor T5 is the same as the first node N1 in potential, i.e., the low potential, and thus the fifth transistor T5 is also turned on, so that the high potential signal inputted from the first potential signal input terminal VGH is transmitted to the second node N2 through the fifth transistor T5 and the fourth transistor T4, and the second node N2 is the high potential, so that the seventh transistor T7 is turned off according to the high potential signal of the second node N2 electrically connected to the gate thereof. That is, in the third stage t3, when the second clock signal input terminal CK2 inputs a low level pulse signal, the first clock signal input terminal CK1 and the start signal input terminal SIN both input a high level signal, and when the third clock signal input terminal CK3 inputs a low level signal, the SCAN signal output terminal SCAN outputs a high level signal, which is the same as the potential input by the first potential signal input terminal VGH.

In addition, since the gate of the ninth transistor T9 is connected to the second potential signal input terminal VGL, that is, the gate of the ninth transistor T9 is always inputted with the low potential signal, the ninth transistor T9 is always turned on in the above stages.

It should be noted that, in the above embodiment, the low potential pulse signal is input to the third clock signal input terminal CK3 in the second half of the first phase t1, specifically, the first phase t1 may be equally divided into a first sub-phase and a second sub-phase in terms of time, where the first sub-phase is a relatively earlier phase in time, the second sub-phase is a relatively later phase in time, and the low potential pulse signal is input to the third clock signal input terminal CK3 at any time in all times in the second sub-phase.

Fig. 13 is a flowchart of a driving method of a scan circuit according to an embodiment of the present invention, and referring to fig. 13 in conjunction with fig. 1, the scan circuit includes a first output control module 110, a second output control module 120, a first output module 130, a second output module 140, an eighth transistor T8, a first potential signal input terminal VGH, a second potential signal input terminal VGL, a first clock signal input terminal CK1, a second clock signal input terminal CK2, a third clock signal input terminal CK3, a start signal input terminal SIN, a first node N1, and a second node N2;

the driving method of the scanning circuit comprises the following steps:

step 210, in a first preset time before the end of inputting the preset pulse signal to the start signal input end SIN is started, inputting a first pulse signal to the third clock signal input end CK3, where the first pulse signal is used to control the start of turning on the reset control module, and when the start of turning on the reset module, transmitting the signal input by the first potential signal input end VGH to the start signal input end SIN, where the potential of the signal input by the first potential signal input end VGH is opposite to the potential of the preset pulse signal input by the start signal input end SIN;

The preset pulse signal points to a pulse signal which is provided by the scanning circuit and enables the scanning circuit to output an effective scanning signal. Referring to fig. 2, if the pulse width corresponding to the preset pulse signal input from the start signal input terminal is d1, the first preset time is less than or equal to the time length corresponding to d 1/2.

Inputting a first pulse signal to the third clock signal input terminal CK3 within a first preset time before the end of inputting a preset pulse signal to the start signal input terminal SIN; the first preset time is less than or equal to the time length corresponding to half of the pulse width of the preset pulse signal, so that the start signal reset module 150 transmits the signal input by the first potential signal input terminal VGH to the start signal input terminal SIN within the first preset time before the preset pulse signal is input to the start signal input terminal SIN, and the signal input by the first potential signal input terminal VGH is opposite to the potential of the preset pulse signal, so that the preset pulse signal input by the start signal input terminal SIN is timely reset, and the SCAN signal output by the SCAN signal output terminal SCAN is normally output, thereby avoiding display abnormality caused by overlapping of the SCAN signal provided to the pixel circuit and the light-emitting control signal, and the problem of large current between the high potential signal input terminal and the low potential signal input terminal in the pixel circuit.

Fig. 14 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and referring to fig. 14, the display panel includes a scanning circuit according to any of the embodiments of the present invention as a primary scanning circuit 310, a first clock signal line 320, a second clock signal line 330, a third clock signal line 340, a first potential signal line 350, a second potential signal line 360, and a start signal line 370;

the display panel further includes at least one secondary scanning circuit 380, fig. 15 is a schematic structural diagram of a secondary scanning circuit according to an embodiment of the present invention, which is different from the structure of the primary scanning circuit shown in fig. 11 only in that the secondary scanning circuit shown in fig. 15 does not include a start signal reset control module, and referring to fig. 15, the secondary scanning circuit 380 includes a third output control module 410, a fourth output control module 420, a third output module 430, a fourth output module 440, a third potential signal input terminal Vgh1, a second potential signal input terminal Vgl1, a fourth clock signal input terminal CK4, a fifth clock signal input terminal CK5, a shift signal input terminal SN, a scanning signal output terminal Scan1, a third node N3, and a fourth node N4;

a first clock signal input end of the primary scanning circuit 310 and a fourth clock signal input end of the even-row secondary scanning circuit 380 are electrically connected with a first clock signal line 320, a second clock signal input end of the primary scanning circuit 310 and a fifth clock signal input end of the even-row secondary scanning circuit 380 are electrically connected with a second clock signal line 330, a fourth clock signal input end of the odd-row secondary scanning circuit 380 is electrically connected with the second clock signal line 330, and a fifth clock signal input end of the odd-row secondary scanning circuit 380 is electrically connected with the first clock signal line 320; a third clock signal input terminal of the primary scanning circuit 310 is electrically connected to the third clock signal line 340, a first potential signal input terminal of the primary scanning circuit 310 and a third potential signal input terminal of the secondary scanning circuit 380 are both electrically connected to the first potential signal line 350, and a second potential signal input terminal of the primary scanning circuit 310 and a fourth potential signal input terminal of the secondary scanning circuit 380 are both electrically connected to the second potential signal line 360; the start signal input terminal of the primary scanning circuit 310 is electrically connected to the start signal line 370;

the shift signal input SN of the first stage scan circuit in the secondary scan circuit 380 is electrically connected to the scan signal output of the primary scan circuit 310; each secondary scanning circuit 380 is cascade-connected, and in any two adjacent stages of the secondary scanning circuits 380, the shift signal input terminal SN of the next-stage secondary scanning circuit 380 is electrically connected to the scanning signal output terminal of the previous-stage scanning circuit.

The odd-numbered line subscanning circuit 380 refers to the subscanning circuits located in the odd-numbered lines from the first-stage subscanning circuit, i.e., the first-stage subscanning circuit, the third-stage subscanning circuit, and the fifth-stage subscanning circuit … …

The even-row sub-scanning circuit 380 refers to the sub-scanning circuits located at even rows from the first-stage sub-scanning circuit, i.e., the second-stage sub-scanning circuit, the fourth-stage sub-scanning circuit, and the sixth-stage sub-scanning circuit … …

The display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, an electronic paper display panel, or the like. The scanning signal output end of each stage of scanning circuit is electrically connected with the scanning line on the display panel and transmits the scanning signal to each scanning line. The primary scanning circuit shifts the start signal on the start signal line 370 and outputs the start signal through the scanning signal output end thereof, and the control end of the start signal resetting module of the primary scanning circuit is electrically connected with the third clock signal input end, so that the preset scanning pulse signal input by the start signal input end can be controlled to be reset in time. In the adjacent two stages of scanning circuits, the next stage of scanning circuit shifts the scanning signal output by the previous stage of scanning circuit and outputs the shifted scanning signal.

It should be noted that the display panel shown in fig. 14 is illustrated by the scanning circuit being located on one side frame of the display panel, and optionally, the scanning circuit may be further disposed on both sides of the display panel, so that the two side frames have smaller widths and more consistent sizes, and the display panel realizes a narrow frame, has more beautiful appearance, and improves experience.

The display panel provided by the embodiment of the invention comprises the scanning circuit provided by any embodiment of the invention, the scanning circuit is arranged to comprise a starting signal resetting module, the starting signal resetting module comprises a control end, an input end and an output end, the control end of the starting signal resetting module is electrically connected with a third clock signal input end, the input end of the starting signal resetting module is electrically connected with a first potential signal input end, and the output end of the starting signal resetting module is electrically connected with a starting signal input end, so that the starting pulse signal output by the starting signal resetting module can be timely reset, and the influence on the display effect caused by the fact that the starting pulse signal corresponding to the starting signal cannot be timely reset after the driving chip outputs the pulse signal is avoided. In addition, the starting signal reset control module is arranged in the primary scanning circuit, so that the scanning signals output by the primary scanning circuit are accurate and reliable, and the scanning signals output by the primary scanning circuit are used as the shifting signals input by the shifting signal input end of the secondary scanning circuit, thereby ensuring that each scanning circuit in the whole display panel outputs accurate and reliable scanning signals.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A scanning circuit is characterized by comprising a first output control module, a second output control module, a first output module, a second output module, a starting signal resetting module, a first potential signal input end, a second potential signal input end, a first clock signal input end, a second clock signal input end, a third clock signal input end, a starting signal input end, a scanning signal output end, a first node and a second node;

the second output control module comprises a first control end, a second control end, a third control end, a first input end, a second input end and an output end, the first control end of the second output control module is electrically connected with the first clock signal input end, the first input end of the second output control module is electrically connected with the starting signal input end, the output end of the second output control module is electrically connected with the second node, the second control end of the second output control module is electrically connected with the second clock signal input end, the third control end of the second output control module is electrically connected with the first node, and the second input end of the second output control module is electrically connected with the first potential signal input end; the second output control module is used for controlling the communication state between the first input end of the second output control module and the output end of the second output control module according to signals input by the first control end of the second output control module, and controlling the communication state between the second input end of the second output control module and the output end of the second output control module according to signals input by the second control end of the second output control module and the third control end of the second output control module;

2. The scan circuit of claim 1, wherein the first output control module comprises a first transistor and a second transistor, each of the first transistor and the second transistor comprises a gate, a first pole and a second pole, the gate of the first transistor is used as the first control terminal of the first output control module, the first pole of the first transistor is used as the first input terminal of the first output control module, and the second pole of the first transistor is used as the output terminal of the first output control module; the grid electrode of the second transistor is used as the second control end of the first output control module, the first pole of the second transistor is used as the second input end of the first output control module, and the second pole of the second transistor is electrically connected with the second pole of the first transistor.

3. The scan circuit of claim 1, wherein the second output control module comprises a third transistor, a fourth transistor, and a fifth transistor, each of the third transistor, the fourth transistor, and the fifth transistor comprising a gate, a first pole, and a second pole;

a gate of the third transistor is used as a first control end of the second output control module, a first pole of the third transistor is used as a first input end of the second output control module, and a second pole of the third transistor is used as an output end of the second output control module;

a gate of the fourth transistor is used as a second control terminal of the second output control module, a first pole of the fourth transistor is electrically connected with a second pole of the fifth transistor, and a second pole of the fourth transistor is electrically connected with a second pole of the third transistor;

and the grid electrode of the fifth transistor is used as a third control end of the second output control module, and the first pole of the fifth transistor is used as a second input end of the second output control module.

4. The scan circuit of claim 1, wherein the first output module comprises a sixth transistor and a first capacitor, a gate of the sixth transistor is used as a control terminal of the first output module, a first pole of the sixth transistor is used as an input terminal of the first output module, and a second pole of the sixth transistor is used as an output terminal of the first output module; two ends of the first capacitor are electrically connected with the grid electrode of the sixth transistor and the first pole respectively.

5. The scan circuit of claim 1, wherein the second output module comprises a seventh transistor and a second capacitor, a gate of the seventh transistor is used as the control terminal of the second output module, a first pole of the seventh transistor is used as the input terminal of the second output module, and a second pole of the seventh transistor is used as the output terminal of the second output module; and two ends of the second capacitor are respectively and electrically connected with the grid electrode and the second pole of the seventh transistor.

6. The scan circuit of claim 1, wherein the enable signal reset module comprises an eighth transistor, a gate of the eighth transistor is used as a control terminal of the enable signal reset module, a first pole of the eighth transistor is used as an input terminal of the enable signal reset module, and a second pole of the eighth transistor is used as an output terminal of the enable signal reset module.

7. The scan circuit of claim 6, wherein the eighth transistor is an IGZO transistor.

8. The scan circuit according to claim 1, further comprising a ninth transistor, wherein the second node is electrically connected to the control terminal of the second output module through the ninth transistor;

9. A driving method of a scanning circuit is characterized in that the scanning circuit comprises a first output control module, a second output control module, a first output module, a second output module, a starting signal reset module, a first potential signal input end, a second potential signal input end, a first clock signal input end, a second clock signal input end, a third clock signal input end, a starting signal input end, a scanning signal output end, a first node and a second node;

the driving method of the scanning circuit comprises the following steps:

inputting a first pulse signal to the third clock signal input end within a first preset time before a preset pulse signal is input to the starting signal input end, wherein the first pulse signal is used for controlling the starting signal reset module to be conducted, and transmitting a signal input by a first potential signal input end to the starting signal input end when the starting signal reset module is conducted, and the potential of the signal input by the first potential signal input end is opposite to that of the preset pulse signal input by the starting signal input end;

10. A display panel comprising the scanning circuit according to any one of claims 1 to 8, a first clock signal line, a second clock signal line, a third clock signal line, a first potential signal line, a second potential signal line, and a start signal line, the scanning circuit according to any one of claims 1 to 8 being a primary scanning circuit of the display panel;

the display panel further comprises at least one secondary scanning circuit, wherein the secondary scanning circuit comprises a third output control module, a fourth output control module, a third output module, a fourth output module, a third potential signal input end, a fourth clock signal input end, a fifth clock signal input end, a shift signal input end, a third node and a fourth node;

a first clock signal input end of the primary scanning circuit and a fourth clock signal input end of the secondary scanning circuit in even rows are electrically connected with the first clock signal line, and a second clock signal input end of the primary scanning circuit and a fifth clock signal input end of the secondary scanning circuit in even rows are electrically connected with the second clock signal line; the fourth clock signal input ends of the odd-numbered rows of the secondary scanning circuits are electrically connected with the second clock signal line, and the fifth clock signal input ends of the odd-numbered rows of the secondary scanning circuits are electrically connected with the first clock signal line;

a third clock signal input end of the primary scanning circuit is electrically connected with the third clock signal line, a first potential signal input end of the primary scanning circuit and a third potential signal input end of the secondary scanning circuit are both electrically connected with the first potential signal line, and a second potential signal input end of the primary scanning circuit and a fourth potential signal input end of the secondary scanning circuit are both electrically connected with the second potential signal line; the starting signal input end of the primary scanning circuit is electrically connected with the starting signal wire;

a shift signal input end of a first-stage scanning circuit in the secondary scanning circuit is electrically connected with a scanning signal output end of the primary scanning circuit; and in any two adjacent stages of the secondary scanning circuits, the shift signal input end of the next-stage secondary scanning circuit is electrically connected with the scanning signal output end of the previous-stage scanning circuit.