CN110673019A - Wafer-level automatic test system - Google Patents
Wafer-level automatic test system Download PDFInfo
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- CN110673019A CN110673019A CN201911023776.4A CN201911023776A CN110673019A CN 110673019 A CN110673019 A CN 110673019A CN 201911023776 A CN201911023776 A CN 201911023776A CN 110673019 A CN110673019 A CN 110673019A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention provides a wafer-level automatic test system, comprising: a tester and a probe station; the probe station is used for bearing a wafer to be tested; displaying an interface; the wafer selection tool is used for reading and selecting the wafer to be detected and generating wafer selection information; the user-defined text is used for defining the position of the target chip; the text interface is arranged on the display interface and used for importing the custom text; the test program module is arranged in the tester and used for converting the self-defined text and the wafer selection information into a communication instruction; and transmitting the communication command to a communication protocol of the probe station. The invention provides an independent graphical operation interface and a text interface, converts the input of a user into a communication instruction between a testing machine and a probe station, and sends the communication instruction to the probe station by the testing machine. The wafer to be tested can be flexibly set, different positions of the target chip to be tested can be set on different wafers, the flexibility of the test system is effectively improved, the execution efficiency of test tasks is improved, and errors caused by manual operation are reduced.
Description
Technical Field
The present invention relates to an automatic test control system, and more particularly, to a wafer level automatic test system.
Background
In a traditional wafer level functional test platform, a test machine and a probe station are required to cooperate to complete the test work. The tester is responsible for executing a test program, and the probe station is responsible for selecting a test wafer and a chip. Fig. 1 shows an architecture of a control interaction logic diagram of a tester and a probe station in a wafer level test, in which the tester and the probe station communicate with each other through a GPIB protocol, and the actual position of a wafer to be tested and a chip to be tested needs to be set at the probe station, and the probe station automatically stores the set information as a probe station program. In fig. 1, a test machine gives a command to perform slot address selection, a probe station carries out wafer bearing and aligns to a wafer to be tested, the test machine communicates with the probe station, the probe station performs slot address confirmation and then communicates with the test machine, the test machine performs X/Y axis position selection of a chip to be tested on the wafer and then communicates with the probe station, the probe station provides X/Y axis data and then communicates with the probe station, the test machine carries out testing and provides test result data, then the probe station communicates with the probe station, the probe station judges whether the chip is the last test chip, if not, the probe moves to the next chip to be tested, and if yes, the operation step of carrying the wafer is returned to the test machine.
In this control mode, in one test task, the chip position to be tested set in the position setting program called by the probe station is a shared position, that is, the different wafer test chip positions are the same. If the position of the chip to be tested on the wafer is inconsistent with the chip position setting in the current later program, a probe station program needs to be newly established at the probe station end according to the new position requirement. If different wafers in the same batch need to test chips at different positions, different probe station programs can be respectively called for testing, and one testing task is divided into multiple tests.
As shown in fig. 2a and fig. 2b, the target chip 01 to be tested and the target chip 02 to be tested are different in position, and therefore, the respective programs are called twice to test.
Under the test system architecture, the test efficiency is low due to low flexibility of setting the test target, and a large amount of resources are wasted. Meanwhile, the failure analysis progress of the project is also seriously influenced, and the overall delay of the project is caused.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a wafer level automatic test system, which is used to solve the problems in the prior art that the test efficiency is low due to low flexibility of setting the test target, which results in a large amount of resource waste, and the failure analysis progress of the project is also seriously affected, which results in the overall delay of the project.
To achieve the above and other related objects, the present invention provides a wafer level automatic test system, which at least comprises: a tester and a probe station; the probe station is used for bearing the wafer box and extracting the wafer to be tested from the wafer box; a display interface arranged on the testing machine; the wafer selection tool is displayed on the display interface and used for reading and selecting the slot position of the wafer to be detected in the wafer box and generating wafer selection information; the custom text is used for defining the position of a target chip in the wafer to be detected; the text interface is arranged on the display interface and used for importing the custom text; the test program module is arranged in the automatic test system and used for converting the self-defined text and the wafer selection information into a communication instruction; and transmitting the communication instruction to a communication protocol of the probe station.
Preferably, the test system further comprises a test input program module and a probe station input program module.
Preferably, the wafer selection tool comprises a list of slots where wafers are located and full selection, no selection and determination buttons.
Preferably, there are 25 options in the list of options.
Preferably, the custom text is in the form of a table.
Preferably, the table includes an index column, a wafer slot number column, a horizontal axis position column of the target chip, a vertical axis position column of the target chip, and a test result column.
Preferably, the test results are in a column by number.
Preferably, the horizontal axis position column of the target chip and the vertical axis position column of the target chip are respectively in a column by the number of horizontal and vertical coordinates.
As described above, the wafer level automatic test system of the present invention has the following advantages: the invention optimizes the communication interactive flow between the existing testing machine and the probe station, provides an independent graphical operation interface and a self-defined text interface, converts the input of a user into a communication instruction between the testing machine and the probe station, and sends the communication instruction to the probe station by the testing machine. The wafer to be tested can be flexibly set, different positions of target chips to be tested can be set on different wafers, the whole process of the program operation of the testing machine is managed and controlled, the flexibility of the testing system is effectively improved, the testing cost is saved, the execution efficiency of testing tasks is improved, and errors caused by manual operation are reduced.
Drawings
FIG. 1 is a logic diagram of the control interaction between a tester and a probe station in a wafer level test according to the prior art;
FIGS. 2a and 2b are diagrams illustrating different chips to be tested on different wafers to be tested;
FIG. 3 is a graphical display interface of the wafer level automatic test system of the present invention;
FIG. 4 is a schematic diagram of a wafer level automatic test system according to the present invention.
Description of the element reference numerals
01. 02 target chip to be tested
03 testing machine
04 Probe station
05 wafer box
06 self-defined text
07 text interface
08 test program module
09 wafer selection tool
10 display interface
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
Please refer to fig. 3 to 4. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
As shown in fig. 4, the present invention provides a wafer level automatic test system, which at least comprises: a tester and a probe station; the probe station is used for bearing the wafer box and extracting the wafer to be tested from the wafer box; the wafers to be tested are stacked in each slot of the wafer box, and one wafer to be tested is arranged in one slot. As shown in fig. 4, the wafers to be tested are stored in the 5 th layer, the 10 th layer, the 15 th layer, the 20 th layer and the 25 th layer of the wafer cassette; a display interface arranged on the testing machine; the wafer selection tool is displayed on the system display interface and used for reading and selecting the slot position of the wafer to be detected in the wafer box and generating wafer selection information; as shown in fig. 3, fig. 3 is a graphical display interface of the wafer level automatic test system according to the present invention, the display interface includes a wafer selection tool and a text interface, preferably, the wafer selection tool includes a list of slots where wafers are located and all-select, all-no-select, and ok buttons. Wherein clicking the All ON button represents a full selection, and All wafers are selected as the wafers to be tested. Clicking the All OFF button represents that All wafers are not selected, All wafers are not selected as wafers to be tested, and the list of options comprises 25 options. If several of the wafers are selected to be the wafers to be tested, several of the slots 1-25 can be selected. Clicking the ok button after selection indicates that the selection is complete. The test system automatically reads the actual wafer slot position in the current operation wafer box, displays the wafer state of each slot position in the wafer box when the display interface is started, can select the corresponding slot position to select the corresponding wafer as the subsequent test target wafer, and can prevent the situation that the slot position of the wafer is selected by mistake actually does not exist.
The wafer level automatic test system of the invention further comprises: the custom text is used for defining the position of a target chip in the wafer to be detected; preferably, the custom text is presented in a table, as shown in the following table: the table comprises an index column, a wafer groove position number column, a target chip transverse axis position column, a target chip longitudinal axis position column and a test result column. The table comprises an index column, a wafer groove position number column, a target chip transverse axis position column, a target chip longitudinal axis position column and a test result column. The horizontal axis position column of the target chip and the vertical axis position column of the target chip are respectively in a column by the number of horizontal and vertical coordinates. Wherein the index columns may be numbered as numbers 1 to 8; the wafer slot number may be displayed in the table after the slot where the wafer to be tested is located is selected, such as selecting slot number 2, slot number 6, slot number 3, and the like. For example, the horizontal axis positions of the target chip corresponding to the slot position No. 2 are 10, 12 and 32 respectively; the positions of the cross shaft of the target chip corresponding to the No. 6 slot position are respectively 9 and 30; the horizontal axis positions of the target chip corresponding to the slot No. 3 are 29, 20 and 18 respectively. Also the target chip longitudinal axis position is shown in the table below. The test results are displayed in a column, the display results are numbered in a certain category, and the same category is classified as a number.
As shown in fig. 3, a text interface provided in the display interface is, as shown in fig. 4, configured to import the custom text; the test program module is arranged in the tester; the test program module is used for converting the custom text and the wafer selection information into a communication instruction; the probe station also comprises a communication protocol for transmitting the communication instruction to the probe station. And after receiving the custom text, a test program module in the tester converts the custom text into a communication instruction, the communication instruction is transmitted to the probe station by the communication protocol, and the probe station starts to test after receiving the instruction.
The work flow of the wafer-level automatic test system of the invention is as follows:
1) a custom text is provided, which may be a third party file, as shown in fig. 3, where the third party file "testdie file. The file can be edited and input by a third-party tool or obtained by filing and converting a previous test result, the system allows the test chip information to be written in the' testdie file.
2) Preferably, the wafer level automatic test system in this embodiment further includes a test input program module and a probe station input program module. Before the test starts, the two program modules are input into the test system, and the two program modules are used for executing the test operation and the probe station operation.
3) And opening a display interface, as shown in fig. 3, checking a wafer to be tested in the wafer selection tool, and clicking an OK button to determine to generate wafer selection information. And then importing the custom text into the test system through a text interface.
4) The tester converts the self-defined text and the wafer selection information into a communication instruction through a test program module;
5) the test machine sends the communication instruction to the probe station through a communication protocol, the probe station bears the wafer box and aligns to a wafer to be tested after receiving the instruction, and a probe in the probe station aligns to a chip to be tested in the wafer to be tested according to the requirement of the communication instruction;
6) the test result is formed after the test of the tester, the test result is presented in a list form, and the test result is numbered according to the category of the test structure.
7) After a chip is tested, the test system will determine whether the tested chip is the last one? If yes, ending the test, otherwise, returning to continue to execute the step 5).
In summary, the present invention provides an independent graphical operation interface and a self-defined text interface, which converts the user input into a communication command between the tester and the probe station, and sends the command from the tester to the probe station. The wafer to be tested can be flexibly set, different positions of target chips to be tested can be set on different wafers, the whole process of the program operation of the testing machine is managed and controlled, the flexibility of the testing system is effectively improved, the testing cost is saved, the execution efficiency of testing tasks is improved, and errors caused by manual operation are reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (8)
1. An automatic wafer-level test system, comprising:
a tester and a probe station; the probe station is used for bearing the wafer box and extracting the wafer to be tested from the wafer box;
a display interface arranged on the testing machine; the wafer selection tool is displayed on the display interface and used for reading and selecting the slot position of the wafer to be detected in the wafer box and generating wafer selection information;
the custom text is used for defining the position of a target chip in the wafer to be detected;
the text interface is arranged on the display interface and used for importing the custom text;
the test program module is arranged in the tester and used for converting the custom text and the wafer selection information into a communication instruction;
and transmitting the communication instruction to a communication protocol of the probe station.
2. The wafer-level automatic test system of claim 1, wherein: the test system also includes a test input program module and a probe station input program module.
3. The wafer-level automatic test system of claim 1, wherein: the wafer selection tool comprises a list option of a slot position where a wafer is located and full selection, full non-selection and determination buttons.
4. The wafer-level automatic test system of claim 3, wherein: there are 25 options in the list.
5. The wafer-level automatic test system of claim 4, wherein: the custom text is in the form of a table.
6. The wafer-level automatic test system of claim 5, wherein: the table comprises an index column, a wafer groove position number column, a target chip transverse axis position column, a target chip longitudinal axis position column and a test result column.
7. The wafer-level automatic test system of claim 6, wherein: the test results are in a column by number.
8. The wafer-level automatic test system of claim 7, wherein: the horizontal axis position column of the target chip and the vertical axis position column of the target chip are respectively in a column by the number of horizontal and vertical coordinates.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN2018221489011 | 2018-12-19 | ||
| CN201822148901 | 2018-12-19 |
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| CN110673019A true CN110673019A (en) | 2020-01-10 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112541657A (en) * | 2020-11-11 | 2021-03-23 | 特劢丝软件科技(上海)有限公司 | Silicon chip product conversion method and system, electronic equipment and storage medium |
| CN112597742A (en) * | 2020-12-02 | 2021-04-02 | 长春光华微电子设备工程中心有限公司 | Method for realizing self-defined test path of wafer probe station |
| CN112600737A (en) * | 2020-12-15 | 2021-04-02 | 厦门芯泰达集成电路有限公司 | Communication test method, medium, device and system |
| CN112612661A (en) * | 2020-12-17 | 2021-04-06 | 海光信息技术股份有限公司 | Chip system level test method, device and system |
| CN112833943A (en) * | 2020-12-29 | 2021-05-25 | 无锡圆方半导体测试有限公司 | Automatic optical detection and wafer test all-in-one machine |
| CN112863587A (en) * | 2021-01-26 | 2021-05-28 | 深圳市卓然电子有限公司 | Method for testing flash memory chip |
| CN115237822A (en) * | 2022-09-22 | 2022-10-25 | 之江实验室 | Address optimization device for IIC configuration interface of wafer-level processor |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62252145A (en) * | 1986-04-25 | 1987-11-02 | Hitachi Ltd | Scan type electron microscope for observing semiconductor wafer |
| US20070007988A1 (en) * | 2003-04-10 | 2007-01-11 | Umc Japan | LSI inspection method and defect inspection data analysis apparatus |
| US20070122128A1 (en) * | 2003-08-20 | 2007-05-31 | Asm International N.V. | Method and system for loading substrate supports into a substrate holder |
| JP2007258312A (en) * | 2006-03-22 | 2007-10-04 | Fujitsu Ltd | Method for storing intrinsic information of semiconductor device |
| CN105336642A (en) * | 2014-07-23 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Semiconductor equipment cavity state display control method and apparatus |
| CN105866652A (en) * | 2016-03-24 | 2016-08-17 | 上海华力微电子有限公司 | Automatic wafer calibration method |
| CN108519550A (en) * | 2018-03-28 | 2018-09-11 | 上海华岭集成电路技术股份有限公司 | IC wafers test optimization method |
| CN108535622A (en) * | 2018-04-28 | 2018-09-14 | 德淮半导体有限公司 | Wafer tester, system and method |
-
2019
- 2019-10-25 CN CN201911023776.4A patent/CN110673019A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62252145A (en) * | 1986-04-25 | 1987-11-02 | Hitachi Ltd | Scan type electron microscope for observing semiconductor wafer |
| US20070007988A1 (en) * | 2003-04-10 | 2007-01-11 | Umc Japan | LSI inspection method and defect inspection data analysis apparatus |
| US20070122128A1 (en) * | 2003-08-20 | 2007-05-31 | Asm International N.V. | Method and system for loading substrate supports into a substrate holder |
| JP2007258312A (en) * | 2006-03-22 | 2007-10-04 | Fujitsu Ltd | Method for storing intrinsic information of semiconductor device |
| CN105336642A (en) * | 2014-07-23 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Semiconductor equipment cavity state display control method and apparatus |
| CN105866652A (en) * | 2016-03-24 | 2016-08-17 | 上海华力微电子有限公司 | Automatic wafer calibration method |
| CN108519550A (en) * | 2018-03-28 | 2018-09-11 | 上海华岭集成电路技术股份有限公司 | IC wafers test optimization method |
| CN108535622A (en) * | 2018-04-28 | 2018-09-14 | 德淮半导体有限公司 | Wafer tester, system and method |
Non-Patent Citations (1)
| Title |
|---|
| 于向伟: "集成电路晶圆批量测试***的设计与实现", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112541657A (en) * | 2020-11-11 | 2021-03-23 | 特劢丝软件科技(上海)有限公司 | Silicon chip product conversion method and system, electronic equipment and storage medium |
| CN112541657B (en) * | 2020-11-11 | 2022-11-18 | 上海赛美特软件科技有限公司 | Silicon chip product conversion method and system, electronic device and storage medium |
| CN112597742A (en) * | 2020-12-02 | 2021-04-02 | 长春光华微电子设备工程中心有限公司 | Method for realizing self-defined test path of wafer probe station |
| CN112600737A (en) * | 2020-12-15 | 2021-04-02 | 厦门芯泰达集成电路有限公司 | Communication test method, medium, device and system |
| CN112600737B (en) * | 2020-12-15 | 2022-03-04 | 厦门芯泰达集成电路有限公司 | Communication test method, computer readable storage medium, device and system |
| CN112612661A (en) * | 2020-12-17 | 2021-04-06 | 海光信息技术股份有限公司 | Chip system level test method, device and system |
| CN112612661B (en) * | 2020-12-17 | 2022-08-23 | 海光信息技术股份有限公司 | Chip system level test method, device and system |
| CN112833943A (en) * | 2020-12-29 | 2021-05-25 | 无锡圆方半导体测试有限公司 | Automatic optical detection and wafer test all-in-one machine |
| CN112863587A (en) * | 2021-01-26 | 2021-05-28 | 深圳市卓然电子有限公司 | Method for testing flash memory chip |
| CN115237822A (en) * | 2022-09-22 | 2022-10-25 | 之江实验室 | Address optimization device for IIC configuration interface of wafer-level processor |
| CN115237822B (en) * | 2022-09-22 | 2022-12-30 | 之江实验室 | Address optimization device for IIC configuration interface of wafer-level processor |
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Application publication date: 20200110 |