CN110659229B - Memory management method, memory storage device and memory control circuit unit - Google Patents

Memory management method, memory storage device and memory control circuit unit Download PDF

Info

Publication number
CN110659229B
CN110659229B CN201810694015.0A CN201810694015A CN110659229B CN 110659229 B CN110659229 B CN 110659229B CN 201810694015 A CN201810694015 A CN 201810694015A CN 110659229 B CN110659229 B CN 110659229B
Authority
CN
China
Prior art keywords
interrupt
mode
information
host system
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810694015.0A
Other languages
Chinese (zh)
Other versions
CN110659229A (en
Inventor
曾明晖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phison Electronics Corp
Original Assignee
Phison Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phison Electronics Corp filed Critical Phison Electronics Corp
Priority to CN201810694015.0A priority Critical patent/CN110659229B/en
Publication of CN110659229A publication Critical patent/CN110659229A/en
Application granted granted Critical
Publication of CN110659229B publication Critical patent/CN110659229B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Example embodiments of the present invention provide a memory management method for a memory storage device including a rewritable non-volatile memory module. The method comprises the following steps: receiving a first instruction and executing a first operation corresponding to the first instruction; sending a completion message to the host system corresponding to completion of the first operation; detecting instruction processing information; determining a transmission mode of interrupt information according to the instruction processing information; and transmitting the interrupt information to the host system according to the transmission mode. In addition, the exemplary embodiments of the present invention also provide a memory storage device and a memory control circuit unit.

Description

Memory management method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a memory technology, and more particularly, to a memory management method, a memory storage device, and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown very rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
In a Non-Volatile Memory Host Controller Interface (Non-Volatile Memory Host Controller Interface) specification or a Non-Volatile Memory express (NVMe) Interface specification, a Host system may execute a Host instruction handler to generate operation instructions to be provided to a Memory storage device. The memory storage device may actively fetch operational instructions from the host system and perform corresponding operations. After completing the corresponding operation, the memory storage device may send a completion message and an interrupt message to the host system. Based on the interrupt information, the host system can convert the executing operating program from the host instruction processing program to the inspection program to interrupt the instruction generating job and start inspecting the received completion information. However, if the host system receives interrupt information frequently, the host system needs to switch between the host instruction processing program and the checking program frequently, thereby increasing the system load.
Although some memory storage devices may not transmit interrupt information until after completing multiple operation commands or after responding to a timeout, the switching frequency of the host system between the host command processing procedure and the checking procedure is reduced. However, when the depth of the instruction arrangement is shallow, the aforementioned mechanism easily causes the reaction efficiency of the entire memory system to decrease. For example, when the depth of the command queue is 1-8, the host system usually waits until the response times out before receiving the interrupt message from the memory storage device. In some cases, if the host system cannot receive the interrupt information in a delayed manner, the host system cannot execute the next-stage program, thereby reducing the data processing performance of the host system.
Disclosure of Invention
The present invention provides a memory management method, a memory storage device and a memory control circuit unit, which can dynamically determine the transmission mode of interrupt information, thereby improving the above problems.
An exemplary embodiment of the present invention provides a memory management method for a memory storage device including a rewritable non-volatile memory module, the memory management method including: receiving a first instruction and executing a first operation corresponding to the first instruction; sending a completion message to the host system corresponding to completion of the first operation; detecting instruction processing information; determining a transmission mode of interrupt information according to the instruction processing information; and transmitting the interrupt information to the host system according to the transmission mode.
In an exemplary embodiment of the present invention, the step of detecting the instruction processing information includes: determining the number of instructions to be executed according to a difference between the number of instructions received and the number of instructions completed.
In an exemplary embodiment of the present invention, the step of determining the transmission mode of the interrupt information according to the instruction processing information includes: the transmission mode is determined based on whether the number of instructions to be executed is greater than a threshold.
In an exemplary embodiment of the invention, the interrupt information sending status reflects a sending status or a sending mode of the interrupt information within a preset time range. The step of determining the transmission mode of the interrupt information according to the instruction processing information includes: and if the sending state of the interrupt information reflects that N times of response timeout events of the interrupt information occur within the preset time range, switching the transmission mode of the interrupt information from a first mode to a second mode, wherein N is a positive integer not less than 1.
In an exemplary embodiment of the present invention, the step of transmitting the interrupt information to the host system according to the transmission mode includes: in a first mode, after the number of the completion messages sent reaches a preset number, sending the interrupt message to the host system; and in a second mode, transmitting the interrupt message to the host system before the number of the completion messages sent reaches the preset number, wherein the preset number is greater than one.
In an exemplary embodiment of the invention, the step of transmitting the interrupt information to the host system according to the transmission mode further includes: in the first mode, enabling a first interrupt control mechanism, wherein the enabled first interrupt control mechanism is configured to control sending of the interrupt message to the host system after the number of the completion messages sent reaches the predetermined number; and in the second mode, disabling the first interrupt control mechanism.
In an exemplary embodiment of the present invention, the step of transmitting the interrupt information to the host system according to the transmission mode includes: in the first mode, after the counting time reaches the preset time, transmitting the interrupt information to the host system; and in a second mode, transmitting the interrupt information to the host system before the counting time reaches the preset time.
In an exemplary embodiment of the invention, the step of transmitting the interrupt information to the host system according to the transmission mode further includes: in the first mode, enabling a second interrupt control mechanism, wherein the enabled second interrupt control mechanism is configured to control sending the interrupt message to the host system after the counting time reaches the preset time; and in the second mode, disabling the second interrupt control mechanism.
In an exemplary embodiment of the present invention, the step of transmitting the interrupt information to the host system according to the transmission mode includes: in a first mode, transmitting the interrupt information to the host system according to a first number of the completion information that has been sent; and in the second mode, transmitting the interrupt information to the host system according to the completion information of the sent second number, wherein the first number is larger than the second number.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for receiving a first instruction and executing a first operation corresponding to the first instruction. The memory control circuitry is further configured to send a completion message to the host system corresponding to completion of the first operation. The memory control circuit unit is also used for detecting instruction processing information. The memory control circuit unit is further configured to determine a transmission mode of interrupt information according to the instruction processing information. The memory control circuit unit is further configured to transmit the interrupt information to the host system according to the transmission mode.
In an exemplary embodiment of the present invention, the operation of the memory control circuit unit detecting the instruction processing information includes: determining the number of instructions to be executed according to a difference between the number of instructions received and the number of instructions completed.
In an exemplary embodiment of the present invention, the operation of the memory control circuit unit determining the transfer mode of the interrupt information according to the instruction processing information includes: the transmission mode is determined based on whether the number of instructions to be executed is greater than a threshold.
In an exemplary embodiment of the invention, the interrupt information sending status reflects a sending status or a sending mode of the interrupt information within a preset time range. The step of the memory control circuit unit deciding the transmission mode of the interrupt information according to the instruction processing information includes: and if the sending state of the interrupt information reflects that N times of response timeout events of the interrupt information occur within the preset time range, switching the transmission mode of the interrupt information from a first mode to a second mode, wherein N is a positive integer not less than 1.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit to transmit the interrupt information to the host system according to the transmission mode includes: in a first mode, after the number of the completion messages sent reaches a preset number, sending the interrupt message to the host system; and in a second mode, transmitting the interrupt message to the host system before the number of the completion messages sent reaches the preset number, wherein the preset number is greater than one.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit to transmit the interrupt information to the host system according to the transmission mode further includes: in the first mode, enabling a first interrupt control mechanism, wherein the enabled first interrupt control mechanism is configured to control sending of the interrupt message to the host system after the number of the completion messages sent reaches the predetermined number; and in the second mode, disabling the first interrupt control mechanism.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit to transmit the interrupt information to the host system according to the transmission mode includes: in the first mode, after the counting time reaches the preset time, transmitting the interrupt information to the host system; and in a second mode, transmitting the interrupt information to the host system before the counting time reaches the preset time.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit to transmit the interrupt information to the host system according to the transmission mode further includes: in the first mode, enabling a second interrupt control mechanism, wherein the enabled second interrupt control mechanism is configured to control sending the interrupt message to the host system after the counting time reaches the predetermined time; and disabling the second interrupt control mechanism in the second mode.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit to transmit the interrupt information to the host system according to the transmission mode includes: in a first mode, transmitting the interrupt information to the host system according to a first number of the completion information that has been sent; and in the second mode, transmitting the interrupt information to the host system according to a second number of the completion information that has been sent, wherein the first number is greater than the second number.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface, a detection circuit, an interrupt control circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface, the memory interface, the detection circuit, and the interrupt control circuit. The memory management circuit is configured to receive a first instruction and perform a first operation corresponding to the first instruction. The memory management circuitry is further to send a completion message to the host system corresponding to completion of the first operation. The detection circuit is used for detecting instruction processing information. The memory management circuit is further configured to determine a transmission mode of interrupt information according to the instruction processing information. The memory management circuit is further configured to instruct the interrupt control circuit to transmit the interrupt information to the host system according to the transmission mode.
In an exemplary embodiment of the present invention, the transmission mode includes a first mode and a second mode, the first mode corresponds to a first rule for transmitting the interrupt information, the second mode corresponds to a second rule for transmitting the interrupt information, and the first rule is different from the second rule.
In an exemplary embodiment of the present invention, the interrupt information is used to interrupt a host instruction handler of the host system.
In an exemplary embodiment of the present invention, the instruction processing information includes at least one of a number of received instructions, a number of completed instructions, a number of instructions to be executed, and an interrupt information sending status.
In an exemplary embodiment of the present invention, the operation of the detection circuit detecting the instruction processing information includes: determining the number of instructions to be executed according to a difference between the number of instructions received and the number of instructions completed.
In an exemplary embodiment of the present invention, the operation of the memory management circuit determining the transmission mode of the interrupt information according to the instruction processing information includes: the transmission mode is determined based on whether the number of instructions to be executed is greater than a threshold.
In an exemplary embodiment of the invention, the interrupt information sending status reflects a sending status or a sending mode of the interrupt information within a preset time range. The step of the memory management circuit deciding the transmission mode of the interrupt information according to the instruction processing information includes: and if the sending state of the interrupt information reflects that N times of response timeout events of the interrupt information occur within the preset time range, switching the transmission mode of the interrupt information from a first mode to a second mode, wherein N is a positive integer not less than 1.
In an example embodiment of the present invention, the operation of the memory management circuit instructing the interrupt control circuit to transfer the interrupt information to the host system according to the transfer mode includes: in a first mode, after the number of the completion messages sent reaches a preset number, sending the interrupt message to the host system; and in a second mode, transmitting the interrupt message to the host system before the number of the completion messages sent reaches the preset number, wherein the preset number is greater than one.
In an exemplary embodiment of the invention, the operation of the memory management circuit instructing the interrupt control circuit to transfer the interrupt information to the host system according to the transfer mode further comprises: in the first mode, enabling a first interrupt control mechanism, wherein the enabled first interrupt control mechanism is configured to control sending of the interrupt message to the host system after the number of the completion messages sent reaches the predetermined number; and in the second mode, disabling the first interrupt control mechanism.
In an example embodiment of the present invention, the operation of the memory management circuit instructing the interrupt control circuit to transfer the interrupt information to the host system according to the transfer mode includes: in the first mode, after the counting time reaches the preset time, transmitting the interrupt information to the host system; and in a second mode, transmitting the interrupt information to the host system before the counting time reaches the preset time.
In an exemplary embodiment of the invention, the operation of the memory management circuit instructing the interrupt control circuit to transfer the interrupt information to the host system according to the transfer mode further comprises: in the first mode, enabling a second interrupt control mechanism, wherein the enabled second interrupt control mechanism is configured to control sending the interrupt message to the host system after the counting time reaches the preset time; and disabling the second interrupt control mechanism in the second mode.
In an example embodiment of the present invention, the operation of the memory management circuit instructing the interrupt control circuit to transfer the interrupt information to the host system according to the transfer mode includes: in a first mode, transmitting the interrupt information to the host system according to a first number of the completion information that has been sent; and in the second mode, transmitting the interrupt information to the host system according to a second number of the completion information that has been sent, wherein the first number is greater than the second number.
In an exemplary embodiment of the present invention, the first number is an integer greater than one, and the second number is one.
Based on the above, after receiving the first command and completing the first operation corresponding to the first command, a completion message may be transmitted to the host system. Meanwhile, according to the detected instruction processing information, the transmission mode of the interrupt information can be determined. Based on the determined transfer mode, an interrupt message may be transferred to the host system. By dynamically determining the transmission mode of the interrupt message, the interrupt message can be properly transmitted to the host system no matter the depth of the command arrangement is deep or shallow, so as to avoid the response timeout or the host system switching between the host command processing program and the checking program too frequently.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.
FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
FIG. 6 is a diagram illustrating a management-rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
Fig. 7 is a diagram illustrating a data transfer operation according to an exemplary embodiment of the present invention.
Fig. 8 is a diagram illustrating transmission of interrupt information based on a first mode according to an exemplary embodiment of the present invention.
FIG. 9 is a diagram illustrating the transmission of interrupt information based on a second mode according to an exemplary embodiment of the invention.
FIG. 10 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention.
Description of reference numerals:
10. 30: a memory storage device;
11. 31: a host system;
110: a system bus;
111: a processor;
112: a random access memory;
113: a read-only memory;
114: a data transmission interface;
12: an input/output (I/O) device;
20: a main board;
201: a USB flash disk;
202: a memory card;
203: a solid state disk;
204: a wireless memory storage device;
205: a global positioning system module;
206: a network interface card;
207: a wireless transmission device;
208: a keyboard;
209: a screen;
210: a horn;
32: an SD card;
33: a CF card;
34: an embedded storage device;
341: an embedded multimedia card;
342: an embedded multi-chip package storage device;
402: a connection interface unit;
404: a memory control circuit unit;
406: a rewritable non-volatile memory module;
502: a memory management circuit;
504: a host interface;
506: a memory interface;
508: an error checking and correcting circuit;
510: a buffer memory;
512: a power management circuit;
513: a detection circuit;
601: a storage area;
602: a replacement area;
610 (0) to 610 (B): an entity unit;
612 (0) to 612 (C): a logic unit;
s701: step (transmit notification);
s702: a step of (obtaining an instruction);
s703: a step (transmitting read data or obtaining write data);
s704: a step of (transmitting completion information);
s705: a step of transmitting interrupt information;
711. 721: arranging the instructions;
712. 722: caching data;
713. 723: finishing the arrangement;
714: an interrupter;
724: an interrupt control circuit;
801 to 810, 901 to 903: completion information;
811. 911 to 913: interrupt information;
s1001: a step of receiving a first instruction and performing a first operation corresponding to the first instruction;
s1002: a step of sending a completion message to the host system corresponding to completion of the first operation;
s1003: a step of detecting instruction processing information;
s1004: a step of determining a transmission mode of interrupt information based on the instruction processing information;
s1005: step (transmitting the interrupt information to the host system according to the transmission mode).
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.
In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via the data transmission interface 114 by wire or wirelessly. The memory storage device 10 may be, for example, a flash disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded storage device 34 includes embedded Multi Media Card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) storage 342, which connect the memory module directly to the main board of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. In the present exemplary embodiment, the connection interface unit 402 is compatible with the NVM express (NVMe) interface specification. However, in another exemplary embodiment, the connection interface unit 402 may conform to other suitable standards. The connection interface unit 402 may be packaged in one chip with the memory control circuit unit 404, or the connection interface unit 402 is disposed outside the chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of the memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of the memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit region includes 32 physical fans, and the size of one physical fan is 512-bit group (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code (BOOT code), and when the memory control circuit unit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware manner. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data sent from the host system 11 are sent to the memory management circuit 502 through the host interface 504. In the present exemplary embodiment, the host interface 504 is compatible with the NVM express interface standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transfer standard.
The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.
The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.
FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
Referring to fig. 6, the memory management circuit 502 logically groups the physical units 610 (0) -610 (B) of the rewritable nonvolatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610 (0) -610 (a) in the storage area 601 are used for storing data, and the physical units 610 (a + 1) -610 (B) in the replacement area 602 are used for replacing damaged physical units in the storage area 601. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered as a damaged physical unit. It is noted that if there are no physical erase units available in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protect (write protect) state, and no more data can be written.
In the present exemplary embodiment, each physical unit refers to a physical erase unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical programming unit, or be composed of a plurality of continuous or discontinuous physical addresses. The memory management circuit 502 configures the logic units 612 (0) -612 (C) to map the physical units 610 (0) -610 (a) in the memory area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic cell may also refer to a logic program cell, a logic erase cell or be composed of a plurality of continuous or discontinuous logic addresses. Further, each of the logical units 612 (0) -612 (C) may be mapped to one or more physical units.
The memory management circuit 502 records a mapping relationship between logical units and physical units (also referred to as a logical-to-physical address mapping relationship) in at least one logical-to-physical address mapping table. When host system 11 is going to read data from memory storage device 10 or write data to memory storage device 10, memory management circuit 502 can perform data access operations with respect to memory storage device 10 according to the logical-to-physical address mapping table.
Fig. 7 is a diagram illustrating a data transfer operation according to an exemplary embodiment of the present invention. The communication mechanism between the memory device 10 and the host system 11 using the NVM express interface standard is described below with reference to fig. 7 as an example.
Referring to fig. 7, when the host system 11 is to perform an access operation on the memory storage device 10 (e.g., to read data from the memory storage device 10 or write data to the memory storage device 10), the processor 111 (e.g., CPU) of the host system 11 may execute a processing program (also referred to as a host instruction processing program) to generate an operation instruction to be provided to the memory storage device. The processor 111 may place the prepared operation instructions in an instruction queue 711. Then, the processor 111 may transmit a notification to the memory storage device 10 (step S701). In an exemplary embodiment, the operation of step S701 is also referred to as ringing (ring). It is to be noted that, under the NVM express interface standard, after issuing the notification, the active behavior of the host system 11 with respect to the memory storage device 10 is ended up to this point.
The memory management circuit 502 can receive the notification and actively read one or more instructions (also referred to as a first instruction) corresponding to the notification from the instruction queue 711 (step S702). For example, the obtained instructions may be cached in one instruction arrangement 721. According to the instructions in the instruction arrangement 721, the memory management circuit 502 may perform a corresponding access operation (also referred to as a first operation). For example, according to a read instruction, the memory management circuit 502 may perform a data read operation on the rewritable non-volatile memory module 406 and transfer the obtained read data from the data buffer 722 to the host system 11 (step S703). For example, the read data may be stored in the data cache 712 of the host system 11. Alternatively, according to a write command, the memory management circuit 502 may actively read the write data from the data cache 712 of the host system 11 and cache the write data in the data cache 722 (step S703). Then, the memory management circuit 502 can perform a data write operation on the rewritable non-volatile memory module 406 to write the write data buffered in the data buffer 722 into the rewritable non-volatile memory module 406.
Memory management circuitry 502 may generate a completion message corresponding to the completion of an access operation, and the completion message may be buffered in a completion queue 723. This completion message is used to notify the host system 11 that the access operation corresponding to a command is completed. The completion information may then be transmitted to the host system 11 and cached in a completion arrangement 713 of the host system 11 (step S704). Based on the data in completion queue 713, host system 11 may know that the memory access operation corresponding to the particular operation instruction has completed. Alternatively, in an example embodiment, based on the data in completion queue 713, host system 11 may also obtain the amount of data to be accessed and/or the data access speed of memory storage device 10 corresponding to one or more operation commands, and so on.
In the example embodiment of FIG. 7, instruction queue 711, data cache 712, and completion queue 713 are located in RAM 112 of host system 11, and instruction queue 721, data cache 722, and completion queue 723 are located in buffer memory 510 of memory storage device 10. However, in another exemplary embodiment, any one of the instruction arrangement 711, the data cache 712 and the completion arrangement 713 may be located in another storage medium of the host system 11, and any one of the instruction arrangement 721, the data cache 722 and the completion arrangement 723 may be located in another storage medium (e.g., the rewritable non-volatile memory module 406) of the memory storage device 10.
In the present exemplary embodiment, the host system 11 is further provided with an interrupter 714, and the memory storage device 10 is further provided with an interrupt control circuit 724. The interrupt 714 is connected to the processor 111 and the interrupt control circuit 724 is connected to the memory management circuit 502. After generating and/or transmitting at least one completion message, the interrupt control circuit 724 transmits an interrupt message to the interrupter 714 of the host system 11 (step S705). The interrupt information is used to interrupt the host command processing program of the host system 11. For example, the interrupt control circuit 724 may send an interrupt message after the memory management circuit 502 completes one or more operation instructions or after a timeout (timeout) occurs in response to the interrupt message. Upon receiving the interrupt information, the interrupter 714 may transmit an interrupt signal to the processor 111. Based on the interrupt signal, the processor 111 converts the executing operation program from the host instruction processing program previously used for generating the operation instruction into a checking program, so as to interrupt the instruction generating operation and start checking the received completion information. After the checking procedure is completed, the processor 111 can switch to execute the host instruction handler again to continue providing operation instructions to the instruction arrangement 711.
It should be noted that if the current instruction queue 711 or 721 is in a high queue depth state (e.g., the number of instructions to be processed in the instruction queue 711 or 721 is between 9 and 127), then completion information and interrupt information are provided more frequently corresponding to multiple instructions being processed consecutively. However, if the host system 11 receives the interrupt information too frequently (i.e., the interrupt control circuit 724 provides the interrupt information too frequently), the processor 111 needs to switch between the host instruction processing program and the checking program frequently, thereby increasing the system load.
Alternatively, if the current instruction queue 711 or 721 is in a low queue depth state (e.g., the number of instructions to be processed in the instruction queue 711 or 721 is between 1 and 8), then there are fewer instructions to be processed, and the completion information and interrupt information are provided less frequently. For example, in the low array depth state, the interrupt control circuit 724 may wait until the response of the interrupt message is expired before sending an interrupt message. However, if the host system 11 does not receive the interrupt information too long (i.e. the interrupt control circuit 724 provides the interrupt information too frequently), the host system 11 may think that the memory storage device 10 has not completed an access operation and temporarily does not perform other operations, thereby slowing down the data processing speed of the host system 11 and/or the memory storage device 10.
In an example embodiment, the memory management circuit 502 may dynamically determine and/or adjust the mode of delivery of interrupt information based on instruction processing information. The instruction processing information may include at least one of a number of instructions received, a number of instructions completed, a number of instructions to be executed, and an interrupt information issue status. By dynamically determining and/or adjusting the pattern of interrupt message delivery, whether the current command queue 711 or 721 is at a high queue depth or a low queue depth, a balance can be struck between increasing the system load on the host system 11 and reducing the data processing speed of the host system 11 and/or the memory storage device 10. For example, if the current command queue 711 or 721 is in a high queue depth state, the memory management circuit 502 may reduce the transmission frequency of the interrupt information to reduce the frequency of switching between the host command processing program and the checking program of the host system 11. Alternatively, if the current command queue 711 or 721 is in a low queue depth state, the memory management circuit 502 may increase (or not decrease) the transmission frequency of the interrupt information to increase the data processing speed of the host system 11 and/or the memory storage device 10.
In an exemplary embodiment, the determined transmission mode may include a first mode and a second mode. The first pattern corresponds to a first rule for transmitting interrupt information, the second pattern corresponds to a second rule for transmitting interrupt information, and the first rule is different from the second rule. According to different modes and/or rules, the memory management circuitry 502 may control the frequency at which the interrupt control circuitry 724 transmits interrupt information.
In one exemplary embodiment, the first rule is used to reduce the frequency of interrupt message transmissions. In an exemplary embodiment, the second rule is to increase (or not decrease) the transmission frequency of the interrupt message or to return the transmission frequency of the interrupt message to the normal transmission frequency.
Referring to fig. 5 and fig. 7, in an exemplary embodiment, the memory control circuit unit 404 further includes a detection circuit 513. The detection circuit 513 is configured to detect instruction processing information. In an example embodiment, the detected instruction processing information includes the number of instructions to be processed in instruction permutation 711 or 721. For example, the detection circuit 513 may count a count value. The detection circuit 513 may increment this count when it detects that a new instruction is added to the instruction queue 711 or 721. Accordingly, according to the count value, the detection circuit 513 can obtain the number of currently pending instructions and notify the memory management circuit 502. In an example embodiment, the detection circuit 513 may detect and count the number of instructions received and the number of instructions completed in the instruction arrangement 711 or 721. The detection circuit 513 may determine the number of instructions to be processed based on the difference between the number of instructions received and the number of instructions completed.
In an exemplary embodiment, the memory management circuit 502 may determine the transfer mode based on whether the number of pending instructions is greater than a threshold (e.g., 8). For example, the memory management circuit 502 may determine whether the number of instructions to be processed is greater than the threshold. If the number of pending instructions is greater than the threshold, memory management circuit 502 may set the mode of forwarding interrupt information to the first mode. Alternatively, if the number of instructions to be processed is not greater than the threshold, the memory management circuit 502 may set the transmission mode of the interrupt message to the second mode. It should be noted that the threshold value may also be a positive integer such as 7 or 9, and the invention is not limited thereto.
In an example embodiment, the memory management circuit 502 may continue to count the number of completion messages that have been sent. Based on the first mode, after the number of completion messages sent reaches the preset number, the memory management circuit 502 may instruct the interrupt control circuit 724 to send the interrupt message to the host system 11. However, based on the second mode, before the number of sent completion messages reaches the predetermined number, the memory management circuit 502 may instruct the interrupt control circuit 724 to send the interrupt message to the host system 11.
In an example embodiment, based on the first mode, the memory management circuit 502 may enable an interrupt control mechanism (also referred to as a first interrupt control mechanism). The enabled first interrupt control mechanism is used to control sending of the interrupt message to the host system 11 after the number of sent completion messages reaches a predetermined number. However, based on the second mode, the memory management circuit 502 may disable (or not enable) the first interrupt control mechanism.
In an exemplary embodiment, after enabling the first interrupt control mechanism, memory management circuit 502 counts the number of completion messages sent to control the delivery of interrupt messages. In an example embodiment, the memory management circuit 502 may not count the number of completion messages sent without enabling the first interrupt control mechanism.
FIG. 8 is a diagram illustrating the transmission of interrupt information based on a first mode according to an exemplary embodiment of the invention. The horizontal axis direction is time, and the preset number is assumed to be 10.
Referring to fig. 7 and 8, in the first mode, completion messages 801-810 are sequentially sent to the host system 11. The completion information 801 to 810 respectively correspond to one executed operation instruction. In response to the number of sent completion messages 801-810 (i.e., 10) reaching the predetermined number, the memory management circuit 502 may instruct the interrupt control circuit 724 to send the interrupt message 811 to the host system 11. However, in the first mode, the memory management circuit 502 temporarily does not instruct the interrupt control circuit 724 to transfer the interrupt information 811 to the host system 11 until the completion information 810 has not been transferred. Alternatively, from another perspective, based on the first mode, if the number of the completion messages sent does not reach the predetermined number, the memory management circuit 502 temporarily disables the interrupt control circuit 724 from sending the interrupt message 811 to the host system 11 until all of the completion messages 801-810 have been sent. In the exemplary embodiment of FIG. 8, the transmission or non-transmission of the interrupt information 811 is controlled by the first interrupt control mechanism being enabled. Further, the processor 11 of the host system 11 can know that the 10 instructions corresponding to the completion information 801 to 810 have been executed, respectively, based on the interrupt information 811.
FIG. 9 is a diagram illustrating the transmission of interrupt information based on a second mode according to an exemplary embodiment of the invention. The horizontal axis direction is time, and the preset number is assumed to be 10.
Referring to FIG. 7 and FIG. 9, based on the second mode, the completion messages 901-903 and the interrupt messages 911-913 are sequentially sent to the host system 11. The completion information 901 to 903 respectively correspond to one operation instruction that has been executed. The interruption information 911 to 913 are transmitted corresponding to the completion information 901 to 903, respectively. That is, before the number of sent completion messages 901-903 (i.e., 3) reaches the preset number (i.e., 10), the memory management circuit 502 instructs the interrupt control circuit 724 to sequentially send the interrupt messages 911-913 to the host system 11. In the example embodiment of FIG. 9, the first interrupt control mechanism is not enabled, so the transmission of the interrupt messages 911-913 is not controlled by the first interrupt control mechanism. Further, the processor 11 of the host system 11 can know that the execution of the 3 instructions corresponding to the completion information 901 to 903 is completed, based on the interrupt information 911 to 913.
It should be noted that, although the predetermined number is assumed to be 10 in the example embodiments of fig. 8 and 9, in other example embodiments, the predetermined number may be set to be an integer greater than 1, such as 6 or 11, and the invention is not limited thereto.
In the example embodiment of FIG. 8, memory management circuit 502 instructs interrupt control circuit 724 to send interrupt information 811 to host system 11 according to the first number (e.g., 10) of completion messages 801-810 that have been sent. In the example embodiment of FIG. 9, the memory management circuit 502 instructs the interrupt control circuit 724 to send the interrupt information 911 to the host system 11 according to the sent second number (e.g., 1) of completion information 901. In another exemplary embodiment, the first number and/or the second number may be other integers greater than 1 as long as the first number is greater than the second number. For example, in another exemplary embodiment of fig. 9, the interrupt message 911 may also be transmitted to the host system 11 according to the sent 2 completion messages 901 and 902, and the interrupt message 911 may inform the host system 11 that the instructions corresponding to the completion messages 901 and 902, respectively, have been executed.
In an exemplary embodiment, based on the first mode, after the counted time reaches the predetermined time, the memory management circuit 502 may instruct the interrupt control circuit 724 to send an interrupt message to the host system 11. For example, after transmitting certain interrupt information, the interrupt control circuit 724 may start a timer (or counter) to start timing. If the count time of the timer reaches the predetermined time (e.g., 1 second) and no interrupt message is sent within the predetermined time, the memory management circuit 502 may instruct the interrupt control circuit 724 to provide an interrupt message to the host system 11 according to one or more completion messages sent within the count time. Therefore, the response timeout of the interrupt information can be avoided. However, in the second mode, before the counting time reaches the predetermined time, the memory management circuit 502 may instruct the interrupt control circuit 724 to send the interrupt message to the host system 11.
In an example embodiment, based on the first mode, the memory management circuit 502 may enable another interrupt control mechanism (also referred to as a second interrupt control mechanism). The enabled second interrupt control mechanism is used to control sending the interrupt message to the host system 11 after the counting time reaches the predetermined time. However, based on the second mode, the memory management circuit 502 may disable (or not enable) the second interrupt control mechanism.
In an exemplary embodiment, after the second interrupt control mechanism is enabled, the interrupt control circuit 724 starts a timer to time and accordingly control the transmission of the interrupt message. In an example embodiment, the memory management circuit 502 may not start the timer without enabling the second interrupt control mechanism.
It is noted that the first interrupt control mechanism and the second interrupt control mechanism can be enabled simultaneously in the first mode. For example, in the exemplary embodiment of FIG. 8, it is assumed that both the first interrupt control mechanism and the second interrupt control mechanism are enabled and the predetermined number is 10. Based on the first mode, if only 9 pieces of completion information 801 to 809 are accumulated and the counting time from sending the completion information 801 reaches a predetermined time (e.g., 1 second), even if the interrupt information sending condition of the first interrupt control mechanism is not satisfied (i.e., the number of sent completion information is greater than the predetermined number), the interrupt information 811 can be sent to the host system 11 under the control of the second interrupt control mechanism to avoid the response timeout.
In an exemplary embodiment, the first interrupt control mechanism and the second interrupt control mechanism may be enabled simultaneously in the first mode, and the second interrupt control mechanism is enabled but not the first interrupt control mechanism in the second mode. In an exemplary embodiment, the transmission mode of the interrupt information may further include more modes, not limited to the first mode and the second mode.
In an exemplary embodiment, the interrupt information transmission status reflects a transmission status or a transmission mode of the interrupt information within a predetermined time range. For example, this interrupt information transmission state may include a transmission record of interrupt information. The memory management circuit 502 may dynamically adjust the transmission mode of the interrupt information according to the transmission state or transmission mode of the interrupt information within a past period of time (i.e., a preset time range). For example, in an exemplary embodiment, if the sending status of the interrupt message reflects that N times (N is greater than or equal to 1) of the timeout event occurs within the predetermined time range, the memory management circuit 502 may switch the transmission mode of the interrupt message from the first mode to the second mode. For example, in the first mode, if N times of events (i.e., response timeout events of the interrupt information) occur continuously or within a preset time range, wherein the events send the interrupt information because the interrupt information sending condition of the second interrupt control mechanism is satisfied (i.e., the counting time reaches the preset time), the memory management circuit 502 may dynamically switch the transmission mode of the interrupt information to the second mode to disable the first interrupt control mechanism and/or the second interrupt control mechanism.
FIG. 10 is a flowchart illustrating a memory management method according to an exemplary embodiment of the invention. Referring to fig. 10, in step S1001, a first instruction is received and a first operation is performed corresponding to the first instruction. In step S1002, a completion message is sent to the host system corresponding to completion of the first operation. In step S1003, instruction processing information is detected. In step S1004, the transmission mode of the interrupt information is determined based on the instruction processing information. In step S1005, the interrupt information is transmitted to the host system according to the transmission mode.
However, the steps in fig. 10 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 10 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 10 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.
In summary, after receiving the first command and completing the first operation corresponding to the first command, a completion message may be sent to the host system. Meanwhile, according to the detected instruction processing information, the transmission mode of the interrupt information can be determined. Based on the determined transfer mode, an interrupt message may be transferred to the host system. By dynamically determining the transmission mode of the interrupt message, the interrupt message can be properly transmitted to the host system no matter the depth of the command arrangement is deep or shallow, so as to avoid the response timeout or the host system switching between the host command processing program and the checking program too frequently.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (30)

1. A memory management method for a memory storage device including a rewritable non-volatile memory module, the memory management method comprising:
receiving a first instruction and executing a first operation corresponding to the first instruction;
sending a completion message to the host system corresponding to completion of the first operation;
detecting instruction processing information;
determining a transfer mode of interrupt information according to the instruction processing information, wherein the instruction processing information is used for reflecting at least one of the number of received instructions, the number of completed instructions, the number of instructions to be executed and an interrupt information sending state, the interrupt information is used for interrupting a host instruction processing program of the host system, the transfer mode comprises a first mode and a second mode, the first mode corresponds to a first rule for transferring the interrupt information, the second mode corresponds to a second rule for transferring the interrupt information, and the first rule is different from the second rule; and
and transmitting the interrupt information to the host system according to the transmission mode.
2. The memory management method according to claim 1, wherein the step of detecting the instruction processing information includes:
determining the number of instructions to be executed according to a difference between the number of instructions received and the number of instructions completed.
3. The memory management method of claim 1, wherein determining the transmission mode of the interrupt information according to the instruction processing information comprises:
the transmission mode is determined according to whether the number of instructions to be executed is greater than a threshold value.
4. The memory management method according to claim 1, wherein the interrupt information transmission state reflects a transmission state or a transmission mode of the interrupt information within a preset time range,
wherein determining the transmission mode of the interrupt information according to the instruction processing information comprises:
and if the sending state of the interrupt information reflects that N times of response timeout events of the interrupt information occur within the preset time range, switching the transmission mode of the interrupt information from a first mode to a second mode, wherein N is a positive integer not less than 1.
5. The memory management method of claim 1, wherein the step of transmitting the interrupt information to the host system according to the transmission mode comprises:
in a first mode, after the number of the completion messages sent reaches a preset number, sending the interrupt message to the host system; and
in a second mode, the interrupt message is sent to the host system before the number of the completion messages sent reaches the preset number, wherein the preset number is greater than one.
6. The memory management method of claim 5, wherein the step of transmitting the interrupt information to the host system according to the transmission mode further comprises:
in the first mode, enabling a first interrupt control mechanism, wherein the enabled first interrupt control mechanism is configured to control sending of the interrupt message to the host system after the number of the completion messages sent reaches the predetermined number; and
in the second mode, the first interrupt control mechanism is disabled.
7. The memory management method of claim 1, wherein transmitting the interrupt information to the host system according to the transmission mode comprises:
in the first mode, after the counting time reaches the preset time, transmitting the interrupt information to the host system; and
in a second mode, the interrupt information is transmitted to the host system before the counted time reaches the preset time.
8. The memory management method of claim 7, wherein the step of transmitting the interrupt information to the host system according to the transmission mode further comprises:
in the first mode, enabling a second interrupt control mechanism, wherein the enabled second interrupt control mechanism is configured to control sending the interrupt message to the host system after the counting time reaches the preset time; and
in the second mode, the second interrupt control mechanism is disabled.
9. The memory management method of claim 1, wherein transmitting the interrupt information to the host system according to the transmission mode comprises:
in a first mode, transmitting the interrupt information to the host system according to a first number of the completion information that has been sent; and
in a second mode, transmitting the interrupt information to the host system according to the sent second number of the completion information,
wherein the first number is greater than the second number.
10. The method of claim 9, wherein the first number is an integer greater than one and the second number is one.
11. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuitry is to receive a first instruction and to perform a first operation corresponding to the first instruction,
wherein the memory control circuitry unit is further configured to send a completion message to the host system corresponding to completion of the first operation,
wherein the memory control circuitry unit is further to detect instruction processing information,
wherein the memory control circuit unit is further configured to determine a transfer mode of interrupt information according to the instruction processing information, the instruction processing information being configured to reflect at least one of a number of received instructions, a number of completed instructions, a number of instructions to be executed, and an interrupt information sending status, the interrupt information being configured to interrupt a host instruction processing program of the host system, the transfer mode including a first mode and a second mode, the first mode corresponding to a first rule for transferring the interrupt information, the second mode corresponding to a second rule for transferring the interrupt information, and the first rule being different from the second rule,
wherein the memory control circuitry is further configured to transmit the interrupt information to the host system according to the transmission mode.
12. The memory storage device according to claim 11, wherein the operation of the memory control circuit unit detecting the instruction processing information comprises:
determining the number of instructions to be executed according to a difference between the number of instructions received and the number of instructions completed.
13. The memory storage device according to claim 11, wherein the operation of the memory control circuit unit deciding the transmission mode of the interrupt information according to the instruction processing information includes:
the transmission mode is determined based on whether the number of instructions to be executed is greater than a threshold.
14. The memory storage device according to claim 11, wherein the interrupt information transmission status reflects a transmission status or a transmission mode of the interrupt information within a preset time range,
wherein the step of the memory control circuit unit deciding the transmission mode of the interrupt information according to the instruction processing information comprises:
and if the sending state of the interrupt information reflects that N times of response timeout events of the interrupt information occur within the preset time range, switching the transmission mode of the interrupt information from a first mode to a second mode, wherein N is a positive integer not less than 1.
15. The memory storage device of claim 11, wherein the operation of the memory control circuitry unit to transmit the interrupt information to the host system according to the transmission mode comprises:
in a first mode, after the number of the completion messages sent reaches a preset number, sending the interrupt message to the host system; and
in a second mode, transmitting the interrupt information to the host system before the number of the completion information that has been transmitted reaches the preset number,
wherein the predetermined number is greater than one.
16. The memory storage device of claim 15, wherein the operation of the memory control circuitry unit to transfer the interrupt information to the host system according to the transfer mode further comprises:
in the first mode, enabling a first interrupt control mechanism, wherein the enabled first interrupt control mechanism is configured to control sending of the interrupt message to the host system after the number of the completion messages sent reaches the predetermined number; and
in the second mode, the first interrupt control mechanism is disabled.
17. The memory storage device of claim 11, wherein the operation of the memory control circuitry unit to transmit the interrupt information to the host system according to the transmission mode comprises:
in the first mode, after the counting time reaches the preset time, transmitting the interrupt information to the host system; and
in a second mode, the interrupt information is transmitted to the host system before the counted time reaches the preset time.
18. The memory storage device of claim 17, wherein the operation of the memory control circuitry unit to transmit the interrupt information to the host system according to the transmission mode further comprises:
in the first mode, enabling a second interrupt control mechanism, wherein the enabled second interrupt control mechanism is configured to control sending the interrupt message to the host system after the counting time reaches the preset time; and
disabling the second interrupt control mechanism in the second mode.
19. The memory storage device of claim 11, wherein the operation of the memory control circuitry unit to transmit the interrupt information to the host system according to the transmission mode comprises:
in a first mode, transmitting the interrupt information to the host system according to a first number of the completion information that has been sent; and
in a second mode, transmitting the interrupt information to the host system according to the sent second number of the completion information,
wherein the first number is greater than the second number.
20. The memory storage device of claim 19, wherein the first number is an integer greater than one and the second number is one.
21. A memory control circuit unit, for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:
a host interface for connecting to a host system;
a memory interface for connecting to the rewritable nonvolatile memory module;
a detection circuit;
an interrupt control circuit; and
a memory management circuit connected to the host interface, the memory interface, the detection circuit, and the interrupt control circuit,
wherein the memory management circuit is to receive a first instruction and perform a first operation corresponding to the first instruction,
wherein the memory management circuitry is further to send a completion message to the host system corresponding to completion of the first operation,
wherein the detection circuit is to detect instruction processing information,
wherein the memory management circuit is further configured to determine a transfer mode of interrupt information according to the instruction processing information, the instruction processing information being configured to reflect at least one of a number of received instructions, a number of completed instructions, a number of instructions to be executed, and an interrupt information sending status, the interrupt information being configured to interrupt a host instruction processing program of the host system, the transfer mode including a first mode and a second mode, the first mode corresponding to a first rule for transferring the interrupt information, the second mode corresponding to a second rule for transferring the interrupt information, and the first rule being different from the second rule,
wherein the memory management circuitry is further configured to instruct the interrupt control circuitry to transmit the interrupt information to the host system according to the transmission mode.
22. The memory control circuit unit of claim 21, wherein the operation of the detection circuit to detect the instruction processing information comprises:
determining the number of instructions to be executed according to a difference between the number of instructions received and the number of instructions completed.
23. The memory control circuit unit of claim 21, wherein the operation of the memory management circuit to determine the transmission mode of the interrupt information according to the instruction processing information comprises:
the transmission mode is determined based on whether the number of instructions to be executed is greater than a threshold.
24. The memory control circuit unit according to claim 21, wherein the interrupt information transmission state reflects a transmission state or a transmission mode of the interrupt information within a preset time range,
wherein the step of the memory management circuit deciding the transmission mode of the interrupt information according to the instruction processing information comprises:
and if the sending state of the interrupt information reflects that N times of response timeout events of the interrupt information occur within the preset time range, switching the transmission mode of the interrupt information from a first mode to a second mode, wherein N is a positive integer not less than 1.
25. The memory control circuit unit of claim 21, wherein the operation of the memory management circuit instructing the interrupt control circuit to transfer the interrupt information to the host system according to the transfer mode comprises:
in a first mode, after the number of the completion messages sent reaches a preset number, sending the interrupt message to the host system; and
in a second mode, transmitting the interrupt information to the host system before the number of the completion information that has been transmitted reaches the preset number,
wherein the predetermined number is greater than one.
26. The memory control circuitry unit of claim 25, wherein said memory management circuitry being configured to instruct said interrupt control circuitry to transmit said interrupt information to said host system according to said transfer mode further comprises:
in the first mode, enabling a first interrupt control mechanism, wherein the enabled first interrupt control mechanism is configured to control sending of the interrupt message to the host system after the number of the completion messages sent reaches the predetermined number; and
in the second mode, the first interrupt control mechanism is disabled.
27. The memory control circuitry unit of claim 21, wherein the operation of the memory management circuitry to instruct the interrupt control circuitry to transfer the interrupt information to the host system according to the transfer mode comprises:
in the first mode, after the counting time reaches the preset time, transmitting the interrupt information to the host system; and
in a second mode, the interrupt information is transmitted to the host system before the counted time reaches the preset time.
28. The memory control circuitry unit of claim 27, wherein said memory management circuitry being configured to instruct said interrupt control circuitry to transmit said interrupt information to said host system according to said transfer mode further comprises:
in the first mode, enabling a second interrupt control mechanism, wherein the enabled second interrupt control mechanism is configured to control sending the interrupt message to the host system after the counting time reaches the predetermined time; and
disabling the second interrupt control mechanism in the second mode.
29. The memory control circuit unit of claim 21, wherein the operation of the memory management circuit instructing the interrupt control circuit to transfer the interrupt information to the host system according to the transfer mode comprises:
in a first mode, transmitting the interrupt information to the host system according to a first number of the completion information that has been sent; and
in a second mode, transmitting the interrupt information to the host system according to the sent second number of the completion information,
wherein the first number is greater than the second number.
30. The memory control circuit cell of claim 29, wherein the first number is an integer greater than one and the second number is one.
CN201810694015.0A 2018-06-29 2018-06-29 Memory management method, memory storage device and memory control circuit unit Active CN110659229B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810694015.0A CN110659229B (en) 2018-06-29 2018-06-29 Memory management method, memory storage device and memory control circuit unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810694015.0A CN110659229B (en) 2018-06-29 2018-06-29 Memory management method, memory storage device and memory control circuit unit

Publications (2)

Publication Number Publication Date
CN110659229A CN110659229A (en) 2020-01-07
CN110659229B true CN110659229B (en) 2022-11-08

Family

ID=69027502

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810694015.0A Active CN110659229B (en) 2018-06-29 2018-06-29 Memory management method, memory storage device and memory control circuit unit

Country Status (1)

Country Link
CN (1) CN110659229B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434643B1 (en) * 1998-04-15 2002-08-13 Seiko Epson Corporation Transmission of status information by a selected one of multiple transfer modes based on the cause for sending the status information
TW201222256A (en) * 2010-11-22 2012-06-01 Phison Electronics Corp Memory storage device, memory controller thereof, and method for responding instruction sent from host thereof
TWI534607B (en) * 2015-10-19 2016-05-21 群聯電子股份有限公司 Memory control circuit unit, data transmitting method and memory storage apparatus
TW201721653A (en) * 2015-12-04 2017-06-16 群聯電子股份有限公司 Memory management method, memory control circuit unit, and memory storage apparatus
CN107766006A (en) * 2017-11-07 2018-03-06 合肥兆芯电子有限公司 Storage management method, memory storage apparatus and memorizer control circuit unit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7165141B2 (en) * 2004-02-27 2007-01-16 Hewlett-Packard Development Company, L.P. Daisy-chained device-mirroring architecture
JP2008084043A (en) * 2006-09-28 2008-04-10 Fujitsu Ltd Interruption processing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6434643B1 (en) * 1998-04-15 2002-08-13 Seiko Epson Corporation Transmission of status information by a selected one of multiple transfer modes based on the cause for sending the status information
TW201222256A (en) * 2010-11-22 2012-06-01 Phison Electronics Corp Memory storage device, memory controller thereof, and method for responding instruction sent from host thereof
TWI534607B (en) * 2015-10-19 2016-05-21 群聯電子股份有限公司 Memory control circuit unit, data transmitting method and memory storage apparatus
TW201721653A (en) * 2015-12-04 2017-06-16 群聯電子股份有限公司 Memory management method, memory control circuit unit, and memory storage apparatus
CN107766006A (en) * 2017-11-07 2018-03-06 合肥兆芯电子有限公司 Storage management method, memory storage apparatus and memorizer control circuit unit

Also Published As

Publication number Publication date
CN110659229A (en) 2020-01-07

Similar Documents

Publication Publication Date Title
US10664167B2 (en) Data transmitting method, memory storage device and memory control circuit unit
US11086564B2 (en) Temperature control method, memory storage device and memory control circuit unit
CN111078146B (en) Memory management method, memory storage device and memory control circuit unit
TW202040370A (en) Data writing method, memory controlling circuit unit and memory storage device
CN107817943B (en) Data transmission method, memory storage device and memory control circuit unit
TWI796882B (en) Read disturb checking method, memory storage device and memory control circuit unit
US11960762B2 (en) Method for managing memory buffer and memory control circuit unit and memory storage apparatus thereof
CN106874223B (en) Data transmission method, memory storage device and memory control circuit unit
TWI672593B (en) Memory management method, memory storage device and memory control circuit unit
CN113504880B (en) Memory buffer management method, memory control circuit unit and memory device
CN110659229B (en) Memory management method, memory storage device and memory control circuit unit
CN114822664A (en) Risk assessment method based on data priority, storage device and control circuit
US10884660B2 (en) Memory management method, memory storage device and memory control circuit unit
CN112732199A (en) Data access method, memory control circuit unit and memory storage device
CN114115739B (en) Memory management method, memory storage device and memory control circuit unit
CN111831210A (en) Memory management method, memory control circuit unit and memory storage device
CN117632038B (en) Wear leveling method, memory storage device and memory control circuit unit
CN113360429B (en) Data reconstruction method, memory storage device and memory control circuit unit
CN112799973B (en) Encoding control method, memory storage device and memory control circuit unit
CN110908591B (en) Memory management method, memory storage device and memory control circuit unit
CN110580230B (en) Memory management method, memory storage device and memory control circuit unit
CN115857808A (en) Memory management method, memory storage device and memory control circuit unit
CN114371877A (en) Instruction management method, memory storage device and memory control circuit unit
CN114385244A (en) Memory management method, memory storage device and memory control circuit unit
CN116954508A (en) Memory management method, memory storage device and memory control circuit unit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant