CN110659112A - Algorithm scheduling method and system - Google Patents
Algorithm scheduling method and system Download PDFInfo
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- CN110659112A CN110659112A CN201810699466.3A CN201810699466A CN110659112A CN 110659112 A CN110659112 A CN 110659112A CN 201810699466 A CN201810699466 A CN 201810699466A CN 110659112 A CN110659112 A CN 110659112A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5017—Task decomposition
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/508—Monitor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of multiprocessors, and discloses an algorithm scheduling method and system for reasonably integrating computing resources of a multiprocessor efficiently and orderly. The method comprises the following steps: splitting an application object algorithm into at least two associated sub-algorithms; counting the resource consumption and response speed of each sub-algorithm required by processing in the main processor; determining a scheduling criterion related to the real-time load of the main processor according to the resource consumption and the response speed; and distributing the related sub-algorithms to the master processor or the slave processor for calculation processing according to the scheduling criteria.
Description
Technical Field
The invention relates to the technical field of multiprocessors, in particular to an algorithm scheduling method and system.
Background
An FPGA (Field-Programmable Gate Array), which is a product of further development based on Programmable devices such as PAL, GAL, CPLD, etc. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
The FPGA adopts a concept of a Logic Cell array lca (Logic Cell array), and includes three parts, namely, a configurable Logic module clb (configurable Logic block), an input Output module iob (input Output block), and an internal connection (Interconnect). FPGAs are programmable devices that have a different structure than traditional logic circuits and gate arrays (e.g., PAL, GAL, and CPLD devices). The FPGA utilizes small lookup tables (16 × 1RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming.
FPGAs are generally applicable to hardware acceleration of algorithms, however, in a multiprocessor system, how to utilize resources of multiple processors for co-processing of the same application object has been a problem commonly faced by those skilled in the art.
Disclosure of Invention
The invention aims to disclose an algorithm scheduling method and system to reasonably and efficiently and orderly integrate computing resources of a multiprocessor.
In order to achieve the above object, the present invention discloses an algorithm scheduling method, which comprises:
splitting an application object algorithm into at least two associated sub-algorithms;
counting the resource consumption and response speed of each sub-algorithm required by processing in the main processor;
determining a scheduling criterion related to the real-time load of the main processor according to the resource consumption and the response speed;
and distributing the related sub-algorithms to the master processor or the slave processor for calculation processing according to the scheduling criteria.
Preferably, the application objects of the invention comprise a rectification control object and an inversion control object, and each application object adopts the same scheduling criterion; the split sub-algorithm is a sub-algorithm with strict requirements on resource consumption and response speed.
Preferably, the slave processor adopts an FPGA chip, the master processor adopts a CPU, and the scheduling criteria include:
establishing a coordinate system, wherein the coordinate system takes the response speed as an abscissa and takes the resource consumption as an ordinate;
carrying out normalization processing on the resource consumption and the response speed counted by each sub-algorithm of the same application object;
drawing a circle by taking a uniform classification threshold value of each application object as a radius, defaulting a sub-algorithm in the circle as a dynamic scheduling algorithm, defaulting an algorithm close to the horizontal coordinate outside the circle to be allocated to the FPGA for execution, and defaulting an algorithm close to the vertical coordinate outside the circle to be allocated to the CPU for execution;
when the real-time load of the CPU is smaller than a first load threshold value, distributing all dynamic scheduling algorithms in a circle to the CPU for execution;
when the real-time load of the CPU is greater than or equal to a first load threshold and smaller than a second load threshold, sequencing the response speed of the in-circle dynamic scheduling algorithm, and distributing partial sub-algorithms with high response speed requirements to the FPGA for execution;
when the real-time load of the CPU is greater than or equal to a second load threshold value and less than a third load threshold value, distributing all dynamic scheduling algorithms in a circle to the FPGA for execution;
and when the real-time load of the CPU is greater than or equal to a third load threshold value, transferring the sub-algorithm with the maximum resource consumption in the CPU to the FPGA for execution.
Corresponding to the method, the invention also discloses an algorithm scheduling system, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the steps of the method when executing the computer program.
The invention has the following beneficial effects:
the application object algorithm is divided into at least two associated sub-algorithms, and the sub-algorithms are reasonably, efficiently and orderly integrated in computing resources among the multiple processors by relying on a scheduling criterion, so that the overall performance of the system is improved.
The present invention will be described in further detail below with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a flowchart of an algorithm scheduling method of a preferred embodiment of the present invention;
fig. 2 is a diagram illustrating a matching scheduling criterion according to this embodiment.
Detailed Description
The embodiments of the invention will be described in detail below with reference to the drawings, but the invention can be implemented in many different ways as defined and covered by the claims.
Example 1
The embodiment discloses an algorithm scheduling method which is applied to a multiprocessor system. As an example, the multiprocessor system of the present embodiment includes a CPU main processor and an FPGA sub processor.
As shown in fig. 1, the method of the present embodiment includes:
and step S1, splitting the application object algorithm into at least two associated sub-algorithms.
In this step, the split sub-algorithm is a sub-algorithm with strict requirements on resource consumption and response speed. The application object refers to a control object for specific software and hardware products in the fields of locomotives, subways, industrial transmission and the like. For example: related application objects include, but are not limited to: the rectification control target may be an inverter control target or the like.
On the other hand, in the embodiment, different application objects have different algorithms, and algorithms related to some application objects are relatively low in complexity, and relatively few sub-algorithms can be stripped for performing algorithm scheduling. However, some sub-algorithms may be the same for different application objects.
And step S2, counting the resource consumption and response speed required by the processing of each sub algorithm in the main processor.
In this step, if the main processor is a CPU, the corresponding resource consumption is mainly the CPU occupancy rate.
And step S3, determining a scheduling criterion related to the real-time load of the main processor according to the resource consumption and the response speed.
In this step, to simplify system design and reduce management and maintenance costs, it is preferable that the same scheduling criteria be used for each application object. As shown in fig. 2, one specific scheduling criteria may be:
establishing a coordinate system, wherein the coordinate system takes the response speed as an abscissa and takes the resource consumption as an ordinate; carrying out normalization processing on the resource consumption and the response speed counted by each sub-algorithm of the same application object; drawing a circle by taking a uniform classification threshold of each application object as a radius, defaulting a sub-algorithm in the circle as a dynamic scheduling algorithm, defaulting an algorithm close to the horizontal coordinate outside the circle to be allocated to FPGA (field programmable gate array) execution, and defaulting an algorithm close to the vertical coordinate outside the circle to be allocated to CPU (central processing unit) execution; when the real-time load of the CPU is smaller than a first load threshold value, distributing all dynamic scheduling algorithms in the circle to the CPU for execution; when the real-time load of the CPU is greater than or equal to the first load threshold and less than the second load threshold, sequencing the response speed of the in-circle dynamic scheduling algorithm, and distributing part of sub-algorithms with high response speed requirements to the FPGA for execution; when the real-time load of the CPU is greater than or equal to the second load threshold value and less than a third load threshold value, distributing all dynamic scheduling algorithms in the circle to the FPGA for execution; and when the real-time load of the CPU is greater than or equal to a third load threshold value, transferring the sub-algorithm with the largest resource consumption in the CPU to the FPGA for execution.
In the invention, the classification threshold is used for dividing each sub-algorithm into three categories of a dynamic scheduling algorithm, a default CPU execution algorithm and a default FPGA execution algorithm; corresponding to fig. 2, the classification threshold is 0.7, and the discrete points in the upper right corner represent a corresponding sub-algorithm. The criterion for determining the proximity abscissa or ordinate may be y ═ x as a boundary, and taking the first quadrant as an example, the left side of the boundary is proximate to the ordinate, and the right side of the boundary is proximate to the abscissa.
Therefore, the scheduling criterion of the embodiment has ordered levels, high refinement degree and convenient implementation.
And step S4, distributing the related sub-algorithms to the master processor or the slave processor according to the scheduling criteria for calculation processing.
In this step, preferably, at least two sub-algorithms in series assigned to the FPGA execution can be executed by time-division multiplexing of the reconfiguration partitions for the same FPGA.
In summary, the method of the embodiment splits the application object algorithm into at least two associated sub-algorithms, and reasonably, efficiently and orderly integrates the computing resources of the sub-algorithms among the multiple processors by relying on the scheduling criteria, thereby improving the overall performance of the system.
Example 2
Corresponding to the above method, the present embodiment discloses an algorithm scheduling system, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.
Similarly, the system of the embodiment splits the application object algorithm into at least two associated sub-algorithms, and reasonably, efficiently and orderly integrates the computing resources of the sub-algorithms among the multiple processors by relying on the scheduling criteria, thereby improving the overall performance of the system.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. An algorithm scheduling method, comprising:
splitting an application object algorithm into at least two associated sub-algorithms;
counting the resource consumption and response speed of each sub-algorithm required by processing in the main processor;
determining a scheduling criterion related to the real-time load of the main processor according to the resource consumption and the response speed;
and distributing the related sub-algorithms to the master processor or the slave processor for calculation processing according to the scheduling criteria.
2. The algorithmic scheduling method of claim 1, wherein the application objects comprise a rectification control object and an inversion control object, and each application object uses the same scheduling criteria.
3. The algorithm scheduling method according to claim 2, wherein the slave processor adopts an FPGA chip, the master processor adopts a CPU, and the scheduling criteria include:
establishing a coordinate system, wherein the coordinate system takes the response speed as an abscissa and takes the resource consumption as an ordinate;
carrying out normalization processing on the resource consumption and the response speed counted by each sub-algorithm of the same application object;
drawing a circle by taking a uniform classification threshold value of each application object as a radius, defaulting a sub-algorithm in the circle as a dynamic scheduling algorithm, defaulting an algorithm close to the horizontal coordinate outside the circle to be allocated to the FPGA for execution, and defaulting an algorithm close to the vertical coordinate outside the circle to be allocated to the CPU for execution;
when the real-time load of the CPU is smaller than a first load threshold value, distributing all dynamic scheduling algorithms in a circle to the CPU for execution;
when the real-time load of the CPU is greater than or equal to a first load threshold and smaller than a second load threshold, sequencing the response speed of the in-circle dynamic scheduling algorithm, and distributing partial sub-algorithms with high response speed requirements to the FPGA for execution;
when the real-time load of the CPU is greater than or equal to a second load threshold value and less than a third load threshold value, distributing all dynamic scheduling algorithms in a circle to the FPGA for execution;
and when the real-time load of the CPU is greater than or equal to a third load threshold value, transferring the sub-algorithm with the maximum resource consumption in the CPU to the FPGA for execution.
4. The algorithm scheduling method of any one of claims 1 to 3, further comprising:
and executing at least two serially connected sub-algorithms which are distributed to the FPGA through time division multiplexing of the reconfiguration partitions of the same FPGA.
5. The algorithm scheduling method of any one of claims 1 to 3 wherein the split sub-algorithms are sub-algorithms with strict requirements on resource consumption and response speed.
6. An algorithmic scheduling system comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 5 when executing the computer program.
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