CN110658885B - Clock tree synthesis method - Google Patents

Abstract

The invention discloses a clock tree synthesis method, which comprises the following steps: determining a driving force of a clock unit; determining a reserved space corresponding to the clock unit according to the driving force; generating the clock unit and the reserved space, wherein the reserved space is adjacent to the clock unit; arranging a decoupling capacitance filling unit in the reserved space, wherein the area and/or the capacitance value of the decoupling capacitance filling unit is related to the driving force; and fixing the properties of the clock unit and the decoupling capacitor filling unit.

Description

Clock tree synthesis method

Technical Field

The present invention relates to clock trees, and more particularly, to a clock tree synthesis method.

Background

Clock trees are commonly found in modern integrated circuits, and fig. 1 is a schematic diagram of a conventional circuit layout, which includes two clock trees-clock tree 112 and clock tree 122. The clock tree 112 is composed of a plurality of clock cells (clock cells) 115, and the clock tree 122 is composed of a plurality of clock cells 125. A clock unit is for example an inverter or a buffer. The clock tree 112 is electrically connected to the phase-locked loop 110, and the phase-locked loop 110 provides the clock to the registers 132 and 134 through the clock tree 112. The clock tree 122 is electrically connected to the phase-locked loop 120, and the phase-locked loop 120 provides the clock to the registers 136 and 138 through the clock tree 122. The logic circuit 140 is coupled between the register 132 and the register 134, and forms a data path therebetween. The circuit also includes analog circuit 150, memory 160, and I/O circuit 170. For simplicity, the routing among the analog circuit 150, the memory 160, and the I/O circuit 170 and other elements are not shown in FIG. 1.

The clock tree synthesis includes the steps of layout planning (floorplan) and placement optimization (placement optimization) before. Layout refers to arranging the positions of the elements. Placement optimization refers to data path optimization. Since the width of poly (crystal) is getting smaller as the process advances, electro-migration (electro-migration) effect may occur when the driving force (driving strength) of the clock cells is strong. Furthermore, the problem of supply voltage drop (IR drop) needs to be considered in circuit design because the clock unit has higher power consumption as the chip speed is faster, i.e. the switching rate is higher. In view of the above considerations, the clock units are arranged to avoid being too close to each other, so as to reduce the probability that the circuit fails the electromigration test and the supply voltage drop test. However, even if proper intervals are reserved between clock cells during layout, parameters corresponding to the intervals, such as clock cell spacing (clock cell spacing), are not mandatory for physical implementation tools (physical implementation tools), in other words, the parameters are soft constraints (soft constraints) rather than hard constraints (hard constraints), so the intervals may become too small after clock tree synthesis, resulting in the circuit failing to pass the test.

Therefore, it is necessary to provide a clock tree synthesis method to ensure sufficient intervals between clock units or between a clock unit and other elements after clock tree synthesis.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a clock tree synthesis method to improve the probability of the circuit passing the electromigration test and the supply voltage drop test.

The invention discloses a clock tree synthesis method, which comprises the following steps: selecting a clock unit; setting a reserved margin for the clock unit; performing clock tree synthesis to generate the clock unit and a reserved space adjacent to the clock unit, wherein the size of the reserved space corresponds to the reserved margin; arranging a decoupling capacitance filling unit in the reserved space, wherein the area and/or the capacitance value of the decoupling capacitance filling unit is related to the reserved margin; and fixing the properties of the clock unit and the decoupling capacitor filling unit.

The invention also discloses a clock tree synthesis method, which comprises the following steps: determining a driving force of a clock unit; determining a reserved space corresponding to the clock unit according to the driving force; generating the clock unit and the reserved space, wherein the reserved space is adjacent to the clock unit; arranging a decoupling capacitance filling unit in the reserved space, wherein the area and/or the capacitance value of the decoupling capacitance filling unit is related to the driving force; and fixing the properties of the clock unit and the decoupling capacitor filling unit.

The clock tree synthesis method of the invention can ensure that a sufficient space is reserved between a clock unit and another clock unit or between the clock unit and other elements after clock tree synthesis (namely, after the clock unit is formed). Compared with the prior art, the clock tree formed by the clock tree synthesis method is not easy to suffer from the problems of electromigration, power supply voltage reduction and the like, so that the clock tree can pass the test more easily, and the service life and the stability of the circuit can be improved.

The features, implementations and functions of the present invention will be described in detail with reference to the drawings.

Drawings

FIG. 1 is a schematic diagram of a conventional circuit layout;

FIG. 2 is a flow chart of an embodiment of the clock tree synthesis method of the present invention;

FIG. 3 is a plan view of a clock unit with a reserved space;

FIG. 4 is a schematic diagram of a clock unit and its adjacent decoupling capacitance;

FIG. 5 is a detailed flow of step S240 of FIG. 2; and

FIG. 6 is a flow chart of another embodiment of the clock tree synthesis method of the present invention.

Detailed Description

The technical terms of the following description refer to conventional terms in the technical field, and some terms are explained or defined in the specification, and the explanation of the some terms is based on the explanation or definition in the specification.

Part or all of the process of the clock tree synthesis method of the present invention can be in the form of software and/or firmware, and the following description of the method invention will focus on the content of steps rather than hardware without affecting the full disclosure and feasibility of the method invention.

FIG. 2 is a flow chart of an embodiment of a clock tree synthesis method of the present invention. The step of layout planning (step S210) includes selecting a clock cell from a clock cell library (clock cell library). This step determines the driving force of the clock unit, in other words, it selects the clock unit according to the required driving force. However, in order to pass the electromigration test and the supply voltage drop test, the clock unit with the strongest driving force is usually not selected in this step. After step S210 is completed, the method first performs placement optimization (step S215), and then sets a keep-out margin (keep-out margin) of the clock unit (step S220). Step S220 may be set by executing the set _ keepout _ margin instruction or the same functional instruction on the physical implementation tool. For physical implementation, the reserved margin is a hard constraint, and the reserved margin indicates the size of a reserved space adjacent to the clock unit. For example, the reserved margin may indicate an area, a side length, or a perimeter of the reserved space. This remaining margin is related to the driving force of the clock unit. In some embodiments, the greater the driving force of the clock unit, the greater the margin remaining, and the lesser the driving force of the clock unit, the lesser the margin remaining. In general, the larger the driving force of the clock unit, the larger the area of the clock unit, so the area of the reserved space may be proportional to the area of the clock unit, that is, the reserved space may be set according to the size of the clock unit. Larger reserved space enables larger decoupling capacitance.

Next, a clock tree synthesis is performed according to the selected clock unit and the set reserved margin to generate the clock unit and the reserved space (step S230). Fig. 3 is a plan view of the clock unit with a reserved space. The reserved space 315 is adjacent to the clock unit 310. The example of fig. 3 approximates the clock unit 310 as a quadrilateral element, but it is possible to approximate other polygons for the clock unit 310, and the reserved space 315 can be disposed on either side of the clock unit 310. All the clock units with the reserved margin set in step S220 are accompanied by the reserved space after step S230 is completed. Because the reserved margin is treated as a hard constraint by the physical implementation tool, the physical implementation tool may consider that the clock unit with the reserved margin needs to occupy a relatively large space when the step of clock tree synthesis is performed.

Next, a decoupling capacitor filler cell (decoupling capacitor cell) is provided for the clock cell with the reserved margin, that is, a decoupling capacitor is provided in the reserved space 315 (step S240). The area and/or capacitance of the decoupling capacitance is related to the retention space 315 (i.e., related to the retention margin). In some embodiments, the larger the remaining margin or space, the larger the area and capacitance of the decoupling capacitor. In other words, the decoupling capacitance can also be selected according to the driving force or size of the clock unit.

After the step S240 is completed, the clock unit is electrically connected to the decoupling capacitor. FIG. 4 is a schematic diagram of a clock cell and its adjacent decoupling capacitance. Electrically, the decoupling capacitance 415 is connected IN parallel with the clock cell 410 (symbol IN is the input of the clock cell 410 and symbol OUT is the output of the clock cell 410). The decoupling capacitance 415 may mitigate the dynamic droop of the voltage source VDD and thus may mitigate the effect of the supply voltage droop. Then, a routing is performed to properly connect the devices on the circuit (step S250), and finally, optimization after routing is performed (step S260) and a filler cell (filler cell) is performed (step S270). Steps S250 to S270 are conventional steps, and details thereof are not described again. However, unlike the conventional clock tree synthesis method, in the present invention, no decoupling capacitor filling unit is formed in the circuit before steps S250 to S270 (i.e. the clock unit is not connected in parallel with the decoupling capacitor), and in the present invention, the decoupling capacitor filling unit is formed in the circuit when steps S250 to S270 are performed (formed in step S240).

Fig. 5 is a detailed flow of step S240. After the clock tree synthesis is completed and before the remaining margin is not removed, a plurality of filling units are filled in the circuit (step S510). The filling unit is a structure containing polycrystalline bodies but not containing metal. After step S510 is completed, the filling unit is filled with the circuit except for the components (including but not limited to pll, register, logic, analog, memory, i/o circuit), clock unit and reserved space. The remaining margin is removed (step S520). The corresponding instruction in step S520 on the physical implementation tool is remove _ keepout _ margin (or an instruction with the same function). After step S520 is completed, the reserved space on the circuit is no longer occupied for the physical implementation tool, i.e. the physical implementation tool considers that no component is disposed in the reserved space. Next, the decoupling capacitor filling unit is filled in the reserved space (step S530). After step S530 is completed, the clock cells originally having the reserved margin (i.e. the clock cells adjacent to the reserved space) are connected in parallel with the decoupling capacitor (as shown in fig. 4). Finally, the filling unit is removed (step S540), and then the property of the clock unit and the property of the decoupling capacitor filling unit are fixed (step S550). The step S550 can prevent the positions of the clock unit and the decoupling capacitance filling unit from being changed in the following steps. The attribute indicated by step S550 includes, for example, the position information of the clock unit and the decoupling capacitor filling unit.

FIG. 6 is a flow chart of another embodiment of a clock tree synthesis method of the present invention. First, the driving force of the clock unit is determined (step S610), that is, an appropriate clock unit is selected according to the requirement (e.g., the size of the clock tree, the location of the clock unit, etc.). The reserved space of the corresponding clock unit is then determined according to the driving force (step S620), that is, the size of the reserved space is related to the driving force and/or the area of the clock unit. Next, a clock unit and a reserved space are generated, wherein the reserved space is adjacent to the clock unit (as shown in fig. 3) (step S630). Next, a decoupling capacitance filling unit is disposed in the reserved space, wherein the area and/or capacitance value of the decoupling capacitance filling unit is related to the driving force and/or area of the clock unit (step S640). The detailed flow of step S640 is shown in fig. 5. After step S640 is completed, steps S250 to S270 are executed.

In some embodiments, the clock unit 310 and the reserved space 315 of fig. 3 are closely adjacent to each other, and no filling unit can be filled between the two.

The invention can make the physical implementation tool consider the influence of clock delay (clock latency) and clock skew (clock skew) to the circuit after filling the decoupling capacitance filling unit when the clock tree is synthesized, so that the result when the clock tree is synthesized can be consistent with the result after filling the decoupling capacitance filling unit. By setting the reserved margin (i.e. reserved space) before the clock tree synthesis step, and setting the decoupling capacitor filling unit and fixing the properties of the decoupling capacitor filling unit and the clock unit before the winding, the present invention can ensure a certain interval between the clock unit and other clock units or elements by using the decoupling capacitor, so that the distribution of the clock units is more even. Moreover, since the capacitance of the decoupling capacitor filling unit has the effect of reducing the power supply voltage drop, the invention can effectively reduce the electromigration and/or the power supply voltage drop effect of the area where the clock unit is located.

Because the details and variations of the method and invention disclosed herein can be understood by those skilled in the art from the disclosure of the apparatus and invention disclosed herein, the repeated descriptions are omitted here for the sake of brevity and clarity. It should be noted that the shapes, sizes, proportions, and sequence of steps of the elements and steps shown in the drawings are illustrative only and not intended to be limiting, since those skilled in the art will understand the present invention.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

[ notation ] to show

110. 120 phase-locked loop

112. 122 clock tree

115. 125, 310, 410 clock unit

132. 134, 136, 138 registers

140 logic circuit

150 analog circuit

160 memory

170 input/output circuit

315 reserve space

415 decoupling capacitance

S210-S270, S510-S550, S610-S640

Claims (8)

1. A method of clock tree synthesis, comprising:

selecting a clock unit;

setting a reserved margin for the clock unit;

performing clock tree synthesis to generate the clock unit and a reserved space adjacent to the clock unit, wherein the size of the reserved space corresponds to the reserved margin;

arranging a decoupling capacitance filling unit in the reserved space, wherein the area and/or the capacitance value of the decoupling capacitance filling unit is related to the reserved margin; and

fixing the property of the clock unit and the property of the decoupling capacitance filling unit, wherein the reserved margin is set according to a driving force of the clock unit.

2. The method of claim 1, wherein the more the driving force is stronger, the more the margin is retained, and the less the driving force is weaker, the less the margin is retained.

3. The method of claim 1, wherein disposing the decoupling capacitor fill cell comprises:

filling a plurality of filling units in the clock unit and the area outside the reserved space;

removing the remaining margin;

filling the decoupling capacitor filling unit in the reserved space; and

removing the plurality of filling units.

4. The method of claim 1, further comprising:

performing routing and optimization after the attributes of the clock unit and the decoupling capacitor filling unit are fixed;

and filling a plurality of filling units after winding.

5. A method of clock tree synthesis, comprising:

determining a driving force of a clock unit;

determining a reserved space corresponding to the clock unit according to the driving force;

generating the clock unit and the reserved space, wherein the reserved space is adjacent to the clock unit;

arranging a decoupling capacitance filling unit in the reserved space, wherein the area and/or the capacitance value of the decoupling capacitance filling unit is related to the driving force; and

fixing the properties of the clock unit and the decoupling capacitor filling unit.

6. The method of claim 5, wherein the larger the driving force, the larger the retention space and the larger the decoupling capacitor fill cell, and the smaller the driving force, the smaller the retention space and the decoupling capacitor fill cell.

7. The method of claim 5, wherein disposing the decoupling capacitor fill cell comprises:

filling a plurality of filling units in the clock unit and the area outside the reserved space;

filling the decoupling capacitor filling unit in the reserved space; and

removing the plurality of filling units.

8. The method of claim 5, further comprising:

performing routing and optimization after the attributes of the clock unit and the decoupling capacitor filling unit are fixed;

and filling a plurality of filling units after winding.

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